KODENSHI KK74HC14AN

TECHNICAL DATA
KK74HC14A
Hex Schmitt-Trigger Inverter
The KK74HC14A is identical in pinout to the LS/ALS14. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
The KK74HC14A is useful to “square up” slow input rise and fall times.
Due to the hysteresis voltage of the Schmitt trigger, the KK74HC14A finds
applications in noisy environments.
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•
•
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC14AN
Plastic
KK74HC14AD
SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Output
A
Y
L
H
H
L
PIN 14 =VCC
PIN 7 = GND
1
KK74HC14A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP**
SOIC Package**
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr , tf
Input Rise and Fall Time
(Figure 1)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
-
No
Limit*
ns
* When VIN ≈50% VCC , ICC > 1mA
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC14A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Guaranteed Limit
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VOUT=0.1 V
⎢IOUT ⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
Minimum PositiveGoing Input Threshold
Voltage
VOUT=0.1 V
⎢IOUT ⎢≤ 20 µA
2.0
4.5
6.0
1.0
2.3
3.0
0.95
2.25
2.95
0.95
2.25
2.95
V
VT-max
Maximum NegativeGoing Input Threshold
Voltage
VOUT=VCC -0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
0.9
2.0
2.6
0.95
2.05
2.65
0.95
2.05
2.65
V
VT-min
Minimum NegativeGoing Input Threshold
Voltage
VOUT=VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VHmax *
Maximum Hysteresis
Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.2
2.25
3.0
1.2
2.25
3.0
1.2
2.25
3.0
V
VHmin *
Minimum Hysteresis
Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.5
0.2
0.4
0.5
0.2
0.4
0.5
0.2
0.4
0.5
V
VOH
Minimum High-Level
Output Voltage
VIN≤VT -min
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN≥VT +max
⎢IOUT⎢≤ 4mA
⎢IOUT⎢≤5.2mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Symbol
Parameter
VT+max
Maximum PositiveGoing Input Threshold
Voltage
VT+min
Test Conditions
VIN≤VT -min
⎢IOUT⎢≤4mA
⎢IOUT⎢≤5.2mA
VOL
Maximum Low-Level
Output Voltage
VIN≥VT +max
⎢IOUT⎢ ≤ 20 µA
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
1.0
10
40
µA
* VHmin>(VT+min)-(VT-max); VHmax=(VT+max)-(VT-min)
.
3
KK74HC14A
AC ELECTRICAL CHARACTERISTICS (CL=50pF, tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C
to
-55°C
≤85°C
≤125°C
Unit
tPLH, tPHL
Maximum Propagation Delay, Input A to
Output Y (Figures 1 and 2)
2.0
4.5
6.0
95
19
16
120
24
20
145
29
25
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
-
10
10
10
pF
CIN
CPD
Maximum Input Capacitance
Power Dissipation Capacitance (Per Inverter)
TA=25°C,VCC=5.0 V
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
22
Figure 1. Switching Waveforms
pF
Figure 2. Test Circuit
4
KK74HC14A
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
8
14
B
7
1
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
N
G
M
K
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
H
B
1
G
P
7
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
8.55
8.75
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
1.27
H
5.27
J
0°
8°
K
0.1
0.25
M
0.19
0.25
P
5.8
6.2
R
0.25
0.5
5