KODENSHI KK74HC651ADW

TECHNICAL DATA
KK74HC651A
Octal 3-State Bus Transceivers
and D Flip-Flops
High-Performance Silicon-Gate CMOS
The KK74HC651A is identical in pinout to the LS/ALS651. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These devices consist of bus transceiver circuits, D-type flip-flop, and
control circuitry arranged for multiplex transmission of data directly from
the data bus or from the internal storage registers. Direction and Output
Enable are provided to select the read-time or stored data function. Data
on the A or B Data bus, or both, can be stored in the internal D flip-flops
by low-to-high transitions at the appropriate clock pins (A-to-B Clock or
B-to-A Clock) regardless of the select or enable or enable control pins.
When A-to-B Source and B-to-A Source are in the real-time transfer
mode, it is also possible to store data without using the internal D-type
flip-flops by simulta-neously enabling Direction and Output Enable. In
this configuration each output reinforces its input. Thus, when all other
data sources to the two sets of bus lines are at high impedance, each set of
bus lines will remain at its last state.
The KK74HC651A has inverted outputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC651AN Plastic
KK74HC651ADW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 24=VCC
PIN 12 = GND
1
KK74HC651A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figures 2,3)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
2
KK74HC651A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limit
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VIH
Minimum HighLevel Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum HighLevel Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VIN=VIH or VIL
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤ 7.8 mA
VOL
Maximum LowLevel Output Voltage
VIN= VIL or VIH
⎢IOUT⎢ ≤ 20 µA
VIN=VIH or VIL
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤ 7.8 mA)
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
(Pins 1,2,3,21,22,and 23)
6.0
±0.1
±1.0
±1.0
µA
IOZ
Maximum ThreeState Leakage
Current
Output in High-Impedance
State
VIN= VIL or VIH
VOUT=VCC or GND,
I/O Pins
6.0
±0.5
±5.0
±10
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
8.0
80
160
µA
3
KK74HC651A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C
to
-55°C
≤85°C
≤125°C
Unit
tPLH, tPHL
Maximum Propagation Delay, Input A to Output
B (or Input B to Output A)
(Figures 2,3 and 9)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
tPLH, tPHL
Maximum Propagation Delay, A-to-B Clock to
Output B (or B-to-A Clock to Output A)
(Figures 1 and 9)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
tPLH, tPHL
Maximum Propagation Delay, A-to-B Source to
Output B (or B-to-A Source to Output A)
(Figures 4 and 9)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
tPLZ, tPHZ
Maximum Propagation Delay , Direction or
Output Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
tPZL, tPZH
Maximum Propagation Delay , Direction or
Output Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Maximum Input Capacitance
-
10
10
10
pF
Maximum Three-State I/O Capacitance
(Output in High-Impedance State
-
15
15
15
pF
CIN
COUT
CPD
Power Dissipation Capacitance (Per Channel)
Typical @25°C,VCC=5.0 V
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
60
pF
4
KK74HC651A
TIMING REQUIREMENTS (Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C to-55°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Input A to
A-to-B Clock (or Input B to B-to-A
Clock) (Figure 7)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
th
Minimum Hold Time, A-to-B Clock
to Input A (or B-to-A Clock to
Input B) (Figure 7)
2.0
4.5
6.0
25
5
5
30
6
5
40
8
7
ns
tw
Minimum Pulse Width, A-to-B Clock
(or B-to-A Clock)
(Figure 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tr, tf
Maximum Input Rise and Fall Times
(Figures 2 and 3)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
TIMING DIAGRAM
5
KK74HC651A
FUNCTION TABLE
Dir.
OE
L
H
CAB CBA SAB SBA
X
X*
L
L
X
X
X*
X*
X
X*
A
B
INPUTS
INPUTS
Both the A bus and the B bus are inputs.
X
X
Z
Z
The output functions of the A and B bus
are disabled.
X
X
INPUTS
INPUTS
Both the A and B bus are used for inputs
to the internal flip-flops. Data at the bus
will be stored on low to high transition of
the clock inputs.
OUTPUTS
INPUTS
The A bus are outputs and the B bus are
inputs.
X
L
H
L
L
H
The data at the B bus are displayed at the
A bus.
X
L
H
L
L
H
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X
H
Qn
X
The data stored to the internal flip-flops,
are displayed at the A bus.
X
H
L
H
H
L
The data at the B bus are stored to the
internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the A bus.
INPUTS
X
H
H
X
L
X
OUTPUTS The A bus are inputs and the B bus are
outputs.
X*
L
X
H
L
L
H
The data at the A bus are displayed at the
B bus.
X*
L
X
H
L
L
H
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X*
H
X
X
Qn
The data stored to the internal flip-flops
are displayed at the B bus.
X*
H
X
H
L
L
H
The data at the A bus are stored to the
internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the B bus.
OUTPUTS
H
FUNCTION
X
OUTPUTS Both the A bus and the B bus are outputs
H
H
Qn
Qn
The data stored to the internal flip-flops
are displayed at the A and B bus
respectively.
H
H
Qn
Qn
The output at the A bus are displayed at
the B bus, the output at the B bus are
displayed at the A bus respec.
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION
OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW
TO TRANSITION OF THE CLOCK INPUTS
6
KK74HC651A
SWITCHING DIAGRAMS
Figure 1. Switching Waveforms
Figure 2. A Data Port = Input, B Data Port =
Output
Figure 3. A Data Port = Output, B Data Port =
Input
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
7
KK74HC651A
Figure 6. Switching Waveforms
Figure 7. Switching Waveforms
Figure 9. Test Circuit
Figure 10. Test Circuit
8
KK74HC651A
EXPANDED LOGIC DIAGRAM
9
KK74HC651A
N SUFFIX PLASTIC DIP
(MS - 001AF)
A
Dimension, mm
13
24
Symbol
MIN
MAX
A
31.24
32.51
B
6.1
7.11
B
12
1
C
F
L
5 .33
D
0.36
0.56
F
1.14
1.78
C
-T- SEATING
G
2.54
H
7.62
PLANE
N
G
M
K
H
D
J
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 013AD)
Dimension, mm
A
24
13
H
B
1
P
12
G
R x 45
C
-TK
D
SEATING
PLANE
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
J
F
Symbol
MIN
MAX
A
15.2
15.6
B
7.4
7.6
C
2.35
2.65
D
0.33
0.51
F
0.4
1.27
G
1.27
H
9.53
M
J
0°
8°
K
0.1
0.3
M
0.23
0.32
P
10
10.65
R
0.25
0.75
10