NanoAmp Solutions, Inc.
670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
N32T1630C1C
32Mb Ultra-Low Power Asynchronous CMOS Pseudo SRAM
w/ Page Mode Operation (2M x 16 bit)
Overview
Features
The N32T1630C1C is an integrated memory
device containing a 32 Mbit SRAM built using a
self-refresh DRAM array organized as 2,097,152
words by 16 bits. The device is designed and
fabricated using NanoAmp’s advanced CMOS
technology to provide both high-speed
performance and ultra-low power. It is designed to
be identical in operation and interface to standard
6T SRAMS. Byte controls (UB and LB) allow the
upper and lower bytes to be accessed
independently and can also be used to deselect
the device. The N32T1630C1C offers a very high
speed page mode operation for improved
performance and operating power savings. The
device is optimal for various applications where
low-power is critical such as battery backup and
hand-held devices. Also included are several
power savings modes: a deep sleep mode and
partial array refresh mode where data is retained in
a portion of the array. The device can operate over
a very wide temperature range of -25oC to +85oC
and is available in a JEDEC standard VFRBGA
package compatible with other standard 2Mb x 16
SRAMs.
• Dual voltage for Optimum Performance:
VccQ - 2.7 to 3.6 Volts
Vcc - 2.7 to 3.6 Volts (Vcc ≤ VccQ)
• Fast random access time
70ns at 2.7V
• Very fast page mode access time
25ns page cycle and access
• Very low standby current
80µA V (Typical)
• Very low operating current
1.0mA at 1µs (Typical)
• Simple memory control
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Automatic power down to standby mode
• PAR and RMS power saving modes
• Deep sleep option
• TTL compatible three-state output driver
Product Family
Package
Type
Part Number
Operating
Temperature
N32T1630C1CZ 48-VFRBGA -25oC to +85oC
Power
Supply
Speed
2.7V - 3.6V (VCC)
70ns
Standby
Current (ISB),
Max
Operating
Current (Icc),
Max
135 µA @ 3.3V 3 mA @ 1MHz
Pin Configuration (Top View)
Pin Descriptions
1
Pin Name
Pin Function
A0-A20
Address Inputs
WE
Write Enable Input
2
3
4
5
6
A
LB
OE
A0
A1
A2
ZZ
B
I/O8
UB
A3
A4
CE
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
VSSQ I/O11
A17
A7
I/O3
VCC
E
VCCQ I/O12
DNU/
VSS
A16
I/O4
VSS
F
I/O14 I/O13
A14
A15
I/O5
G
I/O15
H
A18
A19
A8
A12
A9
A13
A10
WE
A11
48 Ball VFRBGA
6 x 8 mm
CE
Chip Enable Input
OE
Output Enable Input
UB,LB
Byte Enable Inputs
ZZ
Deep Sleep Input
I/O0-I/O15
Data Inputs/Outputs
I/O6
VCC
Core Power
I/O7
VCCQ
I/O Power
A20
VSS
Ground
VSSQ
I/O Ground
DNU
Do Not Use
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
N32T1630C1C
NanoAmp Solutions, Inc.
Functional Block Diagram
Word
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Page
Address
Inputs
A4 - A20
Page
Address
Decode
Logic
CE
ZZ
WE
OE
UB
LB
Input/
Output
Mux
and
Buffers
128K page
x 16 word
x 16 bit
RAM Array
I/O0 - I/O7
I/O8 - I/O15
Control
Logic
Functional Description
CE
ZZ
WE
OE
UB
LB
I/O0 - I/O151
MODE
POWER
H
H
X
X
X
X
High Z
Standby2
Standby
Standby
X
L
H
H
X
X
H
H
High Z
Standby2
L
X3
L1
L1
Data In
Write
Active
L1
L1
Data Out
Read
Active
L
H
H
L
L
H
H
H
L
L
High Z
Active
Active
X
L
X
X
X
X
High Z
Deep Sleep
Deep Sleep
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item
Symbol
Test Condition
Input Capacitance
CIN
CI/O
I/O Capacitance
Max
Unit
VIN = 0V, f = 1 MHz, TA = 25oC
6
pF
25oC
8
pF
VIN = 0V, f = 1 MHz, TA =
Min
1. These parameters are verified in device characterization and are not 100% tested
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
N32T1630C1C
NanoAmp Solutions, Inc.
Absolute Maximum Ratings1
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VIN,OUT
–0.2 to VCCQ+0.3
V
Voltage on VCC Supply Relative to VSS
VCC
–0.2 to 4.0
V
Power Dissipation
PD
500
mW
Storage Temperature
TSTG
–55 to 125
o
Operating Temperature
TA
-25 to +85
oC
Soldering Temperature and Time
TSOLDER
10sec(Lead Only)
oC
240oC,
C
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Min.
Typ1
Max
Unit
2.7
3.0
3.6
V
2.7
3.0
3.6
V
0.8VCCQ
VCCQ+0.2
V
–0.2
0.4
V
IOL = -0.2mA
0.2
V
ILI
VIN = 0 to VCC
0.5
µA
Output Leakage Current
ILO
OE = VIH or Chip Disabled
0.5
µA
Read/Write Operating Supply
Current @ 1 µs Cycle Time2
ICC1
VCC= 3.3V, VIN=CMOS levelsChip Enabled, IOUT = 0
3.0
mA
Read/Write Operating Supply
Current @ 70 ns Cycle Time2
ICC2
VCC= 3.3V, VIN=CMOS levels
Chip Enabled, IOUT = 0
25.0
mA
Maximum Standby Current3
ISB1
VCC= 3.3V, VIN=CMOS levels
Chip Disabled
135.0
µA
Item
Symbol
Test Conditions
Supply Voltage
VCC
Supply Voltage for I/O
VCCQ
Input High Voltage
VIH
Input Low Voltage
VIL
Output High Voltage
VOH
IOH = 0.2mA
Output Low Voltage
VOL
Input Leakage Current
VCC = VCCQ (Note 4)
0.8VccQ
V
80
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to
drive output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (either CE high or both UB and LB high). In order to achieve low
standby current all inputs must be within 0.2V of either VCC or VSS
4. During testing, Vcc = VccQ.
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
3
N32T1630C1C
NanoAmp Solutions, Inc.
Power Up Initialization Timing
2.7V
Device Initialization
VCC
VCCQ
Device Ready for
Normal Operation
100µs
The device will require 100 µs to complete its self-initialization process. During the initialization period, CE#
pin should remain HIGH.
FIGURE 1: Output Load Circuit
VCCQ
14.5K
I/O
14.5K
30 pF
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
4
N32T1630C1C
NanoAmp Solutions, Inc.
Timing
Item
Symbol
Read Cycle Time
tRC
Address Access Time
tAA
Page Mode Read Cycle Time
tPC
Page Mode Access Time
tPA
70ns
Min.
Max.
Units
70
25
ns
70
ns
20000
ns
25
ns
Chip Enable to Valid Output
tCO
70
ns
Output Enable to Valid Output
tOE
20
ns
Byte Select to Valid Output
tLB, tUB
70
ns
Chip Enable to Low-Z output
tLZ
10
ns
Output Enable to Low-Z Output
tOLZ
5
ns
Byte Select to Low-Z Output
tLBZ, tUBZ
10
Chip Disable to High-Z Output
tHZ
0
20
ns
Output Disable to High-Z Output
tOHZ
0
20
ns
Byte Select Disable to High-Z Output
tLBHZ, tUBHZ
0
20
ns
Output Hold from Address Change
tOH
5
ns
Write Cycle Time
tWC
70
ns
Page Mode Write Cycle Time
tPWC
25
Chip Enable to End of Write
tCW
60
ns
Address Valid to End of Write
tAW
60
ns
Byte Select to End of Write
tLBW, tUBW
60
Write Pulse Width
tWP
55
ns
20000
ns
ns
20000
ns
Address Setup Time
tAS
0
ns
Write Recovery Time
tWR
0
ns
Write to High-Z Output
tWHZ
20
ns
Data to Write Time Overlap
tDW
25
ns
Page Mode Data to Write Time Overlap
tPDW
20
ns
Data Hold from Write Time
tDH
0
ns
Page Mode Data Hold from Write Time
tPDH
0
ns
End Write to Low-Z Output
tOW
5
ns
CE Precharge
tCP
10
ns
Maximum Page Mode Cycle
tPGMAX
20000
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
ns
5
N32T1630C1C
NanoAmp Solutions, Inc.
Timing of Read Cycle (CE = OE = VIL, WE = VIH)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle (WE=VIH)
tRC
Address
tAA
tHZ
CE
tCO
tLZ
tOHZ
tOE
OE
tOLZ
tLB, tUB
LB, UB
tLBLZ, tUBLZ
Data Out
High-Z
tLBHZ, tUBHZ
Data Valid
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
6
N32T1630C1C
NanoAmp Solutions, Inc.
Timing Waveform of Page Mode Read Cycle (WE = VIH)
tPGMAX
Page Address (A4 - A20)
tRC
tPC
Word Address (A0 - A3)
tAA
tPA
tHZ
CE
tCO
tOE
tOHZ
OE
tOLZ
LB, UB
Data Out
tLBHZ, tUBHZ
tLB, tUB
High-Z
tLBLZ, tUBLZ
tPGMAX means any page address (A4-A20) must be changed at least once in a 20us period
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
7
N32T1630C1C
NanoAmp Solutions, Inc.
Timing Waveform of Write Cycle (WE Control)
tWC
Address
Address
tWR
tAW
CE
tCW
tLBW, tUBW
LB, UB
tAS
tWP
WE
tDW
High-Z
tDH
Data Valid
Data In
tWHZ
tOW
High-Z
Data Out
Timing Waveform of Write Cycle (CE Control)
tWC
Address
tAW
tWR
tCW
CE
tAS
tLBW, tUBW
LB, UB
tWP
WE
tDW
Data Valid
Data In
tLZ
Data Out
tDH
tWHZ
High-Z
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
8
N32T1630C1C
NanoAmp Solutions, Inc.
Timing Waveform of Page Mode Write Cycle
tPGMAX
Page Address
(A4 - A20)
tPWC
tWC
Word Address
(A0 - A3)
CE
tAS
tCP
tCW
tWP
WE
tLBW, tUBW
LB, UB
tDW
Data Out
tDH
tPDW
tPDH
tPDW
tPDH
High-Z
tPGMAX means any page address (A4-A20) must be changed at least once in a 20us period
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
9
NanoAmp Solutions, Inc.
N32T1630C1C
Power Savings Modes
The N32T1630C1C has several power savings modes and the three modes are:
Reduced Memory Size
Partial Array Refresh
Deep Sleep Mode
The operation of the power saving modes is controlled by setting the Variable Address Register (VAR).
This VAR is shown in Figure 8 and is used to enable/disable the various low power modes.
The VAR is set by using the timings defined in figure 9. The register must be set in less then 1us after ZZ is
enabled low.
1) Reduced Memory Size (RMS)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and
array size are determined by the settings in the VA register. The VA register is set according to the timings
of Figure 9 and the bit setting of Table 12. The RMS mode is enabled at the time of ZZ transitioning high
and the mode remains active until the register is updated. To return to the full 32Mb address space, the VA
register must be reset using the previously defined procedures.
2) Partial Array Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a 8Mb or 16Mb portion of the
array. The mode and array partition to be refreshed are determined by the settings in the VAR register. The
VAR register is set according to the timings of Figure 9 and the bit settings of Table 11. In this mode, when
ZZ is taken low, only the portion of the array that is set in the register is refreshed. The operating mode is
only available during standby time and once ZZ is returned high, the device resumes full array refresh. All
future PAR cycles will use the contents of the VA register. To change the address space of the PAR mode,
the VA register must be reset using the previously defined procedures.
There are two different device versions that have different default settings for the PAR mode.
In the first version, the default state for the ZZ enable/disable register will be ZZ enabled where ZZ low will
initiate a deep sleep mode after 1us. This device is referred to as Deep Sleep Active, or DSA device. In the
second version, the default state for the ZZ register will be such that ZZ low will put the device into PAR
mode after 1us and never initiate a deep sleep mode unless appropriate register is updated. This device is
referred to as Deep Sleep Inactive, or DSI device. In either device, once the SRAM enters Deep Sleep
Mode, the VAR contents are destroyed and the default register settings are reset.
3) Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep
Sleep is entered by bringing ZZ low. After 1 us, if the VAR register corresponding to A4 is not set to Deep
Sleep Disabled, the device will enter Deep Sleep Mode. The device will remain in this mode as long as ZZ
remains low.
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
10
N32T1630C1C
NanoAmp Solutions, Inc.
FIGURE 2: Variable Address Register
A20 - A5
A4
A3
A2
A1
Array mode for ZZ
Reserved for future
Preferably set to all 0
Array section
0 = PAR mode (default)
1 = RMS mode
1
1
0
0
ZZ Enable/Disable
0 = Deep Sleep Enabled
(default for DSA device)
1 = Deep Sleep Disabled
(default for DSI device)
A0
Array half
1 = 1/4 array
0 = 1/2 array
1 = Reserved
0 = Full array
(default)
0 = Bottom array (default)
1 = Top array
FIGURE 3: Variable Address Register (VAR) Update Timings
tWC
A0-A4
tAW
CE
WE
tAS
tWR
tWP
tCDZZ
tZZWE
ZZ
tLBW, UBW
LB, UB
FIGURE 4: Deep Sleep Mode - Entry/Exit Timings
tZZMIN
ZZ
tCDZZ
tR
CE or
LB, UB
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
11
N32T1630C1C
NanoAmp Solutions, Inc.
Table 1: VAR Update and Deep Sleep Timings
Item
Symbol
Min
Max
Unit
1000
ns
PAR and RMS ZZ low to WE low
tzzwe
Chip (CE, UB/LB) deselect to ZZ low
tcdzz
Deep Sleep Mode
tzzmin
10
us
tr
200
us
Deep Sleep Recovery
0
ns
TABLE 2: Address Patterns for PAR (A3 = 0, A4 = 1)
A2
A1
A0
0
0
1
1
1
1
1
1
1
0
1
0
Active Section
One-quarter of die
One-half of die
One-quarter of die
One-half of die
Address space
000000h - 07FFFFh
000000h - 0FFFFFh
180000h - 1FFFFFh
100000h - 1FFFFFh
Size
512Kb x 16
1Mb x 16
512Kb x 16
1Mb x 16
Density
8Mb
16Mb
8Mb
16Mb
TABLE 3: Address patterns for RMS (A3 = 1, A4 = 1)
A2
A1
A0
0
0
0
1
1
1
1
1
0
1
1
0
1
0
0
1
0
0
Active Section
One-quarter of die
One-half of die
Full die
One-quarter of die
One-half of die
Full die
Address space
Size
000000h - 07FFFFh
000000h - 0FFFFFh
000000h - 1FFFFFh
180000h - 1FFFFFh
100000h - 1FFFFFh
000000h - 1FFFFFh
512Kb x 16
1Mb x 16
2Mb x 16
512Kb x 16
1Mb x 16
2Mb x 16
Density
8Mb
16Mb
32Mb
8Mb
16Mb
32Mb
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
12
N32T1630C1C
NanoAmp Solutions, Inc.
TABLE 4: Low Power ICC Characteristics for N32T1630C1C
Item
Symbol
PAR Mode Standby
Current
IPAR
RMS Mode
Standby Current
IRMSSB
Deep Sleep Current
IZZ
Array
Partition
Test
VIN = VCC or 0V,
Chip Disabled, tA= 85oC
VIN = VCC or 0V,
Chip Disabled, tA=
85oC
VIN = VCC or 0V,
1/4 Array
1/2 Array
8Mb Device
16Mb Device
Typ
Max
Unit
tbd
tbd
tbd
tbd
10
uA
uA
uA
o
Chip in ZZ mode, tA= 85 C
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
13
N32T1630C1C
NanoAmp Solutions, Inc.
VFRBGA Package Dimension
0.23±0.05
0.90±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.30±0.05 DIA.
E
2. SEATING PLANE - Z
0.15 Z
0.05
TOP VIEW
Z
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
A1 BALL PAD
MAXIMUM SOLDER BALL DIAMETER.
CORNER
PARALLEL TO PRIMARY Z.
SD
e
SE
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Dimensions (mm)
e = 0.75
D
6±0.10
SD
SE
J
K
BALL
MATRIX
TYPE
0.375
0.375
1.125
1.375
FULL
E
8±0.10
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
14
N32T1630C1C
NanoAmp Solutions, Inc.
Ordering Information
N32T1630C1CZ-XX I
Performance
70 = 70ns
Note: Add -T&R following the part number for Tape and Reel. Orders will be
considered in tray if not noted.
Revision History
Revision
Date
Change Description
A
July 2004
Initial Release
B
July 2004
General Update
C
August 2004
Changed Ball (E3) from Vss to DNU/VSS
Changed Max Vcc/VccQ from 3.3V to 3.6V
© 2003 Nanoamp Solutions, Inc. All rights reserved.
NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications.
NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application
or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp
product may be expected to result in significant injury or death, including life support systems and critical medical instruments.
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
15