November 1995 LMC2626 CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems General Description Features The LMC2626 integrated circuit is specifically developed for a row inversion TFT FPD system architecture. It is designed only to be used in conjunction with National’s LM2625 switching regulator chip. Built on National’s advanced CMOS CS80 process, this chip generates a high-power, precision square-wave from a digital sync signal. The chip also contains thermal shutdown circuitry, system shutdown circuitry, and a low drop-out voltage regulator to generate a 4.2 volt supply from an externally applied reference voltage of 1.227V. Y Connection Diagram Pin Description Y Y Y Y Y Y Y Y Used in conjunction with LM2625 chip High output current buffer Low buffer on resistance System shutdown control LDO voltage regulator LDOR dropout 0.3V maximum at 150 mA Thermal shutdown/short circuit protection External reference required for LDOR VREF pin converts to a digital pin to shutdown LM2625 8-Pin SO Pin Ý Pin Name Description 1 VREF 1.218V to 1.242V Ext. Reference from LM2625 (see Note 8) 2 SD System Shutdown input pin for LMC2626 and LMC2625 3 SYNC Digital input square wave from FPD controller 4 GND Ground 5 P5V Precision Regulated a 5V Supply 6 VOUT Power Buffer Output 7 VIN FPD System Supply ( a 4.5V to a 5.5V) 8 VSH Low Drop-Out Voltage Regulator Output TL/H/12541 – 1 Top View Ordering Information Package Temperature Range b 40§ C to a 85§ C NSC Drawing Transport Media 8-Pin SO LMC2626IM M08A Rail Tape and Reel C1996 National Semiconductor Corporation TL/H/12541 RRD-B30M26/Printed in U. S. A. LMC2626 CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems PRELIMINARY Absolute Maximum Ratings (Note 1) Operating Ratings (Note 1) ESD Tolerance 2 kV HBM, 200V MM (Note 4) VIN Supply Voltage P5V Supply Voltage (Note 5) 4.8V s P5V s 5.2V Junction Temperature Range Ambient Temperature Range b 25§ C to a 125§ C b 40§ C to a 85§ C Sync Input Voltage P5V 6.3V Supply Voltage (VIN, P5V) Continuous Total Power Dissipation (Note 1) Lead Temperature (less than 10 sec) 260§ C b 65§ C to a 150§ C Storage Temperature Range Junction Temperature 150§ C 4.5V s VIN s 5.5V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for b20§ C s TA s a 85§ C, P5V e 5V and 4.5V s VIN s 5.5V, VREF e 1.227V SYNC(OPEN), SD(OPEN) k P5V e VIN e 5V VSH LDO Voltage Regulator (Notes 7, 10, 11) Symbol VO(VREF) Parameter VREF Voltage Level in Shutdown Min Typ (Note 9) 4.00 4.76 b 40.0 b 13.3 b5 mA 4.10 4.20 4.30 V 4 126 mV 0.17 0.30 V Conditions SD e 0V IVREF e b1 mA VIN e 5V IVREF DC Current from VREF Pin VSH Output Voltage on VSH Pin (see Note 2) 4.5V s VIN s 5.5V 20 mA s IL s 150 mA 1.218 s VREF s 1.242 DVSH Variation of VSH over Temperature 4.5V s VIN s 5.5V 20 mA s IL s 150 mA VDO LDOR Voltage Dropout (VIN – VSH) IL e 150 mA IS(VIN) VIN Supply Current 230 Max Units V 394 500 mA Load Regulation of LDO Voltage Regulation 4.5V s VIN s 5.5V 20 mA s IL s 150 mA 0.002 0.015 %/mA Line Regulation of LDOR 4.5V s VIN s 5.5V 20 mA s IL s 150 mA 0.24 0.95 %/V TSD Thermal Shutdown Threshold (see Note 8) IOUT Output Load Current (see Note 2) 160 §C 300 mA Shutdown Control (Note 8) Symbol Parameter Conditions IIL(SD) Low Level Input Current for SD Pin VIN e 5V SD e 0V IIH(SD) High Level Input Current for SD Pin SD e 5V Is(SD) VIN Supply Current in Shutdown Mode Cin(SYNC) Input Capacitance at SYNC Pin (Note 6) Min Typ (Note 9) Max Units b 300 b 217 b 150 mA 310 1000 nA 285 400 mA 180 SYNC e 5V TA e 27§ C 2 20 pF DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for b20§ C s TA s a 85§ C, P5V e 5V and 4.5V s VIN s 5.5V, VREF e 1.227V SYNC(OPEN), SD(OPEN) k P5V e VIN e 5V (Continued) Buffer Symbol Parameter Conditions Min Typ (Note 9) 4.997 4.999 VOUT Peak to Peak Output Voltage Swing or VOUT SYNC e 5Vpp (no load) VOL Low Level Output Voltage SYNC e 0V (No Load) 0.2 VOH High Level Output Voltage SYNC e 5V (No Load) 4.999 DVOUT Variation of VOUT Over Temperature 0.2 1 VIH SYNC, SD High Level Input Voltage 3.5 5 VIL SYNC, SD Low Level Input Voltage IIL(SYNC) Low Level Input Current for SYNC SYNC e 0V IIH(SYNC) High Level Input Current for SYNC SYNC e 5VDC IOUT-AVE VOUT Maximum Average Load Current from (see Note 2) SYNC e 5VPP RON N-Channel On Resistance IL e 150 mA TA e 27§ C RON P-Channel On Resistance RON Matching Is Max Units V 2 mV V 3 mV V 0 1.5 V 5.0 42 1000 nA 170 215 275 mA 100 mA 0.9 1.5 X IL e 150 mA TA e 27§ C 0.7 1.2 X On Resistance IL e 150 mA TA e 27§ C 0.18 0.6 X Supply Current from P5V No SYNC 355 950 mA 3 200 AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TA e 27§ C, VIN e e P5V e 5V. Other conditions are shown in the test circuit. Conditions that deviate from those shown in the test circuit are listed in the conditions column. Symbol Parameter Conditions ts(OUT) Settling Time for VOUT To 98% p-p VOUT, VIN e 5V (see Note 3) Min Typ (Note 9) Max Units 5.0 ms Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions the device is intended to be functional, but device parameter specifications may not be guaranteed under these conditions. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The typical junction-ambient thermal resistance of the molded plastic SO(M) package is 155§ C/W. Therefore the maximum current for the buffer and voltage regulator are limited to the maximum total power dissipation that the package can allow in order to keep the die comfortably below the maximum operating junction temperature of 125§ C. Note 3: The settling time of the Power Buffer is mostly dependent upon the TFT effective series RC load. The measurement of the settling time is taken for the application when driving an all black display. The number in the datasheet reflects a series RC load (R e 6.8X and C e 0.22 mF). Note 4: Human Body Model 100 pF and 1.5 kX. Machine Model 0X. Note 5: The precision of the P5V supply determines the output voltage swing precision of the buffer for very small loads. The operating range of P5V in this datasheet assumes a g 4% error in VOUT p-p such that the total error of the signal at the output of the buffer never exceeds g 5%. Note 6: This capacitance is dominated by the ESD protection zeners connected to the SYNC pin. Note 7: It is important to understand that the load current of the low drop-out voltage regulator must not drop below 2 mA. Otherwise, the internal error amplifier will not have sufficient drive capability to the large series pass transistor. If load requirements from the FPD system is less than 2 mA, an external preIoad resistor must be connected from VSH to ground in order to satisfy the previously mentioned load requirements. Note 8: The thermal shutdown mode of the voltage regulator and the system shutdown mode are identical. When either of the two functions are enabled, two results occur. The pass transistor of the voltage regulator is shut off and The VREF pin of the LMC2626 is pulled up to the VIN supply to shutdown the LM2625 switching regulator. Note 9: Typical values represent the most likely parametric norm. Note 10: The typical closed loop voltage gain of the low drop-out voltage regulator is 3.44(10.7 dB). Note 11: The minimum load current of the voltage regulator is a specific parameter used to guarantee that the regulated output voltage of the LDO regulator stays within the limits specified in the datasheet for 1.216V k VREF k 1.242V. For applications requiring minimum load current less than 20 mA, regulated output voltage limits of the voltage regulator and VREF voltage range must be carefully determined by characterizing the change in regulated output voltage at the minimum load current needed. 4 5 LMC2626 CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems Physical Dimensions inches (millimeters) 8-Lead (0.150× Wide) Molded Small Outline Package, JEDEC Order Number LMC2626IM NS Package M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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