MM5034/MM5035 Octal 80-Bit Static Shift Register General Description The MM5034 octal 80-bit shift register is a monolithic MOS integrated circuit utilizing N-channel low threshold enhancement mode and ion-implanted depletion mode devices. The MM5034 is designed for use in computer display peripherals. All inputs and outputs are TTL compatible. The clocks and recirculate logic are internal to reduce system component count, and TRI-STATEÉ output buffers provide bus interface. Because of its N-channel characteristics, single 5V power supply operation is required. Simple interface to the NSC CRT DP8350 controller and character generator to incorporate an entire CRT terminal is feasible with the MM5034. The MM5034 is available in a 22-lead dual-in-line package. The MM5035 is a 20-pin version of the MM5034 with the TRI-STATE output select feature omitted, for a simple data in/data out operation. Features Y Y Y Y Y Y Single 5V power supply Internal clocks High speed and static operation TRI-STATE output buffer Recirculate and outut select independent TTL compatible Applications Y Y CRT displays Computer peripherals Connection Diagrams Dual-In-Line Package Dual-In-Line Package TL/F/10821 – 2 TL/F/10821 – 1 Top View Order Number MM5034N See NS Package Number N22A Top View Order Number MM5035N See NS Package Number N20A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/10821 RRD-B30M105/Printed in U. S. A. MM5034/MM5035 Octal 80-Bit Static Shift Register April 1990 Absolute Maximum Ratings Power Dissipation If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7 VDC Input Voltage 7 VDC 750 mW Storage Temperature Range b 65§ C to a 150§ C Lead Temperature (Soldering, 10 sec.) 300§ C Electrical Characteristics VDD e 5V g 5%, TA e 0§ C to a 70§ C Parameter Conditions Min Clock Input Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage 2.2 Data and Control Inputs Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage 2.2 Data, Clock and Control Inputs Logical ‘‘1’’ Input Current Input Capacitance Outputs Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage TRI-STATE Output Current VIN e 5V VIN e 2.5V Max Units 0.8 V V 0.8 V V 5.0 8.0 mA pF 0.4 b 5.0 5.0 V V mA mA 60 90 mA 40 3.0 10,000 % 50 80 185 185 5.0 185 MHz ns ns ns ns ns ns ns ms ns 5.0 IOUT e 100 mA IOUT e 1.6 mA VOUT e 5V VOUT e 0V 2.4 Supply Current Timing Clock Frequency Clock Pulse Width High Clock Pulse Width Low Output Rise and Fall Time (tr, tf) Set-Up Time Hold Time Output Enable Time Output Disable Time Clock Rise and Fall Time Output Delay, (tPD) Typ 2.8 0.25 0 125 125 (Figure 1) (Note 1) (Figure 1) (Figure 1) (Figure 1) (Figure 1) (Figure 1) (Figure 1) 100 0 Note 1: The clock input must be a low level for DC storage. Minimum width assumes 10 ns tr and tf. Recirculate and TRI-STATE Operation shift cell back to the input of the first shift cell for each of the 8 registers. For the output to be in the TRI-STATE mode output-select should be at the logical ‘‘1’’ level. Recirculate is used to maintain data in the shift register after it has been loaded. While the shift register is being loaded, Recirculate must be at a logical ‘‘0’’. When the loading is completed, Recirculate should be brought to a logical ‘‘1’’. This disables the data input and feeds the output of the last 2 AC Test Circuits and Switching Time Waveforms tPD1 TL/F/10821–3 tPD0 TL/F/10821–4 TL/F/10821 – 5 FIGURE 1 Typical Application TL/F/10821 – 6 FIGURE 2. CRT System Diagram Using the MM5034, MM5035 as a Line Buffer with DMA 3 MM5034/MM5035 Octal 80-Bit Static Shift Register Physical Dimensions inches (millimeters) 20-Lead Molded Dual-In-Line Package (N) Order Number MM5035N NS Package Number N20A 22-Lead Molded Dual-In-Line Package (N) Order Number MM5034N NS Package Number N22A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.