April 1999 LMX5080 PLLatinum™ 2.7 GHz Low Power Dual Modulus Prescaler for RF Personal Communications General Description Features The LMX5080 integrated dual modulus prescaler, is designed to be used in a synthesized local oscillator for 2.5 GHz wireless transceivers. It is fabricated using National’s 0.5µ ABiCV silicon BiCMOS process. The LMX5080 contains three dual modulus prescalers. Either a 128/130, 256/158 or a 512/514 prescaler can be selected for up to 2.7 Gz RF input frequencies. The prescaler inputs can be driven either differentially, or single ended with the use of a coupling capacitor on one of the inputs to ground. The LMX5080 CMOS output is optimized to generate very stable, low switching noise output signals. The LMX5080 prescaler can be used in conjunction with a low frequency Phase Lock Loop to form a frequency synthesizer suitable for UHF transceivers. Supply voltage can range from 2.7V to 5.5V. The LMX5080 features low current consumption; typically 7.0 mA at 5V VCC n n n n 2.7V to 5.5V operation Low current consumption: 7 mA (typ) @ 5V −40˚C to +85˚C low noise CMOS output Selectable dual modulus prescaler 128/130 256/258 512/514 n 8-pin small package outline (SOP) Applications n 2.5 GHz wireless communications systems (ISM) n Direct Broadcast Satellite systems (DBS) n Cable TV tuners (CATV) The LMX5080 is available in a 8-pin Small Outline (SOP) surface mount plastic package. Functional Block Diagram DS100940-1 PLLatinum™ is a trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100940 www.national.com LMX5080 PLLatinum 2.7 GHz Low Power Dual Modulus Prescaler for RF Personal Communications PRELIMINARY Connection Diagram Small Outline Package (SOP) DS100940-2 NS Package Number M08A Order Number LMX5080M, LMX5080MX Pin Descriptions Pin No. Pin Name I/O Description 1 IN I RF small signal prescaler input. Small signal input from the voltage controlled oscillator 2 VCC — Power Supply voltage input may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 3 SW1 I Divide Ratio Control. CMOS logic input. Pin functionality is described in the Modulus Control Truth Table. 4 OUT O Prescaler Output. CMOS level output for connection to low frequency PLL input. 5 GND — 6 MC I Modulus Control Input. High impedance CMOS logic input. Pin functionality is described in the Modulus Control Truth Table. 7 SW2 I Divide Ratio Control. High impedance CMOS logic input. Pin functionality is described in the Modulus Control Truth Table. 8 IN I RF small signal prescaler complementary input. In single-ended mode, a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. The IN and IN can be driven differentially when the bypass capacitor is omitted. www.national.com Ground for analog and digital signals. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Value Parameter Value Parameter Symbol Min VCC −0.3 Power Supply Voltage Typ Symbol Min Max Units Power Supply Voltage VCC 6.5 V Operating Temperature TA Voltage on any pin with GND = 0V Vi −0.3 VCC+0.3 V Storage Temperature Range TS −65 +1.50 ˚C Lead Temp. (solder 4 sec) TL +2.60 ˚C Typ Max Units 2.7 5.5 V −40 +85 ˚C Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. Electrical Characteristics document specific minimum and/or maximum performance values at specified test conditions and are guaranteed. Typ or Typical values are for informational purposes only which are based on design parameters or device characterization and are not guaranteed. Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should only be done on ESDfree workstations. Electrical Characteristics (VCC = 5.0V, TA = −40˚C to +85˚C except as specified) (Note 1) Symbol Parameter ICC Power Supply Current VOH Output Amplitude VOL fin Input Frequency Condition Value Min Typ Max 7 ZL = 100 kΩ//10 pF VCC = 2.7V to 5.5V AC coupled. VCC = 2.7V to 5.5V VCC = 2.7V to 5.5V Units mA 0.9 x VCC V 0.1 x VCC V 100 2700 MHz −15 +4 dBm 0.1 25 MHz Pfin Operational Input Signal Amplitude fout Output Frequency VIH High-level Input Voltage (MC, SW1, SW2) VIL Low-level Input Voltage (MC, SW1, SW2) IIH High-level Input Current (MC, SW1, SW2) VIH = 0.7 x VCC ±1 uA IIL Low-level Input Current (MC, SW1, SW2) VIL = 0.3 x VCC ±1 uA tSet Modulus Control Set-up time. (Note 3) SW1 = H, SW2 = H fin = 2.7 GHz 15 20 ns IM Input/Output Intermodulation (Note 4) −10 dBm / 50Ω AC coupled signal delivered to input. VCC = 2.7V to 5.5V. MC = 0, MC = 1. Fin = 2.3 GHz to 2.5 GHz. −35 −30 dBc 0.7 x VCC V 0.3 x VCC V Note 3: See Timing Diagram. Note 4: Guaranteed by design and characterization, not tested. Output frequency measured at input. 3 www.national.com Functional Description the low frequency synthesizer, or a controller to set the prescaler divide ratio to N or N+2. The prescaler output frequency is established by dividing the VCO signal down via the prescaler modulus. The RF inputs to the prescalar consist of the Fin and /Fin input pins which are complementary inputs to a differential pair amplifier. This configuration can operate to 2 GHz with an input sensitivity of −15 dBm. The basic phase-lock-loop (PLL) configuration using an external prescaler consists of a high-stability crystal reference oscillator, a prescaler such as the National Semiconductor LMX5080, a low frequency synthesizer, a voltage controlled oscillator (VCO), and a loop filter. The frequency synthesizer typically includes programmable reference [R] and feedback [N] frequency dividers, a phase detector, as well as a charge pump. The MC signal is fed back to the prescaler from either Block Diagram DS100940-3 www.national.com 4 Modulus Control Truth Table SW1 SW2 MC Divide Ratio H H H 1/128 H H L 1/130 H L H 1/256 L H H 1/256 H L L 1/258 L H L 1/258 L L H 1/512 L L L 1/514 Note: SW1, SW2, MC: H = 0.7 x VCC, L = 0.3 x VCC. Timing Diagram DS100940-4 5 www.national.com Typical Performance Characteristics ICC vs VCC N = 1/128, TA = 25˚C RF Input Sensitivity vs Frequency DS100940-6 DS100940-7 Input Impedance (S11) vs Frequency VCC = 2.7V to 5.5V, fin = 100 MHz to 2.7 GHz DS100940-8 Marker Marker Marker Marker 1 2 3 4 = = = = 100 MHz, Real = 364, Imag = −253 1 GHz, Real = 104, Imag = −136 2 GHz, Real = 26, Imag = −53 2.7 GHz, Real = 36, Imag = −23 www.national.com 6 inches (millimeters) unless otherwise noted 8 Lead (0.150” Wide) Molded Small Outline Package, JEDEC Order Number LMX5080M For Tape and Reel Order Number LMX5080MX NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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