NSC ADC14L040CIVY

ADC14L040
14-Bit, 40 MSPS, 235 mW A/D Converter
General Description
Features
The ADC14L040 is a low power monolithic CMOS analogto-digital converter capable of converting analog input signals into 14-bit digital words at 40 Megasamples per second
(MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-andhold circuit to minimize power consumption while providing
excellent dynamic performance and a 150 MHz Full Power
Bandwidth. Operating on a single +3.3V power supply, the
ADC14L040 achieves 11.9 effective bits at nyquist and consumes just 235 mW at 40 MSPS . The Power Down feature
reduces power consumption to 15 mW.
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The differential inputs provide a full scale differential input
swing equal to 2 times VREF with the possibility of a singleended input. Full use of the differential input is recommended for optimum performance. Duty cycle stabilization
and output data format are selectable using a quad state
function pin. The output data can be set for offset binary or
two’s complement.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC14L040 can be connected to a separate supply voltage in the range of 2.4V to
the analog supply voltage.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evaluation process.
Single +3.3V supply operation
Internal sample-and-hold
Internal reference
Outputs 2.4V to 3.6V compatible
Duty Cycle Stabilizer
Power down mode
Key Specifications
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Resolution
DNL
SNR (fIN = 10 MHz)
SFDR (fIN = 10 MHz)
Data Latency
Power Consumption
-- Operating
-- Power Down Mode
14 Bits
± 0.5 LSB (typ)
74 dB (typ)
90 dB (typ)
7 Clock Cycles
235 mW (typ)
15 mW (typ)
Applications
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Medical Imaging
Instrumentation
Communications
Digital Video
Connection Diagram
20146501
© 2006 National Semiconductor Corporation
DS201465
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ADC14L040 14-Bit, 40 MSPS, 235 mW A/D Converter
March 2006
ADC14L040
Ordering Information
Industrial (−40˚C ≤ TA ≤ +85˚C)
Package
ADC14L040CIVY
32 Pin LQFP
ADC14L040EVAL
Evaluation Board
Block Diagram
20146502
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2
ADC14L040
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
2
VIN+
3
VIN−
1
VREF
31
VRP
32
VRM
30
VRN
11
Differential analog input pins. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 VP-P with each
input pin voltage centered on a common mode voltage, VCM.
The negative input pins may be connected to VCM for
single-ended operation, but a differential input signal is
required for best performance.
This pin is the reference select pin and the external reference
input.
If (VA - 0.3V) < VREF < VA, the internal 1.0V reference is
selected.
If AGND < VREF < (AGND + 0.3V), the internal 0.5V reference
is selected.
If a voltage in the range of 0.4V to (VA - 0.4V) is applied to this
pin, that voltage is used as the reference.
The full scale differential voltage range is 2 * VREF. VREF
should be bypassed to AGND with a 0.1 µF capacitor when an
external reference is used.
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor. A 10 µF
capacitor should be placed between the VRP and VRN.
VRM may be loaded to 1mA for use as a temperature stable
1.5V reference. The remaining pins should not be loaded.
VRM may be used to provide the common mode voltage, VCM,
for the differential inputs.
This is a four-state pin.
DF/DCS = VA, output data format is offset binary with duty
cycle stabilization applied to the input clock
DF/DCS = AGND, output data format is 2’s complement, with
duty cycle stabilization applied to the input clock.
DF/DCS = VRM , output data is 2’s complement without duty
cycle stabilization applied to the input clock
DF/DCS = "float", output data is offset binary without duty cycle
stabilization applied to the input clock.
DF/DCS
DIGITAL I/O
10
8
Digital clock input. The range of frequencies for this input is as
specified in the electrical tables with guaranteed performance
at 40 MHz. The input is sampled on the rising edge.
CLK
PD is the Power Down input pin. When high, this input puts the
converter into the power down mode. When this pin is low, the
converter is in the active mode.
PD
3
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ADC14L040
Pin Descriptions and Equivalent Circuits
Pin No.
12-19
22-27
Symbol
Equivalent Circuit
(Continued)
Description
Digital data output pins that make up the 14-bit conversion
result. D0 (pin 12) is the LSB, while D13 (pin 27) is the MSB of
the output word. Output levels are TTL/CMOS compatible.
Optimum loading is < 10pF.
D0–D13
ANALOG POWER
5, 29
VA
4, 7, 28
AGND
Positive analog supply pins. These pins should be connected
to a quiet +3.3V source and bypassed to AGND with 0.1 µF
capacitors located close to these power pins, and with a 10 µF
capacitor.
The ground return for the analog supply.
DIGITAL POWER
6
VD
9
DGND
21
20
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Positive digital supply pin. This pin should be connected to the
same quiet +3.3V source as is VA and be bypassed to DGND
with a 0.1 µF capacitor located close to the power pin and with
a 10 µF capacitor.
The ground return for the digital supply.
Positive driver supply pin for the ADC14L040’s output drivers.
This pin should be connected to a voltage source of +2.4V to
VD and be bypassed to DR GND with a 0.1 µF capacitor. If the
supply for this pin is different from the supply used for VA and
VD, it should also be bypassed with a 10 µF capacitor. VDR
should never exceed the voltage on VD. All 0.1 µF bypass
capacitors should be located close to the supply pin.
VDR
The ground return for the digital supply for the ADC’s output
drivers. These pins should be connected to the system digital
ground, but not be connected in close proximity to the ADC’s
DGND or AGND pins. See Section 5 (Layout and Grounding)
for more details.
DR GND
4
Operating Ratings (Notes 1, 2)
(Notes 1,
2)
Operating Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA, VD)
−40˚C ≤ TA ≤ +85˚C
+3.0V to +3.6V
Output Driver Supply (VDR)
CLK, PD
VA, VD, VDR
4.2V
≤ 100 mV
|VA–VD|
Voltage on Any Input or Output Pin
−0.3V to (VA or VD
+0.3V)
Package Input Current (Note 3)
Package Dissipation at TA = 25˚C
−0.05V to (VD + 0.05V)
Clock Duty Cycle (DCS On)
20% to 80%
Clock Duty Cycle (DCS Off)
40% to 60%
Analog Input Pins
0V to 2.6V
VCM
± 25 mA
± 50 mA
Input Current at Any Pin (Note 3)
+2.4V to VD
0.5V to 2.0V
≤100mV
|AGND–DGND|
See (Note 4)
ESD Susceptibility
Human Body Model (Note 5)
2500V
Machine Model (Note 5)
Storage Temperature
250V
−65˚C to +150˚C
Soldering process must comply with National
Semiconductor’s Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 6)
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz at -0.5dBFS, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle
Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
Limits
(Note 10) (Note 10)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
± 1.5
± 0.5
INL
Integral Non Linearity (Note 11)
DNL
Differential Non Linearity
PGE
Positive Gain Error
0.3
NGE
Negative Gain Error
0.4
TC GE
Gain Error Tempco
VOFF
Offset Error (VIN+ = VIN−)
TC
VOFF
Offset Error Tempco
−40˚C ≤ TA ≤ +85˚C
14
Bits (min)
± 3.8
± 1.0
± 3.3
± 3.3
LSB (max)
2.5
-0.06
−40˚C ≤ TA ≤ +85˚C
LSB (max)
%FS (max)
%FS (max)
ppm/˚C
± 1.0
1.5
%FS (max)
ppm/˚C
Under Range Output Code
0
Over Range Output Code
16383
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCM
Common Mode Input Voltage
VRM
Reference Output Voltage
CIN
VIN Input Capacitance (each pin to
GND)
VREF
External Reference Voltage (Note
13)
1.5
Output load = 1 mA
VIN = 1.5 Vdc
± 0.5 V
V (max)
1.5
V
11
pF
(CLK HIGH)
4.5
1
5
V (min)
2.0
(CLK LOW)
1.00
Reference Input Resistance
0.5
pF
0.8
V (min)
1.2
V (max)
MΩ (min)
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ADC14L040
Absolute Maximum Ratings
ADC14L040
Converter Electrical Characteristics
(Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz at -0.5dBFS, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle
Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Typical
Limits
(Note 10) (Note 10)
Conditions
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
SNR
SINAD
Full Power Bandwidth
Signal-to-Noise Ratio
Signal-to-Noise Ratio and
Distortion
ENOB
Effective Number of Bits
THD
Total Harmonic Disortion
H2
Second Harmonic Distortion
H3
Third Harmonic Distortion
SFDR
Spurious Free Dynamic Range
IMD
0 dBFS Input, Output at −3 dB
74
fIN = 20 MHz
73.3
fIN = 10 MHz
73.5
fIN = 20 MHz
73
fIN = 10 MHz
12
fIN = 20 MHz
11.9
fIN = 10 MHz
-86
fIN = 20 MHz
-86
fIN = 10 MHz
-93
fIN = 20 MHz
-91
fIN = 10 MHz
-90
fIN = 20 MHz
-94
fIN = 10 MHz
90
fIN = 20 MHz
90
fIN = 9.6 MHz and 10.2 MHz,
each = −6.5 dBFS
Intermodulation Distortion
150
fIN = 10 MHz
MHz
dBc
71.7
dBc
dBc
71.5
dBc
Bits
11.6
Bits
-77
dBc
dBc
dBc
-80
dBc
-80
dBc
dBc
dBc
80
dBc
−79
dBFS
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
CLK, PD DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
1.0
V (max)
IIN(1)
Logical “1” Input Current
VIN = 3.3V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
D0–D13 DIGITAL OUTPUT CHARACTERISTICS
VDR = 2.5V
2.3
VDR = 3V
2.7
V (min)
V (min)
0.4
V (max)
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 3V
+ISC
Output Short Circuit Source
Current
VOUT = 0V
−10
mA
−ISC
Output Short Circuit Sink Current
VOUT = VDR
10
mA
COUT
Digital Output Capacitance
5
pF
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
PD Pin = DGND, VREF = VA
PD Pin = VD
ID
Digital Supply Current
IDR
63
4.5
86
mA (max)
mA
PD Pin = DGND
PD Pin = VD , fCLK = 0
8
0
12
mA (max)
mA
Digital Output Supply Current
PD Pin = DGND, CL = 5 pF (Note 14)
PD Pin = VD, fCLK = 0
4
0
Total Power Consumption
PD Pin = DGND, CL = 5 pF (Note 15)
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mA
mA
323
mW (max)
(Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
PSRR
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
Power Down Power Consumption
PD Pin = VD, clock on
15
mW
Power Supply Rejection Ratio
Rejection of Full-Scale Error with
VA =3.0V vs. 3.6V
72
dB
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
40
MHz (min)
5
ns (min)
fCLK1
Maximum Clock Frequency
fCLK2
Minimum Clock Frequency
tCH
Clock High Time
tCL
Clock Low Time
Duty Cycle Stabilizer On
12.5
5
ns (min)
tCH
Clock High Time
Duty Cycle Stabilizer Off
12.5
10
ns (min)
tCL
Clock Low Time
Duty Cycle Stabilizer Off
12.5
10
ns (min)
tCONV
Conversion Latency
7
Clock
Cycles
tOD
Data Output Delay after Rising
Clock Edge
9.6
ns (max)
tAD
Aperture Delay
2
ns
tAJ
Aperture Jitter
0.7
ps rms
tPD
Power Down Mode Exit Cycle
280
µs
5
Duty Cycle Stabilizer On
12.5
6
0.1 µF on pins 30, 31, 32; 10 µF
between pins 30, 31
MHz
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. The values
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per
(Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale
input voltage must be ≤+3.4V to ensure accurate conversions.
20146511
Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for VREF = +1.0V (2VP-P differential input), the 14-bit LSB is 122.1 µV.
Note 10: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
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ADC14L040
DC and Logic Electrical Characteristics
ADC14L040
AC Electrical Characteristics
(Continued)
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.
Note 13: Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23 package) is
recommended for external reference applications.
Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply
voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.
Note 15: Excludes IDR. See note 14.
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APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conversion.
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of 1⁄2 LSB
above negative full scale.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
OFFSET ERROR is the difference between the two input
voltages [(VIN+) – (VIN-)] required to cause a transition from
code 8191 to 8192.
CLOCK DUTY CYCLE is the ratio of the time during one
cycle that a repetitive digital waveform is high to the total
time of one period. The specification here refers to the ADC
clock input signal.
COMMON MODE VOLTAGE (VCM) is the common d.c. voltage applied to both input terminals of the ADC.
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 11⁄2 LSB
below positive full scale.
CONVERSION LATENCY is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. PSRR is the ratio of the change in Full-Scale
Error that results from a change in the d.c. power supply
voltage, expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full
Scale Error
It can also be expressed as Positive Gain Error and Negative
Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error
NGE = Offset Error - Negative Full Scale Error
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (1⁄2 LSB below the first code transition)
through positive full scale (1⁄2 LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value or weight of all bits. This value is VFS/2n,
where “VFS” is the full scale input voltage and “n” is the ADC
resolution in bits.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC14L040 is guaranteed
not to have any missing codes.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where f1 is the RMS power of the fundamental (output)
frequency and f2 through f10 are the RMS power of the first
9 harmonic frequencies in the output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM) is the
difference expressed in dB, between the RMS power in the
input frequency at the output and the power in its 2nd
harmonic level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the
input frequency at the output and the power in its 3rd harmonic level at the output.
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ADC14L040
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
Specification Definitions
ADC14L040
Timing Diagram
20146509
Output Timing
Transfer Characteristic
20146510
FIGURE 1. Transfer Characteristic
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DNL
INL
20146561
20146562
DNL vs. fCLK
INL vs. fCLK
20146563
20146564
DNL vs. Clock Duty Cycle
INL vs. Clock Duty Cycle
20146565
20146566
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ADC14L040
Typical Performance Characteristics, DNL, INL Unless otherwise specified, the following
specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V,
fCLK = 40 MHz, fIN = 0 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to
TMAX: all other limits TJ = 25˚C
ADC14L040
Typical Performance Characteristics, DNL, INL Unless otherwise specified, the following
specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V,
fCLK = 40 MHz, fIN = 0 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to
TMAX: all other limits TJ = 25˚C (Continued)
DNL vs. Temperature
INL vs. Temperature
20146567
20146568
DNL vs. VDR, VA = VD = 3.6V
INL vs. VDR, VA = VD = 3.6V
20146569
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20146570
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Distortion vs. VA
SNR,SINAD,SFDR vs. VA
20146571
20146572
SNR,SINAD,SFDR vs. VDR, VA = VD = 3.6V
Distortion vs. VDR, VA = VD = 3.6V
20146573
20146574
SNR,SINAD,SFDR vs. VCM
Distortion vs. VCM
20146575
20146576
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ADC14L040
Typical Performance Characteristics Unless otherwise specified, the following specifications apply
for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN =
20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits
TJ = 25˚C
ADC14L040
Typical Performance Characteristics Unless otherwise specified, the following specifications apply
for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN =
20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits
TJ = 25˚C (Continued)
SNR,SINAD,SFDR vs. fCLK
Distortion vs. fCLK
20146577
20146578
SNR,SINAD,SFDR vs. Clock Duty Cycle
Distortion vs. Clock Duty Cycle
20146579
20146580
SNR,SINAD,SFDR vs. VREF
Distortion vs. VREF
20146581
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20146582
14
SNR,SINAD,SFDR vs. fIN
Distortion vs. fIN
20146583
20146584
SNR,SINAD,SFDR vs. Temperature
Distortion vs. Temperature
20146585
20146586
Spectral Response @ 4.4 MHz Input
tOD vs. VDR, VA = VD = 3.6V
20146587
20146591
15
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ADC14L040
Typical Performance Characteristics Unless otherwise specified, the following specifications apply
for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN =
20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits
TJ = 25˚C (Continued)
ADC14L040
Typical Performance Characteristics Unless otherwise specified, the following specifications apply
for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN =
20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits
TJ = 25˚C (Continued)
Spectral Response @ 10 MHz Input
Spectral Response @ 20 MHz Input
20146588
20146589
Intermodulation Distortion, fIN1= 9.6 MHz, fIN2 = 10.2
MHz
20146590
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16
Operating on a single +3.3V supply, the ADC14L040 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance. The differential analog input
signal is digitized to 14 bits. The user has the choice of using
an internal 1.0 Volt or 0.5 Volt stable reference, or using an
external reference. Any external reference is buffered onchip to ease the task of driving that pin.
The nominal voltages for the reference bypass pins are as
follows:
VRM = 1.5 V
VRP = VRM + VREF / 2
VRN = VRM − VREF / 2
The output word rate is the same as the clock frequency. For
the ADC14L040 the clock frequency can be between 5
MSPS and 40 MSPS (typical) with fully specified performance at 40 MSPS. The analog input is acquired at the
rising edge of the clock and the digital data for a given
sample is delayed by the pipeline for 7 clock cycles. Duty
cycle stablization and output data format are selectable using the quad state function DF/DCS pin. The output data can
be set for offset binary or two’s complement.
A logic high on the power down (PD) pin reduces the converter power consumption to 15 mW.
User choice of an on-chip or external reference voltage is
provided. The internal 1.0 Volt reference is in use when the
the VREF pin is connected to VA. When the VREF pin is
connected to AGND, the internal 0.5 Volt reference is in use.
If a voltage in the range of 0.8V to 1.2V is applied to the VREF
pin, that is used for the voltage reference. When an external
reference is used, the VREF pin should be bypassed to
ground with a 0.1 µF capacitor close to the reference input
pin. There is no need to bypass the VREF pin when the
internal reference is used.
1.3 Signal Inputs
The signal inputs are VIN + and VIN− . The input signal, VIN,
is defined as
VIN = (VIN+) – (VIN−)
Figure 2 shows the expected input signal range. Note that
the common mode input voltage, VCM, should be in the
range of 0.5V to 2.0V.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC14L040:
3.0V ≤ VA ≤ 3.6V
VD = V A
2.4V ≤ VDR ≤ VA
5 MHz ≤ fCLK ≤ 40 MHz
0.8V ≤ VREF ≤ 1.2V (for an external reference)
The peaks of the individual input signals should each never
exceed 2.6V.
The ADC14L040 performs best with a differential input signal
with each input centered around a common mode voltage,
VCM. The peak-to-peak voltage swing at each analog input
pin should not exceed the value of the reference voltage or
the output data will be clipped.
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the
effective full scale input. For complex waveforms, however,
angular errors will result in distortion.
0.5V ≤ VCM ≤ 2.0V
1.1 Analog Inputs
There is one reference input pin, VREF, which is used to
select an internal reference, or to supply an external reference. The ADC14L040 has one analog signal input pairs,
VIN + and VIN - . This pair of pins forms a differential input
pair.
1.2 Reference Pins
The ADC14L040 is designed to operate with an internal 1.0V
or 0.5V reference, or an external 1.0V reference, but performs well with external reference voltages in the range of
0.8V to 1.2V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC14L040. Increasing
the reference voltage (and the input signal swing) beyond
1.2V may degrade THD for a full-scale input, especially at
higher input frequencies.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects
of noise currents in the ground path.
The Reference Bypass Pins (VRP, VRM, and VRN) are made
available for bypass purposes. All these pins should each be
bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should be placed between the VRP and VRN pins, as
shown in Figure 4. This configuration is necessary to avoid
reference oscillation, which could result in reduced SFDR
and/or SNR. VRM may be loaded to 1mA for use as a
temperature stable 1.5V reference. The remaining pins
should not be loaded.
20146515
FIGURE 2. Expected Input Signal Range
For single frequency sine waves the full scale error in LSB
can be described as approximately
EFS = 16384 ( 1 - sin (90˚ + dev))
Where dev is the angular difference in degrees between the
two signals having a 180˚ relative phase relationship to each
other (see Figure 3). Drive the analog inputs with a source
impedance less than 100Ω.
17
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ADC14L040
Smaller capacitor values than those specified will allow
faster recovery from the power down mode, but may result in
degraded noise performance. Loading any of these pins
other than VRM may result in performance degradation.
Functional Description
ADC14L040
Applications Information
(Continued)
20146516
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level or Cause
Distortion
VIN+
VIN−
Binary Output
2’s Complement
Output
VCM −
VREF/2
VCM
01 0000 0000
0000
11 0000 0000
0000
VCM
VCM
10 0000 0000
0000
00 0000 0000
0000
VCM +
VREF/2
VCM
11 0000 0000
0000
01 0000 0000
0000
VCM +
VREF
VCM
11 1111 1111
1111
01 1111 1111
1111
VIN+
VIN−
Binary Output
2’s Complement
Output
VCM −
VREF/2
VCM +
VREF/2
00 0000 0000
0000
10 0000 0000
0000
1.3.2 Driving the Analog Inputs
The VIN+ and the VIN− inputs of the ADC14L040 consist of
an analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 11 pF when the clock is low,
and 4.5 pF when the clock is high.
As the internal sampling switch opens and closes, current
pulses occur at the analog input pins, resulting in voltage
spikes at the signal input pins. As a driving amplifier attempts
to counteract these voltage spikes, a damped oscillation
may appear at the ADC analog input. Do not attempt to filter
out these pulses. Rather, use amplifiers to drive the
ADC14L040 input pins that are able to react to these pulses
and settle before the switch opens and another sample is
taken. The LMH6702 LMH6628, LMH6622 and the
LMH6655 are good amplifiers for driving the ADC14L040.
To help isolate the pulses at the ADC input from the amplifier
output, use RCs at the inputs, as can be seen in Figure 4 .
These components should be placed close to the ADC inputs because the input pins of the ADC is the most sensitive
part of the system and this is the last opportunity to filter that
input.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered when setting the RC pole. For wideband undersampling applications, the RC pole should be set
at about 1.5 to 2 times the maximum input frequency to
maintain a linear delay response.
A single-ended to differential conversion circuit is shown in
Figure 5. Table 3 gives resistor values for that circuit to
provide input signals in a range of 1.0V ± 0.5V at each of the
differential input pins of the ADC14L040.
VCM −
VREF/4
VCM +
VREF/4
01 0000 0000
0000
11 0000 0000
0000
TABLE 3. Resistor Values for Circuit of Figure 5
VCM
VCM
10 0000 0000
0000
00 0000 0000
0000
SIGNAL
RANGE
R1
VCM +
VREF/4
VCM −
VREF/4
11 0000 0000
0000
01 0000 0000
0000
0 - 0.25V
open
0Ω
124Ω
1500Ω 1000Ω
0 - 0.5V
0Ω
openΩ
499Ω
1500Ω
499Ω
VCM +
VREF/2
VCM −
VREF/2
11 1111 1111
1111
01 1111 1111
1111
± 0.25V
100Ω
698Ω
100Ω
698Ω
499Ω
For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal to the
reference voltage, VREF, be 180 degrees out of phase with
each other and be centered around VCM.
1.3.1 Single-Ended Operation
Performance with a differential input signal is better than with
a single-ended signal. For this reason, single-ended operation is not recommended. However, if single ended-operation
is required and the resulting performance degradation is
acceptable, one of the analog inputs should be connected to
the d.c. mid point voltage of the driven input. The peak-topeak differential input signal at the driven input pin should be
twice the reference voltage to maximize SNR and SINAD
performance (Figure 2b). For example, set VREF to 1.0V,
bias VIN− to 1.5V and drive VIN+ with a signal range of 0.5V
to 2.5V.
Because very large input signal swings can degrade distortion performance, better performance with a single-ended
input can be obtained by reducing the reference voltage
when maintaining a full-range output. Table 1 and Table 2
indicate the input to output relationship of the ADC14L040.
TABLE 1. Input to Output Relationship – Differential
Input
VIN−
Binary Output
2’s Complement
Output
VCM −
VREF
VCM
00 0000 0000
0000
10 0000 0000
0000
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R3
R4
R5, R6
1.3.3 Input Common Mode Voltage
The input common mode voltage, VCM, should be in the
range of 0.5V to 2.0V and be a value such that the peak
excursions of the analog signal does not go more negative
than ground or more positive than 2.6V. See Section 1.2
TABLE 2. Input to Output Relationship – Single-Ended
Input
VIN+
R2
2.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, PD,
and DF/DCS.
18
the power down mode, but can result in a reduction in SNR,
SINAD and ENOB performance.
(Continued)
2.1 CLK
2.3 DF/DCS
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range indicated in the Electrical Table with rise and fall
times of 2 ns or less. The trace carrying the clock signal
should be as short as possible and should not cross any
other signal line, analog or digital, not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency too low, the charge on
internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the
minimum sample rate.
Duty cycle stablization and output data format are selectable
using this quad state function pin. When enabled, duty cycle
stabilization can compensate for clock inputs with duty
cycles ranging from 20% to 80% and generate a stable
internal clock, improving the performance of the part.
With DF/DCS = VA the output data format is offset binary and
duty cycle stabilization is applied to the clock. With DF/DCS
= 0 the output data format is 2’s complement and duty cycle
stabilization is applied to the clock. With DF/DCS = VRM the
output data format is 2’s complement and duty cycle stabilization is not used. If DF/DCS is floating, the output data
format is offset binary and duty cycle stabilization is not
used. While the sense of this pin may be changed "on the
fly," doing this is not recommended as the output data could
be erroneous for a few clock cycles after this change is
made.
The clock line should be terminated at its source in the
characteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on
setting characteristic impedance.
It is highly desirable that the the source driving the ADC CLK
pin only drive that pin. However, if that source is used to
drive other things, each driven pin should be a.c. terminated
with a series RC to ground, as shown in Figure 4, such that
the resistor value is equal to the characteristic impedance of
the clock line and the capacitor value is
3.0 OUTPUTS
The ADC14L040 has 14 TTL/CMOS compatible Data Output
pins. Valid data is present at these outputs while the PD pins
is low. Data should be captured with the CLK signal. Depending on the setup and hold time requirements of the
receiving circuit (ASIC), either the rising edge or the falling
edge of the CLK signal can be used to latch the data.
Generally, rising-edge capture would maximize setup time
with minimal hold time; while falling-edge-capture would
maximize hold time with minimal setup time. However, actual
timing for the falling-edge case depends greatly on the CLK
frequency and both cases also depend on the delays inside
the ASIC. Refer to the tOD spec in the AC Electrical Characterisitics table.
where tPD is the signal propagation rate down the clock line,
"L" is the line length and ZO is the characteristic impedance
of the clock line. This termination should be as close as
possible to the ADC clock pin but beyond it as seen from the
clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on
FR-4 board material. The units of "L" and tPD should be the
same (inches or centimeters).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through VDR and DR GND. These large charging current
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally,
bus capacitance beyond the specified 15 pF/pin will cause
tOD to increase, making it difficult to properly latch the ADC
output data. The result could be an apparent reduction in
dynamic performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connecting buffers (74ACQ541, for example) between the ADC outputs and any other circuitry. Only one driven input should be
connected to each output pin. Additionally, inserting series
resistors of about 33Ω at the digital outputs, close to the ADC
pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4.
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC14L040 has a Duty Cycle Stabilizer
which can be enabled using the DF/DCS pin. It is designed
to maintain performance over a clock duty cycle range of
20% to 80%.
2.2 PD
The PD pin, when high, holds the ADC14L040 in a powerdown mode to conserve power when the converter is not
being used. The power consumption in this state is 15 mW.
The output data pins are undefined and the data in the
pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on pins 30, 31 and 32 and is about
280 µs with the recommended components on the VRP, VRM
and VRN reference bypass pins. These capacitors loose their
charge in the Power Down mode and must be recharged by
on-chip circuitry before conversions can be accurate.
Smaller capacitor values allow slightly faster recovery from
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ADC14L040
Applications Information
ADC14L040
Applications Information
(Continued)
20146513
FIGURE 4. Application Circuit using Transformer Drive Circuit
20146514
FIGURE 5. Differential Drive Circuit of Figure 4
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off.
The VDR pin provides power for the output drivers and may
be operated from a supply in the range of 2.4V to VD. This
can simplify interfacing to lower voltage devices and systems. Note, however, that tOD increases with reduced VDR.
DO NOT operate the VDR pin at a voltage higher than VD.
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
capacitor and with a 0.1 µF ceramic chip capacitor close to
each power pin. Leadless chip capacitors are preferred because they have low series inductance.
As is the case with all high-speed converters, the
ADC14L040 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100
mVP-P.
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20
All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of the
board. All digital circuitry and I/O lines should be placed in
the digital area of the board. The ADC14L040 should be
between these two areas. Furthermore, all components in
the reference circuitry and the input signal chain that are
connected to ground should be connected together with
short traces and enter the ground plane at a single, quiet
point. All ground connections should have a low inductance
path to ground.
(Continued)
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC14L040
between these areas, is required to achieve specified performance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity to any of the ADC14L040’s other ground pins.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 6. The gates used in the clock tree must
be capable of operating at frequencies much higher than
those used if added jitter is to be prevented.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
Best performance will be obtained with a differential input
drive, compared with a single-ended drive, as discussed in
Sections 1.3.1 and 1.3.2.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T)
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 33Ω resistors
in series with each data output line. Locate these resistors as
close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane area.
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90˚ crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because
other lines can introduce jitter into the clock line, which can
lead to degradation of SNR. Also, the high speed clock can
introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very
clean point in the ground plane.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
20146517
FIGURE 6. Isolating the ADC Clock from other Circuitry
with a Clock Tree
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 47Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC14L040 with
a device that is powered from supplies outside the range of
the ADC14L040 supply. Such practice may lead to conversion inaccuracies and even to device damage.
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ADC14L040
Applications Information
ADC14L040
Applications Information
improve performance. The LMH6702 and the LMH6628
have been successfully used to drive the analog inputs of the
ADC14L040.
(Continued)
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through VDR and DR GND. These large charging current spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 15 pF/pin
will cause tOD to increase, making it difficult to properly latch
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180o out of phase
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, when using an
external reference, VREF should be in the range of
0.8V ≤ VREF ≤ 1.2V
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC14L040, which reduces the energy coupled back into
the converter output pins by limiting the output current. A
reasonable value for these resistors is 33Ω.
Operating outside of these limits could lead to performance
degradation.
Inadequate network on Reference Bypass pins (VRP,
VRN, and VRM). As mentioned in Section 1.2, these pins
should be bypassed with 0.1 µF capacitors to ground, and 10
µF capacitor should be connected between pins VRP and
VRN.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 11 pF and 4.5 pF, depending upon
the phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a
capacitor at the analog inputs (as shown in Figure 5) will
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22
ADC14L040 14-Bit, 40 MSPS, 235 mW A/D Converter
Physical Dimensions
inches (millimeters) unless otherwise noted
32-Lead LQFP Package
Ordering Number ADC14L040CIVY
NS Package Number VBE32A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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Japan Customer Support Center
Fax: 81-3-5639-7507
Email: [email protected]
Tel: 81-3-5639-7560