HI-1565, HI-1566 MIL-STD-1553 / 1760 5V Monolithic Dual Transceivers August 2013 DESCRIPTION PIN CONFIGURATIONS The receiver section of each bus converts the 1553 bus biphase differential data to complementary CMOS / TTL data suitable for input to a Manchester decoder. Each receiver has a separate enable input which can be used to force the output of the receiver to a logic 0 (HI-1565) or logic 1 (HI1566). To minimize the package size for this function, the transmitter outputs are internally connected to the receiver inputs, so that only two pins are required for connection to each coupling transformer. FEATURES ! Compliant to MIL-STD-1553A & B, MIL-STD-1760, ARINC 708A ! CMOS technology for low standby power ! Smallest footprint available in 44-pin plastic N/C 1 RXENA 2 GNDA 3 GNDA 4 GNDA 5 VDDB 6 VDDB 7 BUSB 8 BUSB 9 BUSB 10 BUSB 11 1565PCI 1565PCT 1566PCI 1566PCT 33 N/C 32 N/C 31 TXINHA 30 RXA 29 RXA 28 N/C 27 N/C 26 TXB 25 TXB 24 TXINHB 23 N/C N/C 12 N/C 13 N/C 14 N/C 15 RXENB 16 GNDB 17 GNDB 18 GNDB 19 RXB 20 RXB 21 N/C 22 The transmitter section of each bus takes complementary CMOS / TTL Manchester II bi-phase data and converts it to differential voltages suitable for driving the bus isolation transformer. Separate transmitter inhibit control signals are provided for each transmitter. 44 N/C 43 BUSA 42 BUSA 41 BUSA 40 BUSA 39 VDDA 38 VDDA 37 TXA 36 TXA 35 N/C 34 N/C The HI-1565 and HI-1566 are low power CMOS dual transceivers designed to meet the requirements of MILSTD-1553 and MIL-STD-1760 specifications. 44 Pin Plastic 7mm x 7mm Chip-scale package VDDA 1 BUSA 2 BUSA 3 RXENA 4 GNDA 5 VDDB 6 BUSB 7 BUSB 8 RXENB 9 GNDB 10 1565PSI 1565PST 1565PSM 1566PSI 1566PST 1566PSM 20 19 18 17 16 15 14 13 12 11 TXA TXA TXINHA RXA RXA TXB TXB TXINHB RXB RXB 20 Pin Plastic ESOIC - WB package chip-scale package with integral heatsink VDDA 1 20 TXA ! Less than 1.0W maximum power dissipation ! BUS pins ESD protected to greater than 8KV ! Also available in DIP and small outline BUSA 2 19 TXA (ESOIC) package options ! Industrial and extended temperature ranges ! Industry standard pin configurations BUSA 3 RXENA 4 1565CDI 1565CDT 1565CDM BUSB 7 BUSB 8 17 RXA 16 RXA GNDA 5 VDDB 6 18 TXINHA 1566CDI 1566CDT 1566CDM 15 TXB 14 TXB 13 TXINHB RXENB 9 12 RXB GNDB 10 11 RXB 20 Pin Ceramic DIP package (DS1565 Rev. G) HOLT INTEGRATED CIRCUITS www.holtic.com 08/13 HI-1565, HI-1566 PIN DESCRIPTIONS PIN (DIP/ESOIC) SYMBOL FUNCTION DESCRIPTION 1 VDDA power supply +5 volt power for bus A 2 BUSA analog output MIL-STD-1533 bus driver A, positive signal 3 BUSA analog output MIL-STD-1553 bus driver A, negative signal 4 RXENA digital input 5 GNDA power supply Ground for bus A 6 VDDB power supply +5 volt power for bus B Receiver A enable. If low, forces RXA and RXA low (HI-1565) or High (HI-1566) 7 BUSB analog output MIL-STD-1533 bus driver B, positive signal 8 BUSB analog output MIL-STD-1553 bus driver B, negative signal 9 RXENB digital input 10 GNDB power supply Ground for bus B 11 RXB digital output Receiver B output, inverted 12 RXB digital output Receiver B output, non-inverted 13 TXINHB digital input Transmit inhibit, bus B. If high BUSB, BUSB disabled 14 TXB digital input Transmitter B digital data input, non-inverted 15 TXB digital input Transmitter B digital data input, inverted Receiver B enable. If low, forces RXB and RXB low (HI-1565) or High (HI-1566) 16 RXA digital output Receiver A output, inverted 17 RXA digital output Receiver A output, non-inverted 18 TXINHA digital input Transmit inhibit, bus A. If high BUSA, BUSA disabled 19 TXA digital input Transmitter A digital data input, non-inverted 20 TXA digital input Transmitter A digital data input, inverted FUNCTIONAL DESCRIPTION The HI-1565 family of data bus transceivers contain differential voltage source drivers and differential receivers. It is intended for applications using a MIL-STD-1553 A/B data bus. The device produces a trapezoidal output waveform during transmission. produces CMOS/TTL data at the RXA/B and RXA/B output pins. When the MIL-STD-1553 bus is idle and RXENA or RXENB are high, RXA/B will be logic “0” on HI-1565 and logic “1” on HI-1566. The receiver outputs are forced to the bus idle state (logic “0” for HI-1565 or logic “1” for HI-1566) when RXENA or RXENB is low. TRANSMITTER Data input to the device’s transmitter section is from the complementary CMOS /TTL inputs TXA/B and TXA/B. The transmitter accepts Manchester II bi-phase data and converts it to differential voltages on BUSA/B and BUSA/B. The transceiver outputs are either direct- or transformer-coupled to the MIL-STD-1553 data bus. Both coupling methods produce a nominal voltage on the bus of 7.5 volts peak to peak. The transmitter is automatically inhibited and placed in the high impedance state when both TXA/B and TXA/B are driven with the same logic state. A logic “1” applied to the TXINHA/B input forces the transmitter to the high impedance state, regardless of the state of TXA/B and TXA/B. MIL-STD-1553 BUS INTERFACE A direct-coupled interface (see Figure 2) uses a 1:2.5 ratio isolation transformer and two 55 ohm isolation resistors between the transformer and the bus. The primary centertap of the isolation transformer must be connected to GND. In a transformer-coupled interface (see Figure 2), the transceiver is connected to a 1:1.79 isolation transformer which in turn is connected to a 1:1.4 coupling transformer. The transformer coupled method also requires two coupling resistors equal to 75% of the bus characteristic impedence (Zo) between the coupling transformer and the bus. RECEIVER The receiver accepts bi-phase differential data from the MILSTD-1553 bus through the same direct- or transformercoupled interface as the transmitter. The receiver’s differential input stage drives a filter and threshold comparator that Figure 3 and Figure 4 show test circuits for measuring electrical characteristics of both direct- and transformercoupled interfaces respectively. (See electrical characteristics on the following pages.) HOLT INTEGRATED CIRCUITS 2 HI-1565, HI-1566 Data Bus Each Bus TRANSMITTER Isolation Transformer Coupler Network BUSA/B TXA/B Transmit Logic Direct or Transformer Slope Control TXA/B BUSA/B TXINHA/B RECEIVER RXA/B Input Filter Receive Logic RXA/B Comparator RXENA/B Figure 1. Block Diagram TRANSMIT WAVEFORM - EXAMPLE PATTERN TXA/B TXA/B BUSA/B - BUSA/B RECEIVE WAVEFORMS - EXAMPLE PATTERN Vin (Line to Line) tDR tDR tDR RXA/B (HI-1565) tRG tRG tRG tRG RXA/B (HI-1565) RXA/B (HI-1566) RXA/B (HI-1566) HOLT INTEGRATED CIRCUITS 3 tDR HI-1565, HI-1566 RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS Supply voltage (VDD) Logic input voltage range Supply Voltage -0.3 V to +7 V VDD....................................... 5V... ±5% -0.3 V dc to +5.5 V Receiver differential voltage 50 Vp-p Temperature Range Driver peak output current +1.0 A Power dissipation at 25°C ceramic DIL, derate 1.0 W 7mW/°C Industrial ....................... -40°C to +85°C Extended ...................... -55°C to +125°C Solder Reflow Temperature 260°C Junction Temperature 175°C Storage Temperature -65°C to +150°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. DC ELECTRICAL CHARACTERISTICS VDD = 5.0V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS 4.75 5 5.25 V Operating Voltage VDD Total Supply Current ICC1 Not Transmitting 14 22 mA ICC2 Transmit one bus @ 50% duty cycle 200 340 mA ICC3 Transmit one bus @ 100% duty cycle 400 550 mA 0.11 W 0.95 W Power Dissipation PD1 Not Transmitting PD2 Transmit one bus @ 100% duty cycle 0.70 Min. Input Voltage (HI) VIH Digital inputs Max. Input Voltage (LO) VIL Digital inputs Min. Input Current (HI) IIH VIH = 4.9V, Digital inputs Max. Input Current (LO) IIL VIL = 0.1V, Digital inputs -20 µA Min. Output Voltage (HI) VOH IOUT = -0.4mA, Digital outputs 2.7 V (LO) VIH IOUT = 4.0mA, Digital outputs Max. Output Voltage RECEIVER 2.0 1.4 1.4 V 0.8 V 20 µA 0.4 V (Measured at Point “AD“ in Figure 2 unless otherwise specified) Input resistance Input capacitance Common mode rejection ratio RIN Differential CIN Differential CMRR Input common mode voltage 20 40 VICM -5.0 Detect VTHD 1 Mhz Sine Wave Measured at Point “AD“ in Figure 3 RXA/B, RXA/B pulse width >70ns 1.15 No Detect VTHND No pulse at RXA/B, RXA/B Threshold Voltage - Transformer-coupled Detect VTHD 1 Mhz Sine Wave Measured at Point “AT“ in Figure 4 RXA/B, RXA/B pulse width >70ns No Detect VTHND No pulse at RXA/B, RXA/B Threshold Voltage - Direct-coupled Kohm 5 HOLT INTEGRATED CIRCUITS 4 pF dB 5.0 V-pk Vp-p 0.28 0.86 Vp-p Vp-p 0.20 Vp-p HI-1565, HI-1566 DC ELECTRICAL CHARACTERISTICS (cont.) VDD = 5.0V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER TRANSMITTER SYMBOL CONDITION MIN TYP MAX UNITS 7.0 9.0 Vp-p 20.0 27.0 Vp-p 10.0 mVp-p -90 90 mV -250 250 mV (Measured at Point “AD” in Figure 3 unless otherwise specified) Output Voltage Direct coupled VOUT Transformer coupled VOUT Output Noise 35 ohm load (Measured at Point “AD“ in Figure 3) 70 ohm load (Measured at Point “AT“ in Figure 4) VON Output Dynamic Offset Voltage Differential, inhibited Direct coupled VDYN Transformer coupled VDYN 35 ohm load (Measured at Point “AD“ in Figure 3) 70 ohm load (Measured at Point “AT“ in Figure 4) Output resistance ROUT Differential, not transmitting Output Capacitance COUT 1 MHz sine wave 10 Kohm 15 pF AC ELECTRICAL CHARACTERISTICS VDD = 5.0V, GND = 0V, TA =Operating Temperature Range (unless otherwise specified). PARAMETER RECEIVER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 450 ns 365 ns 40 ns (Measured at Point “AT” in Figure 4 unless otherwise specified) Receiver Delay tDR From input zero crossing to RXA/B or RXA/B Receiver gap time tRG Spacing between RXA/B 90 and RXA/B pulses. 1 MHz sine wave applied at point “AT” Figure 4, amplitude range 0.86 Vp-p to 27.0Vp-p Receiver Enable Delay tREN From STROBE rising or falling edge to RXA/B or RXA/B TRANSMITTER (Measured at Point “AD” in Figure 3) Driver Delay tDT TXA/B, TXA/B to BUSA/B, BUSA/B 150 ns Rise time tr 35 ohm load 100 300 ns Fall Time tf 35 ohm load 100 300 ns tDI-H Inhibited output 100 ns tDI-L Active output 150 ns Inhibit Delay Isolation Transformer BUS A 55W BUS A 55W MIL-STD-1553 BUS A (Direct Coupled) Transceiver A 1:2.5 MIL-STD-1553 Stub Coupler Isolation Transformer BUS B 52.5W BUS B 52.5W Transceiver B 1:1.79 1:1.4 HI-1565 / HI-1566 Figure 2. Bus Connecton Example using HI-1565 or HI-1566 HOLT INTEGRATED CIRCUITS 5 MIL-STD-1553 BUS B (Transformer Coupled) HI-1565, HI-1566 VDD Each Bus Isolation Transformer TXA/B TXA/B RXA/B MIL-STD-1553 Transceiver BUS A/B 55W BUS A/B 55W 35W RXA/B 1:2.5 Point “AD” HI-1565 / HI-1566 GND Figure 3. Direct Coupled Test Circuit VDD Each Bus Isolation Transformer TXA/B TXA/B RXA/B MIL-STD-1553 Transceiver RXA/B BUS A/B 70W BUS A/B 1:1.79 Point “AT” HI-1565 / HI-1566 GND Figure 4. Transformer Coupled Test Circuit dissipation. The heat sink is electrically isolated and may be soldered to any convenient power or ground plane. HEAT SINK - ESOIC & CHIP-SCALE PACKAGE Both the HI-1565PSI/T/M and HI-1566PSI/T/M use a 20pin thermally enhanced SOIC package. The HI-1565PCI/T and HI-1566PCI/T use a plastic chip-scale package. These packages include a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal APPLICATIONS NOTE Holt Applications Note AN-500 provides circuit design notes regarding the use of Holt's family of MIL-STD-1553 transceivers. Layout considerations, as well as recommended interface and protection components are included. THERMAL CHARACTERISTICS PART NUMBER PACKAGE STYLE HI-1565PSI / T / M 20-pin Thermally enhanced plastic SOIC (ESOIC) HI-1566PSI / T / M HI-1565CDI / T / M HI-1566CDI / T / M HI-1565PCI / T HI-1566PCI / T JUNCTION TEMPERATURE CONDITION ØJA Heat sink unsoldered 54°C/W 62°C 122°C 162°C Heat sink soldered 47°C/W 57°C 117°C 157°C 20-pin Ceramic side-brazed DIP Socketed 62°C/W 69°C 129°C 169°C 44-pin Plastic chipscale package Heat sink unsoldered 49°C/W 59°C 119°C 159°C TA=25°C TA=85°C TA=125°C Data taken at VDD=5.0V, continuous transmission at 1Mbit/s, single transmitter enabled. HOLT INTEGRATED CIRCUITS 6 HI-1565, HI-1566 ORDERING INFORMATION HI - 156x xx x x (Plastic) PART NUMBER Blank F LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I NO T -55°C TO +125°C T NO M -55°C TO +125°C M YES PART NUMBER PACKAGE DESCRIPTION PC 44 PIN PLASTIC CHIP-SCALE LPCC (44PCS) not available with ‘M’ flow PS 20 PIN PLASTIC ESOIC, Thermally Enhanced Wide SOIC w/Heat Sink (20HWE) PART NUMBER RXENA = 0 RXENB = 0 RXA RXA RXB RXB 1565 0 0 0 0 1566 1 1 1 1 HI - 156xCD x (Ceramic) PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I NO Gold (Pb-free, RoHS compliant) T -55°C TO +125°C T NO Gold (Pb-free, RoHS compliant) M -55°C TO +125°C M YES PART NUMBER LEAD FINISH Tin / Lead (Sn / Pb) Solder RXENA = 0 RXENB = 0 PACKAGE RXA RXA RXB RXB DESCRIPTION 1565CD 0 0 0 0 20 PIN CERAMIC SIDE BRAZED DIP (20C) 1566CD 1 1 1 1 20 PIN CERAMIC SIDE BRAZED DIP (20C) RECOMMENDED TRANSFORMERS The HI-1565 and HI-1566 transceivers have been characterized for compliance with the electrical requirements of MIL-STD-1553 when used with the following MANUFACTURER transformers. Holt recommends Premier Magnetics parts as offering the best combination of electrical performance, low cost and small footprint. PART NUMBER APPLICATION TURNS RATIO(S) DIMENSIONS Premier Magnetics PM-DB2798S Isolation Dual tapped 1:1.79, 1:2.5 .4 x 4 x .185 inches Premier Magnetics PM-DB2725EX Isolation Dual tapped 1:1.79, 1:2.5 .4 x .4 x .242 inches Premier Magnetics PM-DB2745S Isolation Dual core 1:1.79, 1:2.5 .63 x .93 x .159 inches Premier Magnetics PM-DB2702 Stub coupling 1:1.4 .625 x .625 x .250 inches HOLT INTEGRATED CIRCUITS 7 HI-1565, HI-1566 REVISION HISTORY Document DS1565 Rev. Date E 09/26/08 F G 07/24/09 08/20/13 Description of Change Clarification of transmitter and receiver functions in Description, clarified available temperature ranges, and corrected a dimension in Recommended Transformers table. Corrected typographical errors in package dimensions. Updated functional description for clarity. Revised figures 2, 3, and 4. Updated package drawings. HOLT INTEGRATED CIRCUITS 8 PACKAGE DIMENSIONS 20-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced) inches (millimeters) Package Type: 20HWE .008 ± .005 (.215 ± .115) .295 ± .015 (7.495 ± .385) .504 BSC (12.80) .407 BSC (10.33) Bottom View .210 ± .015 (5.335 ± .385) .295 BSC (7.50) Top View See Detail A .016 ± .004 (.419 ± .109) Electrically isolated heat sink pad on bottom of package .086 ± .005 (2.181 ± .131) .050 BSC (1.27) 0° to 8° .008 ± .004 (.200 ± .100) .033 ± .017 (.835 ± .435) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Connect to any ground or power plane for optimum thermal dissipation Detail A 20-PIN CERAMIC SIDE-BRAZED DIP inches (millimeters) Package Type: 20C 1.000 ±.010 (25.400 ±.254) .310 ±.010 (7.874 ±.254) .050 TYP. (1.270 TYP.) .125 min (3.175) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .300 ± .010 (7.620 ± .254) .085 ±.009 (2.159 ± .229) .200 max (5.080) .100 BSC (2.54) .017 ±.002 (.432 ±.051) HOLT INTEGRATED CIRCUITS 9 .010 + 0. 02/-.001 (.254 ±.051/-.025) PACKAGE DIMENSIONS 44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) inches (millimeters) Package Type: 44PCS .276 BSC (7.00) .216 ± .002 (5.50 ± .05) .020 BSC (0.50) .276 BSC (7.00) .216 ± .002 (5.50 ± .05) Top View Bottom View .010 (0.25) typ .039 max (1.00) .008 typ (0.2) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Electrically isolated heat sink pad on bottom of package Connect to any ground or power plane for optimum thermal dissipation HOLT INTEGRATED CIRCUITS 10 .016 ± .002 (0.40 ± .05)