HI-8436 32-Channel Ground/Open or Supply/Open Low Threshold Sensor with SPI Interface August 2013 APPLICATION GENERAL DESCRIPTION · Avionics Discrete to Digital Sensing PIN CONFIGURATIONS - VLOGIC - SCK - nCS - SI - SO - MRB - GND - SENSE_31 - SENSE_30 - SENSE_29 - SENSE_28 The HI-8436 is a 32-channel discrete-to-digital sensor fabricated with Silicon-on-Insulator (SOI) technology designed to interface with a Serial Peripheral Interface (SPI). All sense inputs are internally lightning protected to DO160G, Section 22, Cat AZ, BZ and ZZ without external components. The sensing circuit window comparator thresholds are set by programming the center threshold and hysteresis registers to values from 0.4V to 5.2V. The digital values of the sensed inputs can be read either one bank at a time or all 4 banks with one command. 44 43 42 41 40 39 38 37 36 35 34 Four banks of 8 sense inputs can be programmed as either GND/Open or Supply/Open sensors. Supply/Open sensing is also referred to as 28V/Open sensing. VWET0 - 1 SENSE_0 - 2 SENSE_1 - 3 SENSE_2 - 4 SENSE_3 - 5 SENSE_4 - 6 SENSE_5 - 7 SENSE_6 - 8 SENSE_7 - 9 SENSE_8-10 SENSE_9-11 VWET1 NC SENSE_10 SENSE_11 SENSE_12 SENSE_13 SENSE_14 SENSE_15 SENSE_16 SENSE_17 VWET2 44 Pin Plastic Quad Flat Pack (PQFP) 10mm x 10mm 44 - VLOGIC 43 - SCK 42 - nCS 41 - SI 40 - SO 39 - nMR 38 - GND 37 - SENSE_31 36 - SENSE_30 35 - SENSE_29 34 - SENSE_28 Interface to the digital subsystem is simple CMOS logic inputs and outputs. The logic pins are compatible with 3.3V logic allowing direct connection to a wide range of microcontrollers or FPGAs. FEATURES · Robust CMOS Silicon-on-Insulator (SOI) technology · 32-channel Programmable Sense Operation, GND/Open or Supply/Open, 4 X 8 Input Sensors · Programmable HI/LO Threshold and Hysteresis in 0.1V steps, from 0.4V to 5.2V. VWET0 - 1 SENSE_0 - 2 SENSE_1 - 3 SENSE_2 - 4 SENSE_3 - 5 SENSE_4 - 6 SENSE_5 - 7 SENSE_6 - 8 SENSE_7 - 9 SENSE_8 -10 SENSE_9 -11 HI-8436PC 33 - SENSE_27 32 - VWET3 31 - SENSE_26 30 - SENSE_25 29 - SENSE_24 28 - SENSE_23 27 - SENSE_22 26 - SENSE_21 25 - SENSE_20 24 - SENSE_19 23 - SENSE_18 VWET1 - 12 NC - 13 SENSE_10 - 14 SENSE_11 - 15 SENSE_12 - 16 SENSE_13 - 17 SENSE_14 - 18 SENSE_15 - 19 SENSE_16 - 20 SENSE_17 - 21 VWET2 - 22 · Single Low Voltage Supply Operation for low thresholds applications. HI-8436PQI HI-8436PQT - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 Each bank of sensors have a VWETn pin available for optional application of a voltage higher than the logic supply to provide wetting current to Ground side relay contacts. If the Ground offset is small, then the wetting source will automatically be provided from VLOGIC without connecting VWETn. 33 - SENSE_27 32 - VWET3 31 - SENSE_26 30 - SENSE_25 29 - SENSE_24 28 - SENSE_23 27 - SENSE_22 26 - SENSE_21 25 - SENSE_20 24 - SENSE_19 23 - SENSE_18 · Logic Operation from 3.0V to 3.6V · 20 MHz Serial Peripheral Interface (SPI) · Lightning Protected Sense Inputs · Internal Self-Test 44 Pin Plastic QFN 7mm x 7mm HOLT INTEGRATED CIRCUITS www.holtic.com (DS8436 Rev. New.) 08/13 HI-8436 BLOCK DIAGRAM VLOGIC VWET0-3 4 VLOGIC MRB 32 SO_31-0 SI SPI SO TEST 12 CSN DAC VALUE/HYSTERESIS SCK DAC THRESHOLDS PU PD HI LO HI LO 4 VWET0 SO_7-0 PSEN_n VLOGIC 50K PSEN_n VTHI/10 VLOGIC TESTHI 23.8K 3.3K LIGHTNING PROTECTION 29K + - + TESTLO VTHI/10 - 200K PSEN_n 200K SENSE_7-0 SO_31-24 SO_23-16 SO_15-8 VREF PSEN_3-0 8 SENSE_15-8 8 SENSE_23-16 8 SENSE_31-24 GND Figure 2. HOLT INTEGRATED CIRCUITS 2 8 8 8 8 HI-8436 PIN DESCRIPTIONS DESCRIPTION PIN FUNCTION VLOGIC Supply 3.3V Power Supply for both sensors and logic. VWET<0-3> Supply Optional inputs to supply relay wetting current to sense lines in GND/Open operation. Each of the 4 banks of 8 inputs has a VWETn pin. 50KΩ to GND. 4 banks of 8 discrete inputs programmable through the SPI to be either GND/Open or Supply/Open. The type of input is programmed by bank, PSEN<3:0> bits. “0” makes the bank GND/Open sensors, “1” makes the bank SUPPLY/Open sensors The status of the inputs SENSE<31:0> are stored in SO<31:0> See SPI section for programming and reading sensors. SENSE<31:0> Discrete Input GND Supply SCK Digital Input SPI Clock. nCS Digital Input SPI Chip Select, Active Low, internal 30KΩ pull-up. SI Digital Input SPI serial data input, internal 30KΩ pull-down. SO Digital Output nMR Digital Input 0V Ground for Sensor and Logic. SPI serial data output. Master Reset, Active Low, internal 30KΩ pull-up. Table 1. SPI COMMANDS OP Code R/W # Data Bytes 0x02 W 1 Write Control Register 0x04 W 1 Write Program Sense Banks Register, PSEN<3:0>, to program SENSE Inputs 0x3A W 2 Write GND/Open Threshold Center Value and Hysteresis 0x3C W 2 Write Supply/Open Threshold Center Value and Hysteresis 0x1E W 1 Write Test Mode Data Register 0x82 R 1 Read Control Register 0x84 R 1 Read Program Sense Banks Register, to read programmed bank type 0xBA R 2 Read GND/Open Threshold Center Value and Hysteresis 0xBC R 2 Read Supply/Open Threshold Center Value and Hysteresis 0x9E R 1 Read Test Mode Data Register 0x90 R 1 Read Bank 0, SOUT Register, SO<7:0>, status of SENSE<7:0> Inputs 0x92 R 1 Read Bank 1, SOUT Register, SO<15:8>, status of SENSE<15:8> Inputs 0x94 R 1 Read Bank 2, SOUT Register, SO<23:16>, status of SENSE<23:16> Inputs 0x96 R 1 Read Bank 3, SOUT Register, SO<31:24>, status of SENSE<31:24> Inputs 0xF8 R 4 Read All Banks, SOUT Register, SO<31:0>, status of SENSE<31:0> Inputs DESCRIPTION Table 2. HOLT INTEGRATED CIRCUITS 3 HI-8436 SERIAL PERIPHERAL INTERFACE (SPI) SPI BASICS HI-8436 SPI INSTRUCTIONS The HI-8436 uses a SPI (Serial Peripheral Interface) for host access to internal registers which program the chip and store sensor status. Host serial communication is enabled through the active low, Chip Select (nCS) pin, and is accessed via a four-wire interface consisting of Serial Data Input (SI) from the host, Serial Data Output (SO) to the host, the Serial Clock (SCK) and the nCS. All read / write cycles are completely selftimed. The SPI Instructions used to read, write and configure the HI-8436 consist of an opcode and data bytes. Each SPI instruction begins with an 8-bit opcode with the format shown below. The most significant bit (MSB) specifies whether the instruction is a write, “0”, or a read, “1”, transfer. When nCS goes low, the first 8 rising edges of the SCK shift the op code into the decoder register, MSB first. The SPI can be clocked up to 20 MHz. R /W The SPI protocol specifies master and slave operation; the HI-8436 operates as a SPI slave. The SPI protocol defines two parameters, CPOL (clock polarity) and CPHA (clock phase). The possible CPOL-CPHA combinations define four possible “SPI Modes”. Without describing details of the SPI modes, the HI-8436 operates in Mode 0 where input data for each device (master and slave) is clocked on the rising edge of SCK, and output data for each device changes on the falling edge (CPHA = 0, CPOL = 0). The host SPI logic must be set for Mode 0 for proper communications with the HI-8436. As seen in Figure 3, SPI Mode 0 holds SCK in the low state when idle. The SPI protocol transfers serial data in 8-bit bytes. Once nCS is asserted, the rising edge of SCK shifts the input data into the master and slave devices, starting with each byte's most-significant bit. A rising edge on nCS completes the serial transfer and re-initializes the HI-8436 SPI for the next transfer. If nCS goes high before a full byte is clocked by SCK, the incomplete byte clocked into the device SI pin is discarded. In the general case, both master and slave simultaneously send and receive serial data (full duplex), per Figure 3 below. However the HI-8436 operates half duplex, maintaining high impedance on the SO output, except when actually transmitting serial data. When the HI-8436 is sending data on SO during read operations, activity on its SI input is ignored. The host likewise ignores its SI input activity while transmitting to the HI8436. MSB 7 X X X X X X X 6 5 4 3 2 1 0 LSB Figure 4. SPI OPCODE FORMAT For write instructions, the next 8 rising SCK edges shift a data byte into the buffer register. The specific instruction register is loaded on the 8th rising SCK edge. This sequence is repeated until the required number of data bytes for the instruction are written. For read instructions, the most significant bit of the requested data word appears at the SO pin at the next falling SCK edge after the last op code bit is clocked into the decoder. As in write instructions, the number of data bytes varies with the read instruction. SO data changes on the falling SCK edges. Figure 5 to Figure 7 show read and write timing for single-byte, dual-byte and four byte register operations. The instruction op code is immediately followed by data bytes comprising the 8-bit data bytes read or written. For a register read or write, nCS is negated after all data bytes are transferred. Table 2 summarizes the HI-8436 SPI instruction set. SCK (SPI Mode 0) SI SO High Z MSB LSB MSB LSB nCS FIGURE 3. Generalized Single-Byte Transfer Using SPI Protocol Mode 0 HOLT INTEGRATED CIRCUITS 4 High Z HI-8436 Note: SPI Instruction op-codes not shown in Table 2 are “reserved” and must not be used. Further, these op-codes will not provide meaningful data in response to a read instruction. 0 1 2 3 5 4 6 7 Two instruction bytes cannot be “chained”; nCS must be negated after each instruction, and then reasserted for the following Read or Write instruction. 0 1 2 3 5 4 6 7 SCK MSB LSB SI Op-Code Byte MSB LSB High Z SO High Z Data Byte 0 nCS FIGURE 5. Single-Byte Read From a Register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SPI Mode 0 MSB LSB MSB LSB LSB MSB SI Op-Code Byte Data Byte 1 Data Byte 0 High Z SO nCS FIGURE 6. 2-Byte SPI Write Example 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SPI Mode 0 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB SI Op-Code Byte SO Data Byte 3 Data Byte 2 Data Byte 1 High Z nCS FIGURE 7. 4-Byte SPI Read Example HOLT INTEGRATED CIRCUITS 5 Data Byte 0 HI-8436 REGISTER DESCRIPTIONS SR S TE T ST CONTROL REGISTER : CTRL Read: SPI Op-code 0x82 Write: SPI Op-code 0x02 7 6 MSB Reset Value 00 [Opcode, DB0] Bit Name DATA BYTE 0 X X X X X X R/W Default Description 5 4 3 2 1 0 LSB 7-2 - R/W 0 Not Used. 1 SRST R/W 0 Software Reset - Setting this bit to “1” holds all other registers and the TEST bit to their reset values. SRST bit must be written back to “0” to release this reset 0 TEST R/W 0 Setting this bit to “1” puts the HI-8436 in the self test mode. Input to sensors are internally set according to the value of the TEST MODE DATA register TABLE 3. BA Read: SPI Op-code 0x84 Write: SPI Op-code 0x04 X X X X 7 6 MSB Reset Value 00 [Opcode, DB0] Bit Name N BA K3 N BA K2 N BA K1 N K0 PROGRAM SENSE BANKS REGISTER: PSEN<3:0> 5 DATA BYTE 0 4 3 2 R/W Default Description 7-4 - R/W 0 Not Used. 3-0 BANK3-0 R/W 0 Program Sensor type for SENSE Inputs. 1 0 LSB Bank 0 programs inputs SENSE<7:0> Bank 1 programs inputs SENSE<15:8> Bank 2 programs inputs SENSE<23:16> Bank 3 programs inputs SENSE<31:24> Setting a bit to “0” programs the 8 inputs in the bank to be GND/Open sensors. Setting a bit to “1” programs the 8 inputs in the bank to be Supply/Open sensors. TABLE 4. Name 7-4 - 3-0 D AL 0 L1 AL L0 D 3 2 X X X X 7 6 MSB Reset Value 00 [Opcode, DB0] Bit O Read: SPI Op-code 0x9E Write: SPI Op-code 0x1E O D D 1 TEST MODE DATA REGISTER : TMDATA 5 4 DATA BYTE 0 1 0 R/W Default Description R/W 0 Not Used. TMDATA3-0 R/W 0 These 4 bits program the internal inputs to the sense comparators when in the test mode. ODD1 = 1 Odd inputs are set high ODD0 = 1 Odd inputs are set low ALL1 = 1 All inputs are set high ALL0 = 1 All inputs are set low Note: Only one mode can be selected. If more than one bit is high the inputs will all be set low. TABLE 5. HOLT INTEGRATED CIRCUITS 6 HI-8436 REGISTER DESCRIPTIONS (cont.) G O H G YS O 5 H G YS O 4 H G YS O 3 H G YS O 2 H G YS O 1 H YS 0 GND/OPEN THRESHOLD CENTER VALUE AND HYSTERESIS REGISTER: GOCENHYS Read: SPI Op-code 0xBA Write: SPI Op-code 0x3A X X DATA BYTE 1 7 6 MSB 4 3 2 1 0 LSB G O C G VA O L C 5 G VA O L C 4 G VA O L C 3 G VA O L2 C G VA O L C 1 VA L0 Reset Value 00 5 [opcode, DB1 , DB0] X X Bit Name 7 6 MSB DATA BYTE 0 5 4 3 2 1 0 LSB R/W Default Description R/W 0 Not Used. GOHYS5-0 R/W 0 GND/Open Hysteresis. For all inputs programmed to be GND/Open sensors the hysteresis is set by these 6 bits. Hysteresis = 0.2V x GOHYS. R/W 0 Not Used. 5- 0 GOCVAL5-0 R/W 0 GND/Open Threshold Center Value. For all inputs programmed to be GND/Open sensors the center threshold is set by these 6 bits. Center Threshold = 0.1V x GOCVAL. DATA WORD 1 7-6 5-0 - DATA WORD 0 7-6 - VTHI = Threshold center value + ½ Hysteresis, Max limit = 5.2V, Min limit = 0.6V VTLO = Threshold center value - ½ Hysteresis, Max limit = 5.0V, Min limit = 0.4V Example: GND/Open sensors with VTHI = 3.0V and VTLO = 1.0V: a) Program GOHYS Hysteresis = VTHI - VTLO = 0.2V x GOHYS GOHYS = (3V - 1V)/(0.2V) = 10 LSB b) Program GOCVAL Center Value = (VTHI + VTLO) / 2 = 0.1V x GOCVAL GOCVAL = (3V + 1V) / (2 x 0.1) = 20 LSB c) Write 0x3A 0x0A 0x14 to SPI 0x3A writes to the GND/Open Threshold and Hysteresis Register. 0x0A = 10 LSB x 0.2V/LSB = 2V Hysteresis 0x14 = 20 LSB x 0.1V/LSB = 2V Center Threshold VTHI = 2V + ½ (2V) = 3V VTLO = 2V - ½ (2V) = 1V Note: The maximum value for VTHI = 5.2V and the minimum value for VTLO = 0.4V. Also VTHI - VTLO >= 0.2V. TABLE 6. HOLT INTEGRATED CIRCUITS 7 HI-8436 REGISTER DESCRIPTIONS (cont.) SO H SO YS H 5 SO YS H 4 SO YS H 3 SO YS H 2 SO YS H 1 YS 0 SUPPLY/OPEN THRESHOLD CENTER VALUE AND HYSTERESIS REGISTER: SOCENHYS Read: SPI Op-code 0xBC Write: SPI Op-code 0x3C X X 7 6 MSB 4 3 2 1 0 LSB SO C SO VA C L5 SO VA C L4 SO VA C L3 SO VAL C 2 SO VA C L1 VA L0 Reset Value 00 DATA BYTE 1 5 [Opcode, DB1, DB0] X X Bit Name R/W Default Description 7 6 MSB DATA BYTE 0 5 4 3 2 1 0 LSB DATA WORD 1 7-6 - R/W 0 Not Used. 5-0 SOHYS5-0 R/W 0 Supply/Open Hysteresis. For all inputs programmed to be Supply/Open sensors the hysteresis is set by these 6 bits. Hysteresis = 0.2V x SOHYS. R/W 0 Not Used. SOCVAL5-0 R/W 0 Supply/Open Threshold Center Value. For all inputs programmed to be Supply/Open sensors the center threshold is set by these 6 bits. Center Threshold = 0.1V x SOCVAL. DATA WORD 0 7-6 5- 0 - VTHI = Threshold center value + ½ Hysteresis, Max limit = 5.2V, Min limit = 0.6V VTLO = Threshold center value - ½ Hysteresis, Max limit = 5.0V, Min limit = 0.4V Example: Supply/Open sensor with VTHI = 5V and VTLO = 2V: a) Program SOHYS Hysteresis = VTHI - VTLO = 0.2V x SOHYS SOHYS = (5V - 2V)/(0.2V) = 15 LSB b) Program SOCVAL Center Value = (VTHI + VTLO) / 2 = 0.1V x SOCVAL SOCVAL = (5V + 2V) / (2 x 0.1) = 35 LSB c) write 0x3C 0x0F 0x23 to SPI 0x3C writes to the Supply/Open Threshold and Hysteresis Registers. 0x0F = 15 LSB x 0.2V/LSB = 3V Hysteresis 0x23 = 35 LSB x 0.1V/LSB = 3.5V Center Value VTHI = 3.5 + ½ (3) = 5V VTLO = 3.5 - ½ (3) = 2V Note: The maximum value for VTHI = 5.2V and the minimum value for VTLO = 0.4V. Also VTHI - VTLO >= 0.2V. TABLE 7. HOLT INTEGRATED CIRCUITS 8 HI-8436 REGISTER DESCRIPTIONS (cont.) SENSOR OUTPUT STATUS REGISTER: SO<31:0> THIS 32 BIT REGISTER IS ACCESSED BY THE FOLLOWING 5 SPI COMMANDS For GND/Open inputs, SO<n> = “0” if the SENSE<n> pin is open or > VTHI SO<n> = “1” if the SENSE<n> pin is <= VTLO For Supply/Open inputs, SO<n> = “1” if the SENSE<n> pin is open or < VTLO SO<n> = “0” if the SENSE<n> pin is >= VTHI SO <7 SO > < SO 6> < SO 5> < SO 4> < SO 3> <2 SO > < SO 1> <0 > SENSOR STATUS BANK 0 REGISTER: SO<7:0> Read: SPI Op-code 0x90 Write: NA, read only DATA BYTE 0 7 6 MSB Reset Value 00 [Opcode, DB0] Bit Name 7-0 SO<7:0> R/W Default R 0 5 4 3 2 1 0 LSB Description Sensor output status, SO<7:0> reports the state of SENSE<7:0>. SO Read: SPI Op-code 0x92 Write: NA, read only DATA BYTE 0 7 6 MSB Reset Value 00 [Opcode, DB0] Bit Name 7-0 SO<15:8> <1 SENSOR STATUS BANK 1 REGISTER: SO<15:8> SO 5> < SO 14> < SO 13> < SO 12> < SO 11> <1 SO 0> < SO 9> <8 > TABLE 8. R/W Default R 0 5 4 3 2 1 0 LSB Description Sensor output status, SO<15:8> reports the state of SENSE<15:8>. Read: SPI Op-code 0x94 Write: NA, read only DATA BYTE 0 7 6 MSB Reset Value 00 [Opcode, DB0] Bit Name 7-0 SO<23:16> <2 SO SENSOR STATUS BANK 2 REGISTER: SO<23:16> SO 3> < SO 22> < SO 21> < SO 20> < SO 19> <1 SO 8> < SO 17> <1 6> TABLE 9. R/W Default R 0 5 4 3 2 1 0 LSB Description Sensor output status, SO<23:16> reports the state of SENSE<23:16>. Read: SPI Op-code 0x96 Write: NA, read only DATA BYTE 0 7 6 MSB Reset Value 00 [Opcode, DB0] Bit Name 7-0 SO<31:24> <3 SO SENSOR STATUS BANK 3 REGISTER: SO<31:24> SO 1> < SO 30> < SO 29> < SO 28> < SO 27> <2 SO 6> < SO 25> <2 4> TABLE 10. R/W Default R 0 5 4 3 2 1 0 LSB Description Sensor output status, SO<31:24> reports the state of SENSE<31:24>. TABLE 11. HOLT INTEGRATED CIRCUITS 9 HI-8436 REGISTER DESCRIPTIONS (cont.) SO <3 SO 1> < SO 30> < SO 29> < SO 28> < SO 27> <2 SO 6> < SO 25> <2 4> SENSOR STATUS ALL BANKS REGISTER: SO<31:0> Read: SPI Op-code 0xF8 Write: NA, read only DATA BYTE 3 7 6 MSB 4 3 2 1 0 LSB SO <2 SO 3> < SO 22> < SO 21> < SO 20> < SO 19> <1 SO 8> < SO 17> <1 6> Reset Value 00 5 [Opcode, DB3, DB2, DB1, DB0] DATA BYTE 2 5 4 3 2 1 0 LSB SO <1 SO 5> < SO 14> < SO 13> < SO 12> < SO 11> <1 SO 0> < SO 9> <8 > 7 6 MSB DATA BYTE 1 4 3 2 1 0 LSB < SO 6> < SO 5> < SO 4> < SO 3> <2 SO > < SO 1> <0 > 5 SO SO <7 > 7 6 MSB DATA BYTE 0 Bit Name 31-0 SO<31:0> R/W Default R 0 7 6 MSB Description 5 4 3 2 1 0 LSB Sensor output status, SO<31:0> reports the state of SENSE<31:0>. TABLE 12. SPI Format Examples SO SO<7> SO<6> SO<5> SO<4> SO<3> SO<2 > SO<1> <0 > Example 1. Single Data Byte, Read Sense Data in SENSE BANK 0 (Op-Code 0x90). SPI Op-Code Data Word Bits 1 0 0 1 0 0 0 0 LSB MSB 1 0 1 1 1 0 1 1 MSB LSB Data Byte 0 SPI Op-Code Threshold Center Value Hysteresis Value 0 0 1 1 1 0 1 0 LSB MSB 0 0 0 0 0 1 1 0 MSB G O G CV O A G CV L5 O A G CV L4 O A G CV L3 O A G CV L2 O A C L1 VA L0 G O G HY O S G HY 5 O S G HY 4 O S G HY 3 O S G HY 2 O S H 1 YS 0 Example 2. Double Data Byte, Write GND/Open Threshold Center Value and Hysteresis (Op-Code 0x3A) . 0 0 0 0 1 1 1 1 LSB LSB MSB Data Byte 1 Data Byte 0 SO SO<31 SO<3 > 0 SO<29> > < SO 28 < SO 2 > 7> SO<26 > SO<2 <25> SO 4> < SO 23 > SO<2 2> < SO 21 SO<2 > 0 SO19>> SO<18 SO<1 > <17> 6 SO > SO<1 5 SO<1 > 4 < SO 13> SO<1 > 2 SO<11 > SO<10> SO<9>> <8 > SO < SO 7> SO<6> SO<5> SO<4> SO<3> SO<2 > SO<1> <0 > Example 3. 4 Data Byte, Read all sense values, SENSE ALL BANKS (Op-Code 0xF8). SPI Op-Code 1 1 1 1 1 0 0 0 MSB LSB 0 0 0 0 1 0 0 1 LSB MSB Data Byte 3 1 1 1 0 0 0 1 0 LSB MSB Data Byte 2 1 1 0 0 0 1 0 1 0 0 1 1 0 1 1 0 LSB MSB MSB Data Byte 1 TABLE 13. HOLT INTEGRATED CIRCUITS 10 LSB Data Byte 0 HI-8436 FUNCTIONAL DESCRIPTION FUNCTION TABLE Table 14. Function Table OVERVIEW The HI-8436 is comprised of 32 sensors arranged in 4 banks of 8 inputs, easily accessible via a four wire SPI communication bus. Each bank of sensors can be programmed as either GND/Open or Supply/Open. The state of each sensor can be read out through the SPI. The GND/Open high/low thresholds can be programmed independently of the Supply/Open high/low thresholds. Table 14 summarizes basic function selection and Table 16 gives more details on possible threshold values. An internal test mode is available which sets the input to each sensor comparator to the test value as programmed by the Test Mode Data Register. PSEN_n SO_n VWET_n Open or > VTHI L (GND/OPEN) L ** < VTLO L (GND/OPEN) H ** Open or < VTLO H (V+/OPEN) H open > VTHI H (V+/OPEN) L open H = VLOGIC, L = GND VTHI = Threshold Center Value + ½ Hsyteresis VTLO = Threshold Center Value - ½ Hysteresis **For GND/Open applications with thresholds > VLOGIC use VWETn VWETn > VTHI/0.9 + 2.75V INITIALIZATION AND RESET The HI-8436 generates a full reset upon application of power. This power-on-reset (POR) sets all registers to their default values. The part can also be initialized to the full reset state by applying a 100ns active low pulse to the external nMR pin. A software reset is also possible via the SPI by writing a “1’ to CTRL<1>. This reset is the same as the full reset except the part is held in the reset mode until the CTRL<1> bit is written back to a “0”. CONFIGURATION The user configures the HI-8436 for specific applications by: 1) Programming the sensor type for each of the 4 banks. 2) Convert the required VTHI and VTLO into center and hysteresis values as shown in example below. 3) For GND/Open sensors, VWETn must be set greater than VTHI/0.9 + 2.75V. PROGRAMMING THRESHOLDS The HI-8436’s on-chip DAC takes the 6-bit programmed center and hysteresis values from the Threshold Center Value and Hysteresis Registers (GOCENHYS and SOCENHYS) and converts them to VTHI and VTLO values. Maximum and minimum values may be found in Table 16. The gain of the DAC is 0.1V per LSB. VTHI = center value + ½ hysteresis VTLO = center value - ½ hysteresis SENSE_n To program the thresholds: a) Select VTHI and VTLO. b) Hysteresis = (VTHI - VTLO) / (0.2V/LSB) c) Center Value = (VTHI - VTLO)/2 / (0.1V/LSB) d) Program the register. GND/OPEN SENSING For GND/Open sensing, the PSENn bit is set to 0. Referring to the Block Diagram, Figure 2, this selection will connect a 3.3KΩ pull-up resistor through a diode to VLOGIC. This resistor gives extra noise immunity for detecting the open state while providing relay wetting current. The user programs the desired threshold/hysteresis levels and then determines the open input voltage to set VWETn. OPEN INPUT VOLTAGE For correct operation, the VSENSE_n when open, must be higher than VTHI so SO_n will be low. This condition requires VWET to be set greater than (VTHI/0.9 + 2.75V). In the case where VTHI ≤ 1.4V, VWET may be left OPEN. Various ARINC standards such as ARINC 763 define the standard “Open” signal as characterized by a resistance of 100KΩ or more with respect to signal common. The user should consider this 100KΩ to ground case when setting the thresholds. HOLT INTEGRATED CIRCUITS 11 HI-8436 FUNCTIONAL DESCRIPTION (cont.) WETTING CURRENT WETTING CURRENT For GND/Open applications with VWET open, the wetting current with the input voltage at GND is simply (VLOGIC 0.75)/3.3K. When applying a higher voltage at VWET_n the wetting current is (VLOGIC - 0.75)/3.3K + (VWET 4.2)/127K. Additional wetting current can be achieved by placing an external resistor and a diode between VWET_n and the individual sense inputs. For the V+/Open case the wetting current into the sense input is simply the current sunk by the effective 30KΩ to GND. For VSENSE_n = 28V, IWET is 1ma. See Figure 8. SUPPLY/OPEN SENSING When programmed as Supply/Open sensors, PSEN_n is set to a logic 1. Referring to Figure 2, a 32KΩ resistor in series with a diode is switched to provide a pull down in addition to the 400KΩ of the comparator input divider to GND. The user programs the desired threshold and hysteresis levels. VWET_n must be left open for any bank that is programmed as Supply/Open sensors. THRESHOLD SELECT TEST MODE Writing a high in CTRL<0> puts the HI-8436 into the test mode. Referring to Figure 2, when in the test mode each of the internal inputs to the sense comparators are set to either a high or low. Since the input sense pin is isolated by a 200KΩ resistor, this test mode will not disturb the actual status of the input pin. By programming the Test Mode Data Register, one of four input data patterns can be selected. See Table 5 on page 6 for options. The comparator results are read through the SPI just as in normal operation. Before entering Test Mode the sensors must be programmed with valid threshold values. The threshold selections are handled the same was as stated above for the GND/OPEN case. See Table 16 for maximum and minimum values. Figure 8. Input Current Vs. Input Voltage HOLT INTEGRATED CIRCUITS 12 HI-8436 FUNCTIONAL DESCRIPTION (cont.) 96 Channel Sensor Application using HI-8436 nCS_1 nCS_2 nCS_3 SCK nCS SI SO GP1 GP2 GP3 HI - 8436 Device 1 From Sense Inputs 31-0 32 SENSE<31-0> SCK nCS SI SO Host Controller SO SI SCK HI - 8436 Device 2 From Sense Inputs 63-32 32 SENSE<31-0> SCK nCS SI SO SO SI SCK HI - 8436 Device 3 From Sense Inputs 95-64 32 SENSE<31-0> Figure 9. Multiple Chip Connection HOLT INTEGRATED CIRCUITS 13 HI-8436 FUNCTIONAL DESCRIPTION (cont.) LIGHTNING PROTECTION All SENSE_n inputs are protected to RTCA/DO-160G, Section 22, Categories AZ and BZ, Waveforms 3, 4, 5A, with no external components. In addition, all inputs are also protected to ZZ, Waveforms 3 and 5B, to provide more robustness in composite airframe applications. Table 15 and Figure 10 give values and waveforms. Waveforms 3/3 4/1 5A/5A 5B/5B Voc (V) / Isc (A) Voc (V) / Isc (A) Voc (V) / Isc (A) Voc (V) / Isc (A) 2 250/10 125/25 125/125 125/125 Z 500/20 300/60 300/300 300/300 3 600/24 300/60 300/300 300/300 Level Table 15. Waveform Peak Amplitudes V/I (%) Peak 1.0 Voltage/Current Waveform 3 Voltage Waveform 4 V (%) Peak 1.0 50% 0.5 0.8 0.0 0.5 -0.5 0.3 -1.0 t I/V (%) 1.0 Peak 1us/div. Current/Voltage Waveform 5A 0.0 T1 I/V (%) 1.0 0.8 50% Peak t T1 = 6.4µs +/-20% T2 = 69µs +/-20% Current/Voltage Waveform 5B 0.8 50% 0.5 0.5 0.3 0.3 0.0 T2 T1 t T2 T1 = 40µs +/-20% T2 = 120µs +/-20% 50% 0.0 T1 Figure 10. Lightning Waveforms HOLT INTEGRATED CIRCUITS 14 t T2 T1 = 50µs +/-20% T2 = 500µs +/-20% HI-8436 FUNCTIONAL DESCRIPTION (cont.) Table 16. Configuration examples and allowed threshold values -55C to 125C. Guaranteed High Threshold* Guaranteed Low Threshold* 0.4V VTHI + 0.3V VTLO - 0.2V 5.2V 0.4V VTHI + 1.0V VTLO - 0.2V 5.2V 0.4V VTHI + 1.0V VTLO - 0.2V Programmed Programmed VTLO VTHI VLOGIC VWET Pin PSENn Operation 3.0V to 3.6V OPEN L GND/OPEN 1.4V 3.0V to 3.6V 8.5 to 28V L GND/OPEN 3.0V to 3.6V OPEN H V+/OPEN NOTE: VTHI = Center Value + 0.5 x Hysteresis, VTLO = Center Value - 0.5 x Hysteresis *: See Figure 11 for guaranteed tolerance for programmed VTHI and VTLO Threshold Tolerance 7 6 Voltage (V) 5 4 Max limit Programmed Min limit 3 2 1 0 0 1 2 3 4 5 VTHI or VTLO (V) Figure 11: Threshold tolerance over Programmed value HOLT INTEGRATED CIRCUITS 15 6 HI-8436 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Voltages referenced to Ground Supply Voltage Supply Voltage (VLOGIC) ......................... VLOGIC -0.3V to +7V ................................. 3.0V to 3.6V VWET_n ................................. 4.5V to 36V VWETn .......................... Logic Input Voltage Range -0.3V to +80V Sense_n ............................... ................ -0.3V to VLOGIC+0.3V Discrete Input Voltage Range (DC) (AC, 60 - 400Hz) ................... -80V to +80V ................... 115Vrms Continuous Power Dissipation (TA=+70°C) QFN (derate 21.3mW/°C above +70°C) ........ QFP (derate 10.0mW/°C above +70°C) ........ Solder Temperature (reflow) Digital Inputs .......................... 0 to VLOGIC -4.0V to 36V Operating Temperature Range Industrial Screening ............. -40°C to +85°C Hi-Temp Screening ............. -55°C to +125°C 1.7W 1.5W ............................. 260°C Junction Temperature ............................. 175°C Storage Temperature ............................ -65°C to -150°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. D.C. ELECTRICAL CHARACTERISTICS VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYM CONDITION MIN TYP MAX UNITS DISCRETE INPUTS SENSE V+/OPEN Resistance to Ground RIN Threshold DAC Gain VTHAC 1 DAC bit = 0.1V. Guaranteed monotonic Max Threshold High (V+ State Input Voltage) VTHIMAX VTHI = Center Value + ½ Hysteresis Input voltage to give Low output Min Threshold Low (Open State Input Voltage) VTLOMIN VTLO = Center Value - ½ Hysteresis Input voltage to give High output Input Current at 28V IIN28 30 KΩ 0.1 V/bit Refer to Figure 11 VTHI - VTLO ≥ 0.2V VTHI - VTLO ≥ 0.2V VIN = 28V HOLT INTEGRATED CIRCUITS 16 Refer to Figure 11 V V 0.95 mA HI-8436 D.C. ELECTRICAL CHARACTERISTICS (cont) VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYM CONDITION MIN TYP MAX UNIT DISCRETE INPUTS SENSE GND/OPEN Resistance in series with diode to VLOGIC RIN 3.3 KΩ Resistance in series with diode to VWET RW 28 KΩ 0.1 V/bit Threshold DAC Gain VTDG 1 DAC bit = 0.1V. Guaranteed monotonic Max Threshold High (Open State Input Voltage) VTHIMAX VTHI = Center Value + ½ Hysteresis Input voltage to give Low output Min Threshold Low (Ground State Input Voltage) VTLOMIN VTLO = Center Value - ½ Hysteresis Input voltage to give High output Input Current at 0V Refer to Figure 11 VTHI - VTLO ≥ 0.2V VTHI - VTLO ≥ 0.2V Refer to Figure 11 V V IIN0 VIN = 0V, VWET = open VIH Input Voltage HI VIL Input Votage LO 30% VLOGIC VIN = VLOGIC, 30KΩ pull down 125 μA VIN = GND 0.1 μA -0.65 mA LOGIC INPUTS Input Voltage Input Current, SI ISINK ISOURCE Input Current, MRB, CSN 70% VLOGIC VIN = VLOGIC 0.1 μA VIN = GND , 30KΩ pull up 125 μA VOH IOH = -100μA 90% VLOGIC VOL IOL = 100μA IOL VOUT= 0.4V IOH VOUT = VLOGIC - 0.4V ISINK ISOURCE LOGIC OUTPUTS Output Voltage Output Current Output Capacitance 10% 1.6 mA -1.0 15 CO VLOGIC mA pF SUPPLY Operating VLOGIC range Operation VWET range VLOGIC 3.0 3.6 V VWET 4.5 28 V All Sense Pins Open 15 mA All Inputs for bank = 0V, VWETn = 28V 35 mA VLOGIC Current IDD1 VWETn Current IVWETn HOLT INTEGRATED CIRCUITS 17 HI-8436 AC ELECTRICAL CHARACTERISTICS VDD = 3.3V, TA = Operating Temperature Range LIMITS PARAMETER SYMBOL MIN TYP MAX UNITS SPI INTERFACE TIMINGS SCK clock period tCYC 50 ns CS active after last SCK rising edge tCHH 5 ns CS setup time to first SCK rising edge tCES 5 ns CS hold time after last SCK falling edge tCEH 5 ns CS inactive between SPI instructions tCPH 55 ns SPI SI Data set-up time to SCK rising edge tDS 10 ns SPI SI Data hold time after SCK rising edge tDH 10 ns SCK rise time tSCKR 10 ns SCK fall time tSCKF 10 ns SCK pulse width high tSCKH 20 ns SCK pulse width low tSCKL 20 ns SO valid after SCK falling edge tDV 20 SO high-impedance after SCK falling edge tCHZ 20 MR pulse width tMR 100 ns ns SENSOR TIMINGS Delay, change at sense input to valid status in SO_n 1 μs Delay, change of Threshold to valid status in SO_n 1 μs t CPH t CYC CS tCHH t SCKF t CES t CEH SCK t DS t DH SI t SCKR MSB LSB t CPH FIGURE 12. SPI Serial Input Timing CS t CYC t SCKH t SCKL SCK t CHZ t DV SO Hi Impedance MSB FIGURE 13. SPI Serial Output Timing HOLT INTEGRATED CIRCUITS 18 LSB Hi Impedance HI-8436 ORDERING INFORMATION HI - 8436xx x x PART NUMBER Blank LEAD FINISH Tin / Lead (Sn /Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) F PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I NO T -55°C TO +125°C T NO PART NUMBER PACKAGE DESCRIPTION 8436PQ 44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PMQS) 8436PC 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) HOLT INTEGRATED CIRCUITS 19 HI-8436 REVISION HISTORY P/N Rev DS8436 New Date 08/01/13 Description of Change Initial Release. HOLT INTEGRATED CIRCUITS 20 PACKAGE DIMENSIONS inches (millimeters) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) Package Type: 44PMQS .009 MAX. (.23) .0315 BSC (.80) .394 ± .004 (10.0 ± .10) SQ. .520 ± .010 (13.20 ± .25) SQ. .014 ± .003 (.37 ± .08) .035 ± .006 (.88 ± .15) .012 R MAX. (.30) See Detail A .079 ± .008 (2.0 ± .20) .096 MAX. (2.45) .005 R MIN. Detail A (.13) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) Electrically isolated pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation. .276 BSC (7.00) 0° £ Q £ 7° inches (millimeters) Package Type: 44PCS .216 ± .002 (5.5 ± .05) .020 BSC (0.50) .276 BSC (7.00) .216 ± .002 (5.5 ± .05) Top View Bottom View .010 (0.25) typ .039 max (1.00) .008 typ (0.2) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 21 .016 ± .002 (0.40 ± .05)