ML2002 Preliminary ML2002 Series Static/Half Duty LCD COG Driver Application Features General Purpose Clock High quality instrument Telephone, mobile phone Automotive Handheld Device like PDA, MP3, or PMP A Gold Bump Chip which can reduce pin count and area. Simplest design with no charge pump to supply high voltage to LCD Only 5 pin is needed which can reduce space. Low operating current Can disable internal clock to reduce current. Wide Logic & LCD power supply: 2.5V to 6.0V No need to add external voltage regulator Static or 1/2 Duty driving with 1/2 Bias Number of segments: (Static) 48, (1/2 Duty) 96 Cascading structure to increase the number of driving segments, it’s more flexible for different application. Build-in LCD voltage driver, crystal oscillator, internal RC oscillator and display control circuit. Offer best contrast and widest viewing angle of TN LCD technology especially in static mode. No temperature compensation is needed for Topr = -40oC to 80oC. General Description ML2002 (COG) LCD driver can be cascaded to increase the number of segments drive, with Static driving it can form a single piece of 48 (1 ICs) or 96 (2 ICs cascaded) segments driver. With 1/2 Duty, the number of segment drive would be doubled. It targets at custom TN LCD COG Module product which requires the best quality of TN LCD technology and small to medium number of segment display. ML2002 series driver offers the best contrast, the widest viewing angle, the widest range of operating voltage and temperature when compared to the high duty cycle driver. EMI and Noise protection circuit has been added which tailor made for COG application. Ordering Information Part Number Description Package Form ML2002-1U One ML2002 LCD driver Gold Bump Die ML2002-2U Two ML2002 LCD driver Gold Bump Die P1/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary Block Diagram Absolute Maximum Ratings Parameter Symbol Condition MIN MAX Unit Supply voltage VDD -0.5 +6.0 V Supply Current IDD -50 +50 mA Input Voltage VIN GND-0.3 VDD +0.3 V Output Voltage VOUT GND-0.3 VDD +0.3 V DC input Current IIN -10 +10 mA DC output Current IOUT -10 +10 mA Storage temperature Tstg -65 +150 o Total power dissipation Ptot - 400 mW VDD = 3V, no Load P2/13 C Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary DC Characteristic VDD = 3.0V; Tamb = 25oC ; unless otherwise specified Parameter Symbol Condition Supplies Supply voltage VDD Supply Current IDD Disable Oscillator and 1/2 PVDD opamp Supply Current IDD Enable Oscillator Supply Current IDD Enable Oscillator and Internal 1/2 PVDD opamp Logic LOW-level input voltage VIL HIGH-level input voltage VIH LOW-level output current IOL VOL = 1.0V HIGH-level output IOH VOH = 2.0V current LCD outputs Output resistance at pads RSEG S1 to S40 Output resistance at pads RCOM COM1A and COM1B MIN TYP MAX Unit 2.5 - 0.1 6.0 0.5 V uA - 25 80 60 100 uA uA GND 0.7*VDD 1 -1 - 0.3*VDD VDD - V V mA mA - 85 150 ohm - 45 100 ohm MIN 21 TYP 32 MAX 48 Unit kHz 0.4 - - us 0.4 - - us - - 10 us - - 10 us 1 - 250 kHz AC Characteristic VDD =3.0V; Tamb = 25oC; unless otherwise specified Parameter Symbol Conditions Oscillator frequency at foout pad OOUT FIN, LOAD, DIN, DCLK tH High time FIN, LOAD, DIN, DCLK tL Low time FIN, LOAD, DIN, DCLK tr Rise time FIN, LOAD, DIN, DCLK tf Fall time DCLK Frequency FDCLK P3/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary Timing Diagram for slave mode display With MS connected to GND, it represents it is in slave mode, it will treat all the DIN data as display data and will be sent to ML2002’s display shift register directly through DIN and DCLK. To Load display data onto the screen, LAI need to be high, then a rising edge of DCLK would load the display, the LAI need to keep low again. Functional Description There are 48 Segments in Static Mode, and 96 Segments in 1/2 Duty Mode with 1/2 Bias. The display data should be input in reverse order, for static it’s starting from SEG48, SEG47… SEG2 to SEG1, for 1/2 duty it’s starting from SEG48-COMB, SEG48-COMA … SEG1-COMB to SEG1-COMA for proper display of data. When updating the display, it will require inputting 48 Segments in Static Mode and 96 Segments in 1/2 Duty Mode. i) Internal Power on reset At power on the ML2002 will reset the internal display Data RAM as cleared. P4/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary ii) Oscillator The LCD driving signal of ML2002 is clocked either by the built-in oscillator, crystal oscillator or from an external clock. a) Internal clock When the internal oscillator is used, BIOEN should be connected to GND and the OOUT should be connected to FIN. The internal oscillator will oscillate at 32 kHz and the frequency is independent in the range of 2.5V < VDD < 6.0V . Then connect OOUT to FIN. b) Crystal clock When using the crystal oscillator, BCOEN is connected to GND, then connect the crystal to OSC+, and OSC-. Then connect OSC- to FIN. The OSC+ and OSC- should connect as: c) External clock When using an external clock, BCOEN & BIOEN is connected to VDD then connects the external clock to FIN (32 KHz) or LCLK (125Hz) iii) Timing ML2002 have several frequencies of clock signal for the users to choose for the LCD display clock (ie. LCLK) and the blink clock (ie.BCLK). They include the following clock signals: Frequency of Clock Signal at FIN = 32 kHz 256/128 Hz 128/64 Hz 4 Hz 2 Hz 1 Hz Actual Divider of FIN 1/256(1/2 Duty) or 1/128(Static) 1/128(1/2 Duty) or 1/64(Static) 1/8192 1/16384 1/32768 Target Input Pin LCLK BCLK iv) Segment outputs ML2002 has 48 segment outputs which should be connected directly to the LCD. If less than 48 segments, the unused segments should be left open circuit. v) Common outputs ML2002 consists of 2 common signals (ie. COM1A & COM1B). The common outputs should be left open-circuit if the outputs are unused. Users can disable the COM1A and COM1B by connecting the CEN1A and CEN1B to VDD respectively. The common outputs will change to GND after disabling it. vi) Blink ML2002 has a blink function that users shall connect BEN to GND and input the blink clock (ie. BCLK) either by connecting ML2002 output clock signal from Frequency Divider or an external clock signal. Users shall disable blink function by connecting BEN to VDD. P5/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary Pad Configuration Chip Size : Part Number Description Chip Size ML2002-1U One ML2002 LCD driver 3660 x 660 ML2002-2U Two ML2002 LCD driver 7320 x 660 Chip Thickness : 700 um + 25 um Gold Bump Pad Size : 32 um x 72 um Gold Bump Height : 18 um + 2 um Note : The die faces up in the diagram P6/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary ＊ Pad Orientation and Alignment Mark: Note: Pad 1, 49 and 50 are DUM Pads which must be open. P7/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary Application Circuit ML2002 Single Chip Connection 1. ML2002 1U Static Slave Mode 2. ML2002 1U 1/2 Duty Slave Mode P8/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary ML2002 Cascode Structure Connection 1. ML2002 2U 1/2Duty-1/2Duty Slave-Slave Mode Working Glass Size: Length = 64.80 V.A Width = 35.40 V.A (Unit: mm) P9/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary 2. ML2002 2U Static Slave-Slave Mode Working Glass Size: Length = 76.00 V.A Width = 59.95 V.A (Unit: mm) P10/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary Pin Description SYMBOL PAD BRES I I I I I I/O O LGND INT LVDD MS DIN DCLK LAI LAO CEI CEO DOUT CNT Q15 FIN 4,2,1Hz 256/125 Hz 125/62 Hz LCLK SEG1 .. SEG48 COM1A / B PVDD 1/2 PVDD 1/2 Duty CEN1A , CEN1B T0 OOUT COEN IOEN HPVDDEN BEN BCLK OSC+ / SYNC TFI SYEN TOUT DUM1,2,3 DESCRIPTION I O O I O I O O O I O O I I I I O I I External reset input (active LOW) Logic Ground Alarm interrupt output Logic Supply voltage Input “0”, for slave mode Data line input Data clock input It is an input pin which LOAD the display onto the LCD screen during rising edge. Send out LOAD signal to the cascade slave ML2002 for displaying data onto LCD screen. Enable Chip for receive data/command in the DIN pin Send out chip enable signal to the following cascade slave IC Data output from the display data RAM Input clock, count number of rising edge clock Output High on the 16th clock from CNT 32768Hz Oscillator input 4, 2, 1Hz clock output 125Hz clock output for static/ 250 clock output for 1/2 duty 62Hz clock output for static/125 clock output for 1/2 duty LCD Clock signal frequency Segment output Common output Power VDD supply 1/2 PVDD LCD driving voltage “1” – Halfduty, “0” – Static Common Enable. “0” – Enable, “1” – Disable Test mode. “0” – Normal mode, “1” – Testing Mode 32K internal clock output Crystal oscillator enable. “0” – Enable, “1” – Disable 32K internal clock enable. “0” – Enable, “1” – Disable I 1/2 PVDD enable. “0” – Enable, “1” – Disable I I I I/O I I O - Blink control circuit enable “0” – Enable, “1” – Disable Blink clock input Crystal oscillator input To synchronize COMMON signal to the following cascade IC Master mode 2/4 pin interface, “1” - 2pin , “0” - 4pin SYNC enable. SYEN is “1” – SYNC output, “0” – SYNC will be high impredence. When select 4pin interface, it would output timer data. Dummy Pad, Left it open only Note : 1. In cascade format of ML2002(ie. ML2002-2U and –3U), one pin is the input of current ML2002 and the other is for the connection with the corresponding input pin of next ML2002. 2. Condition : FIN = 32 KHz Clock. P11/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary Application Note 1. To ensure the good flip-chip assembly quality, we suggest flip-chip bonding house add a “CHECK” pin for each COG module as shown on the section of “Application Example”. Pin “LOAD” and Pin “CHECK” shall be connected together if the flip-chip assembly is in good condition. The measured resistance between Pin “LOAD” and Pin “CHECK” shall not more than 5 kohm. 2. The resistance of ITO glass shall between 15 ohm/□ to 25 ohm/□. 3. Each Common (ie. COM1A and COM1B) shall not cover more than 2,000 mm2 area. In case the Viewing area of LCD has to be more than 2,000 mm2, IOEN pin has to be connected to outside. At the time where data is transferring into the IC, internal oscillator has to be disabled through IOEN pin to prevent abnormal behavior. When data transfer finishes, internal oscillator has to be enabled again. Suggested programming steps: 1 Disable internal oscillator through IOEN pin 2 Delay (Necessary for fast MCU) 3 Transfer data through DIN, DCLK, LOAD 4 Delay (Necessary for fast MCU) 5 Enable internal oscillator through IOEN pin P12/13 Version 0.6 Preliminary, Sept 2011 ML2002 Preliminary Example : Note : COM1A and COM1B shall cover half of the Viewing Area (ie. Area = 1,300mm2) Each Common shall not connect to each other. Revision History Version 0.1 – Preliminary Version 0.2 – Change Alignment mark co-ordinate on page 7 Add application note on page 12 Modify Application Circuit on page 8 – 10. Updating Feature list on page 1 Updating Functional Description on page 4 Version 0.3 – Change Supply current condition with disable oscillator and internal PVDD opamp Remove Real time clock in block diagram Version 0.4 – Add Application Note when glass size area is larger than 2000mm2 for each COM Version 0.5 – Add Timing diagram for using large LCD panel Version 0.6 – Add remark on page 8, for FIN connect to GND if OOUT don’t connect with FIN. P13/13 Version 0.6 Preliminary, Sept 2011