MP2004 Dual, Low Noise, High PSRR 200mA Linear Regulator The Future of Analog IC Technology DESCRIPTION FEATURES The MP2004 is a dual-channel, low noise, low dropout and high PSRR linear regulator. The output voltage of MP2004 ranges from 1.2V to 5V and 1% accuracy by operating from a +2.5V to +6.0V input. The MP2004 can supply up to 200mA of load current at each channel. • • • • • • • The MP2004 uses an internal PMOS as the pass element, which consumes 114μA supply current (both LDOs on) at no load condition. The EN1 and EN2 pins control each output respectively. When both channels shutdown simultaneously, the chip will be turned off and consume nearly zero operation current which is suitable for battery-power devices. The MP2004 features current limiting and over temperature protection. Two LDOs in a TSOT23-6 Package Up to 200mA Output Current (Per Channel Two Enable Pins Control Each Output 69dB PSRR (100Hz) 95μVRMS Low Noise Output 110mV Dropout at 100mA Load Very Fast Transient Responses with Small Output Capacitor Current Limiting and Thermal Protection • APPLICATIONS • • • • Cellular Phones Laptop PCs Hand-held Equipment Netbook Computing “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. It is available in a small 6-pin TSOT23 package. TYPICAL APPLICATION EN1 EN1 EN2 OUT2 OUT2 COUT2 EN2 OUT1 OUT1 COUT1 MP2004 IN IN GND MP2004 Rev. 0.92 4/6/2010 CIN www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 1 MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR ORDERING INFORMATION* Part Number VOUT1 VOUT2 MP2004DJ-JG-LF-Z MP2004DJ-ZS-LF-Z MP2004DJ-PN-LF-Z MP2004DJ-DD-LF-Z MP2004DJ-SJ-LF-Z MP2004DJ-MG-LF-Z 2.5V 5.0V 3.0V 1.85V 3.3V 2.8V 1.8V 3.3V 2.85V 1.85V 2.5V 1.8V Package TSOT23-6 Temperature Top Marking -40°C to +85°C 2B 2L 3L 4L 5L 6L * Other output voltage versions between 1.2V and 5.0V are available in 100mV increments. Contact factory for availability. OUTPUT GUIDE*** ORDERING GUIDE** MP2004DJ- -LF-Z Code C B F W G D Y H E J K VOUT2 VOUT1 Package Type J: TSOT23-6 ** For RoHS Compliant Packaging, add suffix - LF (e.g. MP2004DJ-LF); For Tape and Reel, add suffix -Z (e.g. MP2004DJLF-Z). VOLTAGE VOUT 1.2 1.3 1.5 1.6 1.8 1.85 1.9 2.0 2.1 2.5 2.6 Code T L M N V P Q X R S Z SELECTOR VOUT 2.65 2.7 2.8 2.85 2.9 3.0 3.1 3.15 3.2 3.3 5.0 *** Code in Bold are standard versions. For other output voltages between 1.2V and 5.0V contact factory for availability. Minimum order quantity on non-standard versions is 25,000 units. PACKAGE REFERENCE TOP VIEW OUT1 IN 6 5 4 1 2 3 OUT2 GND MP2004 Rev. 0.92 4/6/2010 EN1 EN2 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 2 MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR ABSOLUTE MAXIMUM RATINGS (1) Supply Input Voltage ................................. 6.5V Continuous Power Dissipation (TA = +25°C)(2) ........................................................... 0.45W Operation Temperature Range ... -40°C to 85°C Storage Temperature Range ..... -65°C to 150°C Lead Temperature (Soldering, 10sec) .....260°C Recommended Operating Conditions (3) Supply Input Voltage.......................2.5V to 6.0V Enable Input Voltage .........................0V to 6.0V Junction Temperature Range . –40°C to +125°C MP2004 Rev. 0.92 4/6/2010 Thermal Resistance (4) θJA θJC TSOT23-6 ..............................220 ....110. . °C/W Notes: 1) Exceeding these ratings may cause permanent damage to the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside its operating conditions. 4) Measured on JESD51-7 4-layer board. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 3 MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR ELECTRICAL CHARACTERISTICS VIN=3.6V, VOUT1=2.5V, VOUT2=1.8V, CIN=COUT1=COUT2=2.2uF, EN1=EN2=VIN, Typical Value at TA=25°C for each LDO unless otherwise noted. Parameter Symbol Output Voltage Accuracy (Load regulation)(5) Maximum Output Current Current Limit ΔVOUT ILOAD = 1mA to 200mA IMAX ILIM Quiescent Current IQ Dropout Voltage (6) VDROP Line Regulation(7) ∆VLINE EN Input High Threshold EN Input Low Threshold EN Input Bias Current Shutdown Supply Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis VIH VIL ISD IGSD TSD ΔTSD Continuous RLoad=1Ω Output PSRR 5) Load Regulation= VOUT[IOUT(MAX) ] − VOUT[IOUT(MIN) ] VOUT(NOM) Min Typ -1 Max Units +1 % 450 mA mA No Load 114 uA IOUT1 = 100mA 110 mV IOUT1 = 200mA VIN =(VOUT+0.4V or 2.5V) to 6V, IOUT=1mA VIN = 2.5V to 6.0V VIN = 2.5V to 6.0V EN= VIN =6.5V EN1 = EN2 = GND 250 mV 10Hz to 100kHz, COUT=2.2μF, ILOAD=1mA 100Hz, COUT = 2.2μF, ILOAD = 100mA Output Voltage Noise Notes: Condition 200 -0.05 +0.05 1.6 0.03 140 10 0.45 300 1 %/V V V nA uA °C °C 95 μVRMS 69 dB × 100(%) 6) Dropout Voltage is defined as the input to output differential when the output voltage drops 100mV below its nominal value. 7) Line Regulation= VOUT[VIN(MAX) ] − VOUT[VIN(MIN) ] [VIN(MAX) − VIN(MIN) ] × VOUT(NOM) × 100(%/V ) PIN FUNCTIONS Pin # 1 2 3 4 5 6 MP2004 Rev. 0.92 4/6/2010 Name VOUT2 GND EN2 EN1 VIN VOUT1 Description Channel 2 Output Voltage Common Ground Channel 2 Enable (Active High). Do Not Float This Pin. Channel 1 Enable (Active High). Do Not Float This Pin. Supply Input Pin Channel 1 Output Voltage www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 4 MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS VIN=3.6V, VOUT1=2.5V, VOUT2=1.8V, CIN=COUT1=COUT2=2.2uF, EN1=EN2=VIN, Typical Value at TA=25°C for Both Channel Enabled. Quiescent Current vs. Temperature Dropout Voltage vs. Temperature 300 200 280 150 260 100 240 50 0 -40 220 -20 0 20 40 60 0.25 80 0.20 70 20 40 60 85 Channel-to-Channel Isolation vs. Frequency 120 100 60 0.10 0.05 0.00 50 -0.05 30 80 40 -0.10 60 40 20 -0.15 20 10 -0.20 -0.25 -40 ILOAD=200mA 0 Power Supply Rejection Ratio vs. Frequency Out Voltage Accuracy vs. Temperature 0.15 200 -40 -20 85 -20 0 20 40 60 0 10 85 100 1000 10000 100000 1000000 0 100 1000 FREQUENCY(Hz) VOUT 10mV/div 10000 100000 1000000 FREQUENCY(Hz) VOUT 10mV/div VOUT 1V/div VIN 1V/div MP2004 Rev. 0.92 4/6/2010 ILOAD 50mA/div VEN 5V/div www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 5 MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR BLOCK DIAGRAM Figure1—Functional Block Diagram OPERATION The MP2004 integrates two low noise, low dropout, low quiescent current and high PSRR linear regulators. It is intended for use in devices that require very low voltage, low quiescent current power such as wireless LAN, batterypowered equipment and hand-held equipment. The MP2004 uses internal PMOSs as the pass elements and features internal thermal shutdown and an internal current limit circuit. Dropout Voltage Dropout voltage is the minimum input to output differential voltage required for the regulator to maintain an output voltage within 100mV of its nominal value. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage of MP2004 is very low. Shutdown The MP2004 can be switched ON or OFF by a logic input at the EN pin. A high voltage at this pin will turn the device on. When the EN pin is low, the regulator output is off. The EN pin should be tied to VIN to keep the regulator output always on if the application does not require the shutdown feature. Do not float the EN pin. MP2004 Rev. 0.92 4/6/2010 Current Limit The MP2004 includes two independent current limit structures which monitor and control each PMOS’s gate voltage limiting the guaranteed maximum output current to 200mA. Thermal Protection Thermal protection turns off the PMOS when the junction temperature exceeds +140ºC, allowing the IC to cool. When the IC’s junction temperature drops by 10ºC, the PMOS will be turned on again. Thermal protection limits total power dissipation in the MP2004. For reliable operation, junction temperature should be limited to 125 ºC maximum. Load-Transient Considerations The output response of load-transient consists of a DC shift and transient response. Because of the excellent load regulation of MP2004, the DC shift is very small. The output voltage transient depends on the output capacitor’s value and the ESR. Increasing the capacitance and decreasing the ESR will improve the transient response. Typical output voltage transient spike of MP2004 for a step change in the load current from 0mA to 80mA is tens mV. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 6 MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR APPLICATION INFORMATION 100 Power Dissipation The power dissipation for any package depends on the thermal resistance of the case and circuit board, the temperature difference between the junction and ambient air, and the rate of airflow. The power dissipation across the device can be represented by the equation: Unstable 10 1 Stable P = (VIN - VOUT) ×IOUT The allowable power dissipation can calculated using the following equation: P(MAX) = (TJunction - TAmbient) / θJA be Where (TJunction - TAmbient) is the temperature difference between the junction and the surrounding environment, θJA is the thermal resistance from the junction to the ambient environment. Connect the GND pin of MP2004 to ground using a large pad or ground plane helps to channel heat away. Input Capacitor Selection Using a capacitor whose value is >0.47µF on the MP2004 input and the amount of capacitance can be increased without limit. Larger values will help to improve line transient response with the drawback of increased size. Ceramic capacitors are preferred, but tantalum capacitors may also suffice. Output Capacitor Selection The MP2004 is designed specifically to work with very low ESR ceramic output capacitor in spacesaving and performance consideration. A ceramic capacitor in the range of 0.47µF and 10µF, and with ESR lower than 1.2Ω is suitable for the MP2004 application circuit. Output capacitor of larger values will help to improve load transient response and reduce noise with the drawback of increased size. 0.1 0 40 80 120 160 200 LOAD CURRENT (mA) Figure 2—Relationship between ESR and LDO Stability Reverse Current Path The PMOS used in the MP2004 has an inherent diode connected between input and output (see Figure3). If VOUT -VIN is more than a diode-drop, this diode gets forward biased and starts to conduct. To avoid misoperation, an external Schottky connected in parallel with the internal parasitic diode prevents it from being turned on by limiting the voltage drop across it to about 0.3V (see Figure 4). Figure 3—Inherent Diode Connected between Each Regulator Input and Output Figure 4—External Schottky Diode Connected in Parallel with the Internal Parasitic Diode MP2004 Rev. 0.92 4/6/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 7 MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR PCB Layout Guide PCB layout is very important to achieve good regulation, ripple rejection, transient response and thermal performance. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines and take Figure 5 for reference. 1) 2) 3) Input and output bypass ceramic capacitors are suggested to be put close to the IN Pin and OUT Pin respectively. Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. Connect IN, OUT and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. CIN R1 MP2004 R2 OUT1 OUT1 IN IN COUT1 OUT2 EN1 EN1 EN2 EN2 OUT2 COUT2 GND IN 5 EN1 4 1 OUT2 OUT1 6 EN2 2 GND 3 Top Layer Figure 5—PCB Layout MP2004 Rev. 0.92 4/6/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 8 MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR PACKAGE INFORMATION TSOT23-6 6 See Note 7 EXAMPLE TOP MARK 4 AAAA PIN 1 0.95 BSC 0.60 TYP 2.80 3.00 1 1.20 TYP 1.50 1.70 2.60 TYP 2.60 3.00 3 TOP VIEW RECOMMENDED LAND PATTERN 0.84 0.90 1.00 MAX 0.09 0.20 SEATING PLANE 0.30 0.50 0.95 BSC 0.00 0.10 SEE DETAIL "A" FRONT VIEW SIDE VIEW NOTE: GAUGE PLANE 0.25 BSC 0o-8o DETAIL “A” 0.30 0.50 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-193, VARIATION AB. 6) DRAWING IS NOT TO SCALE. 7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2004 Rev. 0.92 4/6/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 9