NSC CLC005AJE

CLC005
ITU-T G.703 Cable Driver with Adjustable Outputs
General Description
Key Specifications
National’s Comlinear CLC005 is a monolithic, high-speed
cable driver designed for the ITU-T G.703 serial digital data
transmission standard. The CLC005 drives 75Ω transmission lines (Belden 8281 or equivalent) at data rates from DC
to over 622 Mbps. Output signal waveforms produced by the
CLC005 comply with G.703 specifications. Controlled output
rise and fall times (650 ps typical) minimize transitioninduced jitter. The output voltage swing, typically 2.0V, set by
an accurate, low-drift internal bandgap reference, delivers a
1.0V swing to back-matched and terminated 75Ω cable. Output swing is adjustable from 0.7 Vp-p to 2.2 Vp-p using external resistors.
The CLC005’s class AB output stage consumes less power
than other designs, 185 mW with both outputs terminated,
and requires no external bias resistors. The differential inputs accept a wide range of digital signals from 200 mVp-p to
G.703 levels within the specified common-mode limits. All
this make the CLC005 an excellent general purpose high
speed driver for digital applications.
The CLC005 is powered from a single +5V or −5.2V supply
and comes in an 8-pin SOIC package.
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650 ps rise and fall times
Data rates to 622 Mbps
200 mV differential input
Low residual jitter (25 pspp )
Features
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No external pull-down resistors
Adjustable output amplitude
Differential input and output
Low power dissipation
Single +5V or −5.2V supply
Applications
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ITU-T G.703, Sonet/SDH, and ATM compatible driver
Digital routers and distribution amplifiers
Coaxial cable driver for digital transmission line
Twisted pair driver
Buffer applications
Typical Application
DS100144-2
© 1998 National Semiconductor Corporation
DS100144
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CLC005 ITU-T G.703 Cable Driver with Adjustable Outputs
August 1998
Typical Performance Characteristic
DS100144-1
Connection Diagram (8-Pin SOIC)
DS100144-3
Order Number CLC005AJE
See NS Package Number M08A
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2
Absolute Maximum Ratings (Note 1)
Package Thermal Resistance
θ JA Surface Mount AJE
θJC Surface Mount AJE
Reliability Information
Transistor count
MTTF
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Output Current
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering 10 seconds)
ESD Rating (Human Body Model)
6V
30 mA
+125˚C
−65˚C to +150˚C
Parameter
72
254 Mhr
Recommended Operating
Conditions
+300˚C
1000V
Electrical Characteristics
125˚C/W
105˚C/W
Supply Voltage Range (V
CC –VEE)
+4.5V to +5.5V
(VCC = 0V, VEE = −5V; unless otherwise specified).
Condition
Typ
+25˚C
Min/Max
+25˚C
Min/Max
0˚C to
+70˚C
Min/Max
-40˚C to
+85˚C
Units
37
-
-
-
mA
STATIC DC PERFORMANCE
Supply Current, Loaded
150Ω @ 270 Mbps
(Notes 5, 7)
Supply Current, Unloaded
(Note 3)
34
28/37
26/39
26/39
mA
Output HIGH Voltage (VOH )
(Note 3)
−1.7
−2.0/1.4
−2.0/1.4
−2.0/1.4
V
Output LOW Voltage (VOL )
(Note 3)
−3.7
−4.0/3.4
−4.0/3.4
−4.0/3.4
V
Input Bias Current
(Note 4)
10
30
50
50
µA
V
Output Swing
REXT = ∞ (Note 3)
2.0
1.86/2.14
1.86/2.14
1.86/2.14
Output Swing
REXT = 10 kΩ (Note 5)
1.30
-
-
-
V
Common Mode Input Range Upper Limit
−0.7
−0.8
−0.8
−0.8
V
Common Mode Input Range Lower Limit
−2.6
−2.5
−2.5
–2.5
V
Minimum Differential Input Swing (Note 5)
200
200
200
200
mV
Power Supply Rejection Ratio (Note 3)
26
20
20
20
dB
650
425/825
400/850
400/850
ps
AC PERFORMANCE
Output Rise and Fall Time
(Notes 3, 6, 7)
Overshoot
(Note 5)
5
%
Propagation Delay
(Note 5)
1.0
ns
Duty Cycle Distortion
(Note 5)
50
Residual Jitter
(Note 5)
25
Input Capacitance
(Note 5)
1.0
Output Resistance
(Note 5)
10
Ω
Output Inductance
(Note 5)
6
nH
ps
-
-
-
pspp
MISCELLANEOUS PERFORMANCE
pF
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: Spec is 100% tested at +25˚C, sample tested at +85˚C.
Note 4: Spec is 100% tested at +35˚C at wafer probe.
Note 5: Spec is guaranteed by design.
Note 6: Measured between the 20% and 80% levels of the waveform.
Note 7: Measured with both outputs driving 150Ω, AC coupled at 270 Mbps.
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Operation
INPUT INTERFACING
used to provide input termination and biasing. The input D.C.
common-mode voltage range is 0.8V to 2.5V below the positive power supply (VCC). Input signals plus bias should be
kept within the specified common-mode range. For an 800
mVP-P input signal, typical input bias levels range from 1.2V
to 2.1V below the positive supply.
The CLC005 has high impedance, emitter-follower buffered,
differential inputs. Single-ended signals may also be input.
Transmission lines supplying input signals must be properly
terminated close to the CLC005. Either A.C. or D.C. coupling
as in Figure 2 or Figure 3 may be used. Figures 2, 4 and Figure 5 show how Thevenin-equivalent resistor networks are
Resistor to VCC (R1)
Resistor to VEE (R2)
ECL, 50Ω, 5V, VT=2V
Load Type
82.5Ω
124Ω
ECL, 50Ω, 5.2V, VT=2V
80.6Ω
133Ω
ECL, 75Ω, 5V, VT=2V
124Ω
187Ω
ECL, 75Ω, 5.2V, VT=2V
121Ω
196Ω
800mVP-P, 50Ω, 5V, VT=1.6V
75.0Ω
154Ω
800mVP-P, 75Ω, 5V, VT=1.6V
110Ω
232Ω
800mVP-P, 2.2KΩ, 5V, VT=1.6V
3240Ω
6810Ω
DS100144-4
FIGURE 1. Input Stage
DS100144-5
FIGURE 2. AC Coupled Input
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4
Operation
(Continued)
DS100144-6
FIGURE 3. DC Coupled Input
OUTPUT INTERFACING
The CLC005’s class AB output stage, Figure 6, requires no
standing current in the output transistors and therefore requires no biasing or pull-down resistors. Advantages of this
arrangement are lower power dissipation and fewer external
components. The output may be either D.C. or A.C. coupled
to the load. A bandgap voltage reference sets output voltage
levels which are compatible with F100K and 10K ECL when
correctly terminated. The outputs do not have the same output voltage temperature coefficient as 10K. Therefore, noise
margins will be reduced over the full temperature range
when driving 10K ECL. Noise margins will not be affected
when interfacing to F100K since F100K is fully voltage and
temperature compensated.
DS100144-7
FIGURE 4. Single Ended 50Ω ECL Input
DS100144-8
FIGURE 5. Differential 50Ω ECL Input
DS100144-9
FIGURE 6. Output Stage
5
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Operation
(Continued)
DS100144-10
FIGURE 7. Differential Input DC Coupled Output
and low levels. It may be necessary to empirically select resistances used to set output levels when the D.C. loading on
the CLC005 differs appreciably from 150Ω.
OUTPUT AMPLITUDE ADJUSTMENT
The high and low output levels of the CLC005 are set by a
circuit shown simplified in Figure 8. Output high and low levels may be set independently with external resistor networks
connected between REXT-H (pin 3), REXT-L (pin 4) and the
power supplies. The resistor networks affect the high and
low output levels by changing the internally generated bias
voltages, VH and V L. The nominal high and low output levels
are VCC−1.7V and VCC−3.7V, respectively, when the pins
REXT-H and REXT-L are left unconnected. Though the internal
components which determine output voltage levels have accurate ratios, their absolute values may be controlled only
within about ± 15% of nominal. Even so, without external adjustment, output voltages are well controlled. A final design
should accommodate the variation in externally set output
voltages due to the CLC005’s part-to-part and external component tolerances.
Output voltage swing may be reduced with the circuit shown
in Figure 9. A single resistance chosen with the aid of the
graph, Figure 10, is connected between pins 3 and 4. Output
voltage swing may be increased with the circuit of Figure 11.
Figure 12 is used to estimate a value for resistor R. Note that
both of these circuits and the accompanying graphs assume
that the CLC005 is loaded with the standard 150Ω. Be aware
that output loading will affect the output swing and the high
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DS100144-11
FIGURE 8. Equivalent Bias Generation Circuit
6
Operation
(Continued)
DS100144-12
FIGURE 9. Differential Input Reduced Output
DS100144-13
FIGURE 10. Resistance Pins 3 to 4 vs Output Voltage
Reduced Output @ 150Ω Load
DS100144-14
FIGURE 11. Differential Input Increased Output
7
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Operation
(Continued)
DS100144-15
FIGURE 12. Resistance Pins 3 to 4 vs Output Voltage
Increased Output @ 150Ω Load
OUTPUT RISE AND FALL TIMES
Output load capacitance can significantly affect output rise
and fall times. The effect of load capacitance, stray or otherwise, may be reduced by placing the output back-match resistor close to the output pin and by minimizing all interconnecting trace lengths. Figure 13 shows the effect on risetime
of parallel load capacitance across a 150Ω load.
DS100144-16
FIGURE 13. Rise Time vs CL
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8
EVALUATION BOARD
A schematic, parts list and layout for a suitable evaluation
board are given on the following page. The artwork includes
trace, silk screen and ground layers. The individual printed
circuit board is available unassembled from National Semiconductor. To order this evaluation board, part number
CLC730056, contact your local sales representative or
the National Semiconductor Customer Response Center
in your area. (This evaluation board is identical to that for
the CLC007 for which some of the listed parts are not required.)
The evaluation board is a guide to proper circuit layout and
makes prototyping and measurement-taking easy. Since the
board is designed to accommodate many of the application
circuits possible with the CLC005, your particular application
may not require all of the listed parts or may require different
values. The evaluation board may be powered from standard
ECL supply voltages by installing the two jumpers in the locations labeled “−5”. For PECL supply voltages, install the
jumpers in the locations labeled “+5”.
PCB Layout Recommendations
Printed circuit board layout affects the performance of the
CLC005. The following guidelines will aid in achieving satisfactory device performance.
• Use a ground plane or power/ground plane sandwich design for optimum performance.
• Bypass device power with a 0.01 µF monolithic ceramic
capacitor in parallel with a 6.8 µF tantalum electrolytic capacitor located no more than 0.1″ (2.5 mm) from the device power pins.
• Provide short, symmetrical ground return paths for:
— inputs,
— supply bypass capacitors and
— the output load.
• Provide short, grounded guard traces located
— under the centerline of the package,
— 0.1″ (2.5 mm) from the package pins
— on both top and bottom of the board with connecting
vias.
DS100144-17
CLC005 Evaluation Board Schematic
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PCB Layout Recommendations
Item
(Continued)
Reference Designator
Part Description
Qty
1
C1, C2, C8, C9
0.1 µF SMD Capacitor, Size 1206
4
2
C5, C60
33 pF SMD Capacitor, Size 1206
2
3
C7, C10, C13, C14
0.01 µF SMD Tantalum Capacitor, Size 12062
4
4
C11, C12
6.8 µF SMD Tantalum Capacitor, Size 6032
2
5
J1, J2
BNC PC Amphenol #31-5329-52RFX
2
6
J3, J4
BNC PC Amphenol #31-5329-72RFX
2
7
R3, R1
124Ω SMD Resistor, Size 1206
2
8
R4, R5
82.5Ω SMD Resistor, Size 1206
2
9
R6,R7
75Ω SMD Resistor, Size 1206
2
10
R11
2.4 kΩ SMD Resistor, Size 1206
1
11
R12
3 kΩ SMD Resistor, Size 1206
1
12
U1
CLC005AJE Cable Driver
1
13
+5, −5
Jumper
4
14
VR1
10 kΩ Potentiometer, Bourns 3299
1
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PCB Layout Recommendations
(Continued)
DS100144-18
DS100144-19
DS100144-20
DS100144-21
11
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CLC005 ITU-T G.703 Cable Driver with Adjustable Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number CLC005AJE
NS Package Number M08A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into
sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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