TI LM96530

LM96530
LM96530 Ultrasound Transmit/Receive Switch
Literature Number: SNAS499E
LM96530
Ultrasound Transmit/Receive Switch
General Description
Features
The LM96530 is an eight-channel monolithic high-voltage,
high-speed T/R (Transmit/Receive) switch for multi-channel
medical ultrasound applications. It is well-suited for use with
National’s LM965XX series chipset which offers a complete
medical ultrasound solution targeted towards low-power,
portable systems.
The LM96530 contains eight high-voltage T/R switches with
integrated clamping diodes. This chip protects the inputs of
the receive channel's LNA (Low Noise Amplifier) from the
high-voltage pulses of the transmit channel. Advanced features include a diode bridge with internal current sources that
are programmable via an external resistor. Low-power operation is enabled via per-channel-selectable switching.
National Semiconductor also offers a development package
for sale which includes a driver hardware and software package with a graphical user interface for configuration and monitoring.
■ 8-channel high-voltage receive side switches without
Applications
■
■
■
■
■
■
■
■
■
charge-injection
Can be used for receive protection and/or receive
multiplexing with SPI™ compatible bus control
Channel bandwidth supports 1MHz to 20MHz transducers
Input accepts pulses and continuous-wave signals within
±60V
Integrated output clamping diodes limit output to ±0.7V
Low harmonic distortion HD2 at -75dBc at 5MHz
Continuous-wave operation
Soft-switcher based on a diode bridge architecture
yielding better noise performance and faster turn-on and off times than competing T-gate switch architectures
2.5V to 3.3V CMOS SPI™ compatible logic interface with
daisy chain capability
Bias current source (IS) can be scaled between 0 and 8mA
via an external resistor
Key Specifications
■ Ultrasound Imaging
Input voltage
Output voltage
clamp ( IS= 1mA)
On-resistance
Off-isolation @
5MHz
Noise spectral
density @ 5MHz
Harmonic
distortion
HD2
HD3
Channel crosstalk
@ 5MHz
Operating Temp.
© 2011 National Semiconductor Corporation
301220
±60
V
±0.7
V
18
Ω
-58
dB
0.5
nV/√Hz
-75
-75
dB
dB
-73
dB
0 to +70
°C
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LM96530 Ultrasound Transmit/Receive Switch
September 19, 2011
LM96530
Block Diagram
30122002
Typical Application
8-Channel Transmit/Receive Chipset
30122007
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2
LM96530
Pin Diagram
30122001
FIGURE 1. Pin Diagram of LM96530
Ordering Information
Part Number
Package Type
NSC Package Drawing
LM96530SQ
LM96530SQE
Supplied As
1000
60 Lead LLP
SQA60A
LM96530SQX
250
2000
3
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LM96530
TABLE 1. Pin Descriptions
Pin No.
Name
Type
Function and Connection
1, 3, 5, 7, 9, 11, 13,
15
INn
n=0,...,7
Input
High-voltage input
45, 43, 41, 39, 37,
35, 33, 31
OUTn
n=0,...
Output
Low-voltage output
External resistor to AGND. Used to set internal current sources.
RREF = 6.25 kΩ → IS = 8mA;
25
RREF
Output
RREF = 12.5 kΩ → IS = 4mA;
RREF = 25 kΩ → IS = 2mA;
RREF = 50 kΩ → IS = 1mA
59
SW_OFF
Input
1 = Switch all channels OFF
0 = Use SPI™ to control switch
60
SPI_EN
Input
1 = Enable the SPI™ Interface
0 = Disable the SPI™ Interface and presets SPI™ registers for all
switches ON.
58
57
SCSI
SCKI
Input
SPI™ chip select input,
0 = Chip Select
Input
SPI™ compatible clock input
SPI™ compatible data input
56
SDI
Input
53
SDO
Output
SPI™ compatible data buffered output
52
SCKO
Output
SPI™ compatible clock buffered output
51
SCSO
Output
SPI™ chip select buffered output
26, 27, 49, 50
VDD
Power
Positive analog supply voltage (+5V)
28, 29, 47, 48
VSS
Power
Negative analog supply voltage (-5V)
54
VLL
Power
Logic voltage supply (+2.5 to 3.3V)
VSUB
Power
Negative high voltage supply (-65V)
HVGND
Ground
High voltage reference potential (0V)
AGND
Ground
Analog and logic low voltage reference input, logic ground (0V)
0, 17
2, 4, 6, 8, 10, 12,
14, 16, 55
All others
SPI™ is a trademark of Motorola, Inc.
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4
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Supply Voltage (VDD)
Supply Voltage (VSS)
Supply Voltage (VSUB)
IO Supply Voltage (VLL)
−70V to 70V
−0.3V to VLL
+0.3v
Operating Ratings
+150°C
−40°C to +125°C
+0.3V to +5.5V
+0.3V and −5.5V
−70V (Must
always be most
negative voltage)
−0.3V to +3.6V
Operation Junction Temperature
VDD, −VSS, Analog Supply
VLL, Logic Supply
High Voltage Analog Inputs
VSUB, Substrate bias supply
0°C to + 70°C
+4.7V to 5.3V
+2.4V to 3.5V
−60V to +60V,
VSUB must be most
negative supply
−50V to −65V
Package Thermal Resistance (θJA)
ESD Tolerance
Human Body Model
Machine Model
Charge Device Model
20°C/W
2kV
150V
750V
Analog Characteristics
Unless otherwise stated, the following conditions apply.
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 50 kΩ, RT = 50Ω, fIN = 5 MHz, SW_OFF = SPI_EN = 0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
VIN
High Voltage Analog Inputs
VSUB must be most negative voltage.
See (Note 2)
-60
en
Voltage Noise
at 5MHz
BW
HD2
HD3
Third harmonic distortion
XTALK
Channel crosstalk
TON
Turn-on time
TOFF
Turn-off time
Iso_off
Off isolation
RON
On resistance of TR switch
IL
Insertion Loss
VCLAMP
IMISMATCH
Max
Units
+60
V
0.8
nV/√Hz
-3dB Bandwidth
150
MHz
Second harmonic distortion
-60
dBc
-65
dBc
-69
dB
2
µs
0.2
µs
-55
dB
0.1VPP 5MHz tone applied as input
0.1Vpp 5MHz tone is applied as input
125
Ω
-5.5
dB
Output clamped voltage
±0.7
V
Current source mis-match
0.03
0.2
mA
14
20
mA
fIN = 5MHz
VDD & VSS
VLL
Typ
Power Supply Current
VSUB
5
5
µA
0.45
mA
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LM96530
Voltage at High Voltage Analog Inputs
Voltage at Logic Inputs (SCLKI, SDI
SCSI, SW_OFF)
Absolute Maximum Ratings (Note 1)
LM96530
Unless otherwise stated, the following conditions apply
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 25 kΩ, RT = 50Ω, fIN = 5MHz, SW_OFF = SPI_EN = 0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
VIN
High Voltage Analog Inputs
VSUB must be most negative voltage.
See (Note 2)
-60
en
Voltage Noise
at 5MHz
BW
-3dB Bandwidth
HD2
Second harmonic distortion
HD3
Third harmonic distortion
XTALK
Channel crosstalk
TON
TOFF
Iso_off
Off isolation
RON
On resistance of TR switch
IL
Insertion Loss
VCLAMP
Output clamped voltage
IMISMATCH
Current source mis-match
Max
Units
+60
V
0.7
nV/√Hz
150
MHz
-67
dBc
-70
dBc
-73
dB
Turn-on time
2
µs
Turn-off time
0.2
µs
-58
dB
48
Ω
-4
dB
±0.75
V
0.1VPP 5MHz tone applied as input
0.1Vpp 5MHz tone is applied as input
fIN = 5MHz
VDD & VSS
VLL
Typ
Power Supply Current
VSUB
0.1
0.35
mA
23
30
mA
5
µA
1
mA
Unless otherwise stated, the following conditions apply
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 12.5 kΩ, RT = 50Ω, fIN = 5MHz, SW_OFF = SPI_EN = 0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
VIN
High Voltage Analog Inputs
VSUB must be most negative voltage.
See (Note 2)
-60
en
Voltage Noise
at 5MHz
BW
HD2
HD3
Third harmonic distortion
XTALK
Channel crosstalk
TON
Turn-on time
TOFF
Turn-off time
Iso_off
Off isolation
RON
On resistance of TR switch
IL
Insertion Loss
VCLAMP
IMISMATCH
Units
+60
V
nV/√Hz
-3dB Bandwidth
180
MHz
Second harmonic distortion
-73
dBc
-75
dBc
-73
dB
2
µs
0.1VPP 5MHz tone applied as input
0.1Vpp 5MHz tone is applied as input
0.2
µs
-58
dB
27
Ω
-3
dB
Output clamped voltage
±0.78
V
Current source mis-match
0.25
0.6
mA
40
49
mA
fIN = 5MHz
Power Supply Current
VSUB
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Max
0.55
VDD & VSS
VLL
Typ
6
5
µA
2.2
mA
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 6.25 kΩ, RT = 50Ω, fIN = 5MHz, SW_OFF = SPI_EN = 0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
VIN
High Voltage Analog Inputs
VSUB must be most negative voltage.
See (Note 2)
-60
en
Voltage Noise
at 5MHz
BW
-3dB Bandwidth
HD2
Second harmonic distortion
HD3
Third harmonic distortion
XTALK
Channel crosstalk
TON
TOFF
Iso_off
Off isolation
RON
On resistance of TR switch
IL
Insertion Loss
VCLAMP
Output clamped voltage
IMISMATCH
Max
Units
+60
V
Current source mis-match
0.6
1.2
mA
75
86
mA
0.5
nV/√Hz
180
MHz
-75
dBc
-75
dBc
-73
dB
Turn-on time
2
µs
Turn-off time
0.2
µs
-58
dB
18
Ω
-2.5
dB
±0.8
V
0.1VPP 5MHz tone applied to input
0.1Vpp 5MHz tone is applied as input
fIN = 5MHz
VDD & VSS
VLL
Typ
Power Supply Current
VSUB
7
5
µA
5
mA
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LM96530
Unless otherwise stated, the following conditions apply
LM96530
Digital Characteristics
Unless otherwise stated, the following conditions apply.
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 50 kΩ, RT = 50Ω, SW_OFF = 0V, SPI_EN = 2.5V, TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Logical Input “HI” Voltage
VIL
Logical Input “LO” Voltage
IIN-H/L
Logic Input Current
-1
VOH
Logical Output “HI” Voltage
2.2
VOL
Logical Output “LO” Voltage
tSSELS
SPI™ SCSI Setup Time
11
ns
tSSELH
SPI™ SCSI Hold Time
11
ns
tSSELHI
SPI™ SCSI HI Time
tWS
SPI™ SDI Setup Time
11
ns
tWH
SPI™ SDI Hold Time
11
ns
tOD
SPI™ SCLKI to SDO
Propagation Delay
tVALID
SPI™ SCSI to T/R Switch
State Change Delay
tSCLK
SPI™ SCLKI Period
SPI™ SCLKI Duty Cycle
2
Unit
VIH
V
0.2
0.5
V
+1
µA
V
0.3
250
CL = 5 pF
ns
25
30
See (Note 5)
V
ns
ns
100
ns
45
% of CLK
Period
55
tSCLKOD-H
SPI™ SCLKI-HI to SCLKOHI Propagation Delay
12
tSCLKOD-L
SPI™ SCLKI-LO to SCLKOLO Propagation Delay
12
tSCSOD-H
SPI™ SCSI-HI to SCSO-HI
Propagation Delay
12
tSCSOD-L
SPI™ SCLSI-LO to SCLSOLO Propagation Delay
12
Maximum Number of DaisySCLKI Freq. = 10MHz
Chained devices
ns
ns
ns
ns
16
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics.
Note 2: Total input signal levels, including any transient voltage overshoots, must be within this maximum voltage range.
Note 3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 4: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: Guarantee by design
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8
LM96530
SPI™ Timing
30122005
FIGURE 2. SPI™ Timing Diagram
9
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VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 50 kΩ, RT = 50Ω, fIN = 5 MHz, TA = 25°C.
Input Referred Noise vs Rref
2nd Harmonic Distortion vs Rref
-55
0.80
-60
0.70
HD2 (dBc)
en (nV/√Hz)
0.75
0.65
0.60
0.56
-65
-70
-75
0.50
0.45
-80
0
10
20
30
RREF (K Ω)
40
50
0
10
20
30
RREF (KΩ)
40
30122009
Crosstalk vs frequency
Isolation vs Frequency
-20
-30
I solation (dBc)
-40
-50
-60
-70
-40
-50
-60
-70
-80
1M
-80
10M
F requency (Hz)
100M
1M
10M
F requency (Hz)
100M
30122011
30122012
Turn On Respone
Turn Off Response
30122016
30122015
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50
30122010
-30
X talk (dBc)
LM96530
Typical Performance Characteristics
10
The LM96530 RX switch provides an 8-channel receive side
interface solution for medical ultrasound applications suitable
for integration into multi-channel (128 / 256 channel) systems.
30122002
FIGURE 3. Block Diagram of T/R Channel
A functional block diagram of the IC is shown in . Each RX
switch channel on the IC has a high-voltage input that can be
directly connected to a transducer driven by a high-voltage
pulser, such as the LM96550. The input feeds into a diode
bridge with its output being diode-clamped to ± 0.7V. The
diode bridge bias current is set to 1 mA with Rref = 50KΩ.
Therefore, the output can be directly connected to a low noise
amplifier (LNA) stage which must be protected from the highvoltage signals on the transducer.
The bias current of the bridge is determined by two equallysized current sources with their current value ranging between 0 and 8mA depending on the external resistor Rref at
the input of the bandgap reference block. While the bias current is the same value for all channels on the IC, each channel
can be switched on and off individually with an 8–bit shift register that is programmed via a SPI™ compatible bus.
The on-chip analog circuitry requires dual 5V supplies VDD
and VSS, a single logic supply VLL, and a high voltage negative bias, VSUB.
SERIAL INTERFACE OPERATION
The digital interface is comprised of an 8-bit shift register and
a latch. Each bit controls one T/R switch channel, where the
MSB bit, i.e., the first bit written (D7) controls channel 7, and
the LSB bit (D0) controls channel 0. The three input pins, SDI,
SCSI and SCKl, are all Schmitt Trigger inputs with 0.5V typical
hysteresis. The output pins SDO, SCSO, and SCLKO are
SPI™ compatible. The serial data input SDI is synchronously
read into the shift register on the rising edge of the clock SCKI.
When SCSI changes from low to high, the data in the shift
register is transferred to the latch circuit, and output on the
parallel data signals P0 through P7 which drive the switched
bias current sources for channels n=0,…, 7, respectively.
When SCSI changes from high to low, the latch output Pn,
and thus the biasing condition, does not change.
11
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LM96530
Its diode-bridge-based architecture allows high-speed lowdistortion channel designs targeting low-power, portable systems. A complete system can be designed using National’s
companion LM965XX chipset.
Functional Description
LM96530
ICs. For example, if 3 LM96530 ICs are daisy-chained, one
can picture a 24–bit shift register. Thus, the MSB or first bit
written on the SDI line (D23) will control channel 7 of the last
LM96530, i.e., the IC that is daisy-chained the farthest away
from the SPI master. The LSB or last bit written on the SDI
line (D0) will control channel 0 of the first LM96530, i.e., the
IC that is closest to the SPI master. It is important to note that
If only one particular channel of an IC in the daisy-chain requires updating, all of the ICs, i.e., the entire shift register,
must be written to.
DAISY CHAINING MULTIPLE LM96530 ICs
For connecting multiple T/R switch ICs, the LM965XX SPI™compatible bus can be daisy-chained up to 16 ICs at 10MHz
SCLKI for easy PCB routing. The inputs SDI, SCSI and SCLKI
are daisy-chained together with SDO, SCSO and SCLKO.
Therefore, the next IC’s SDI is connected to the previous IC’s
SDO. Similarly, the next IC’s SCSI is connected to the previous IC’s SCSO, and the next IC’s SCLKI is connected to the
previous IC’s SCLKO, as shown in . Daisy-chaining multiple
LM96530 devices amounts to one large shift register with the
number of bits being equal to 8 times the number of LM96530
30122006
FIGURE 4. 16 LM96530 Devices Daisy Chained @ SCLKI = 16MHz
BASIC OPERATION WITHOUT SERIAL INTERFACE
COMMUNICATION
To disable the SPI™ compatible interface, connect the pin
SPI_EN to AGND. To reverse bias all 8 channels of the T/R
switch, connect the pin, SW_OFF to VLL. To forward bias all
8 channels of the T/R switch, connect the pin, SW_OFF to
AGND.
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POWER-UP AND POWER-DOWN SEQUENCES
VSUB needs to always be the most negative supply – equal
to or more negative than VSS or the most negative transmit
pulse at all times. The power sequence should be to applied to VSUB first, followed by the remaining supplies in
any order.
12
LM96530
Physical Dimensions inches (millimeters) unless otherwise noted
60-Lead LLP Package
NS Package Number SQA60A
13
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LM96530 Ultrasound Transmit/Receive Switch
Notes
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Applications
Audio
www.ti.com/audio
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Amplifiers
amplifier.ti.com
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www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
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Medical
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Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and Automotive www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
www.ti.com/video
e2e.ti.com
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