WOLFSON WM8524

WM8524
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24-bit 192kHz Stereo DAC with 2Vrms
Ground Referenced Line Output
DESCRIPTION
FEATURES
The WM8524 is a stereo DAC with integral charge pump
and hardware control interface. This provides 2Vrms line
driver outputs using a single 3.3V power supply rail.

The device features ground-referenced outputs and the use
of a DC servo to eliminate the need for line driving coupling
capacitors and effectively eliminate power on pops and
clicks.
The device is controlled and configured via a hardware
control interface.
The device supports all common audio sampling rates
between 8kHz and 192kHz using all common MCLK fs
rates. The audio interface operates in slave mode.
The WM8524 has a 3.3V tolerant digital interface, allowing
logic up to 3.3V to be connected.
The device is available in a 16-pin TSSOP.










High performance stereo DAC with ground referenced line
driver
Audio Performance

106dB SNR (‘A-weighted’)

-89dB THD @ -1dBFS
120dB mute attenuation
All common sample rates from 8kHz to 192kHz supported
Hardware control mode
2
Data formats: LJ, RJ, I S
Maximum 1mV DC offset on Line Outputs
Pop/Click suppressed Power Up/Down Sequencer
AVDD and LINEVDD +3.3V ±10% allowing single supply
16-lead TSSOP package
Operating temperature range: -40°C to 85°C
APPLICATIONS

Consumer digital audio applications requiring 2Vrms output

Games Consoles

Set Top Box

A/V Receivers

DVD Players

Digital TV
BLOCK DIAGRAM
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Production Data, October 2011, Rev 4.1
Copyright 2011 Wolfson Microelectronics plc
WM8524
Production Data
TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 TERMINOLOGY .............................................................................................................. 6 POWER CONSUMPTION MEASUREMENTS ................................................................ 7 SIGNAL TIMING REQUIREMENTS ...................................................................... 8 SYSTEM CLOCK TIMING ............................................................................................... 8 AUDIO INTERFACE TIMING – SLAVE MODE ............................................................... 9 POWER ON RESET CIRCUIT ...................................................................................... 10 DEVICE DESCRIPTION ...................................................................................... 12 INTRODUCTION ........................................................................................................... 12 DIGITAL AUDIO INTERFACE ....................................................................................... 12 DIGITAL AUDIO DATA SAMPLING RATES ................................................................. 14 HARDWARE CONTROL INTERFACE .......................................................................... 15 POWER UP AND DOWN CONTROL ............................................................................ 16 POWER DOMAINS ....................................................................................................... 17 DIGITAL FILTER CHARACTERISTICS .............................................................. 18 DAC FILTER RESPONSES .......................................................................................... 19 APPLICATIONS INFORMATION ........................................................................ 20 RECOMMENDED EXTERNAL COMPONENTS ........................................................... 20 RECOMMENDED ANALOGUE LOW PASS FILTER .................................................... 21 RECOMMENDED PCB LAYOUT .................................................................................. 21 RELEVANT APPLICATION NOTES .............................................................................. 22 PACKAGE DIMENSIONS .................................................................................... 23 IMPORTANT NOTICE ......................................................................................... 24 ADDRESS ..................................................................................................................... 24 w
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PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
WM8524CGEDT
−40°C to +85°C
16 lead TSSOP
MSL1
260 C
WM8524CGEDT/R
−40°C to +85°C
16-lead TSSOP
MSL1
260 C
o
(Pb-free)
o
(Pb-free, tape and reel)
Note:
Reel quantity = 2000
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PIN DESCRIPTION
PIN NO
NAME
TYPE
1
LINEVOUTL
Analogue Out
Left line output
2
CPVOUTN
Analogue Out
Charge Pump negative rail decoupling pin
3
CPCB
Analogue Out
Charge Pump fly back capacitor pin
4
LINEGND
Supply
5
CPCA
Analogue Out
6
LINEVDD
Supply
7
DACDAT
Digital In
Digital audio interface data input
8
LRCLK
Digital In
Digital audio interface left/right clock
9
BCLK
Digital In
Digital audio interface bit clock
10
MCLK
Digital In
Master clock
11
MUTE
¯¯¯¯¯
Digital In
12
AIFMODE
Digital In
Tri-level
DESCRIPTION
Charge Pump ground
Charge Pump fly back capacitor pin
Charge Pump supply
0 = Mute enabled
1 = Mute disabled
0 = 24-bit Left Justified
2
1 = 24-bit I S
Z = 24-bit Right Justified
13
AGND
Supply
Analogue ground
14
VMID
Analogue Out
15
AVDD
Supply
Analogue supply
16
LINEVOUTR
Analogue Out
Right line output
Analogue midrail decoupling pin
Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling
and storage of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
AVDD, LINEVDD
Voltage range digital inputs
Voltage range analogue inputs
MAX
-0.3V
+4.5V
LINEGND -0.3V
LINEVDD +0.3V
AGND -0.3V
AVDD +0.3V
Temperature range, TA
-40°C
+125°C
Storage temperature after soldering
-65°C
+150°C
Notes:
1.
Analogue grounds must always be within 0.3V of each other.
2.
LINEVDD and AVDD must always be within 0.3V of each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Analogue supply range
AVDD, LINEVDD
Ground
AGND, LINEGND
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.97
3.3
3.63
V
0
V
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ELECTRICAL CHARACTERISTICS
Test Conditions
°
LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, TA=+25 C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0dBFS
1.89
2.1
2.31
Vrms
Analogue Output Levels
Output Level
Load Impedance
1
Load Capacitance
kΩ
No external RC filter
300
pF
With filter shown in
Figure 16
1
µF
DAC Performance
Signal to Noise Ratio
SNR
RL = 10kΩ
106
dB
104
dB
104
dB
A-weighted
RL = 10kΩ
Un-weighted
Dynamic Range
DNR
RL = 10kΩ
A-weighted
Total Harmonic Distortion
AVDD + LINEVDD
THD
PSRR
Power Supply Rejection Ratio
Channel Separation
-1dBFS
-89
dB
0dBFS
-86
dB
100Hz
54
dB
1kHz
54
dB
20kHz
50
dB
1kHz
100
dB
20Hz to 20kHz
95
0
degrees
System Absolute Phase
Channel Level Matching
Mute Attenuation
DC Offset at LINEVOUTL and
LINEVOUTR
-1
dB
0.1
dB
-120
dB
0
1
mV
Digital Logic Levels
Input HIGH Level
VIH
Input LOW Level
VIL
0.7
LINEVDD
Input Capacitance
Input Leakage
V
0.3
LINEVDD
V
0.9
A
10
-0.9
pF
TERMINOLOGY
1.
Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale
output signal and the output with no input signal applied.
2.
Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative to
the amplitude of the measured output signal.
3.
All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to
use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The
low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
4.
Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with
mute applied.
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POWER CONSUMPTION MEASUREMENTS
Test Conditions
LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, TA=+25°C, Slave Mode, quiescent (no signal)
TEST CONDITIONS
Off
IAVDD
ILINEVDD
TOTAL
(mA)
(mA)
(mA)
No clocks applied
0.8
1.1
1.9
Standby
MUTE
¯¯¯¯¯ = 0
0.2
2.2
2.4
Playback
MUTE
¯¯¯¯¯ = 1
4.8
6.0
10.8
Standby
MUTE
¯¯¯¯¯ = 0
0.2
2.9
3.1
Playback
MUTE
¯¯¯¯¯ = 1
5.5
8.5
14.0
Standby
MUTE
¯¯¯¯¯ = 0
0.2
2.9
3.1
Playback
MUTE
¯¯¯¯¯ = 1
5.5
8.5
14.0
fs=48kHz, MCLK=256fs
fs=96kHz, MCLK=256fs
fs=192kHz, MCLK=128fs
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
MCLK cycle time
tMCLKY
27
MCLK high time
tMCLKH
11
500
ns
ns
MCLK low time
tMCLKL
11
ns
Master Clock Timing Information
MCLK duty cycle (tMCLKH/tMCLKL)
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40:60
60:40
%
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AUDIO INTERFACE TIMING – SLAVE MODE
tBCY
BCLK
(input)
LRCLK
(input)
VIH
VIL
tBCH
tBCL
VIH
VIL
tLRH
tLRSU
DACDAT
(input)
VIH
VIL
tDS
tDH
Figure 2 Digital Audio Data Timing – Slave Mode
Test Conditions
°
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25 C, Slave Mode
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
BCLK cycle time
tBCY
27
BCLK pulse width high
tBCH
11
ns
BCLK pulse width low
tBCL
11
ns
LRCLK set-up time to BCLK rising edge
tLRSU
7
ns
LRCLK hold time from BCLK rising edge
tLRH
5
ns
DACDAT hold time from LRCLK rising edge
tDH
5
ns
DACDAT set-up time to BCLK rising edge
tDS
7
ns
Audio Data Input Timing Information
ns
Table 1 Slave Mode Audio Interface Timing
Note:
BCLK period should always be greater than or equal to MCLK period.
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POWER ON RESET CIRCUIT
Figure 3 Internal Power on Reset Circuit Schematic
The WM8524 includes an internal Power-On-Reset circuit, as shown in Figure 3, which is used to
reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD
and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a
minimum threshold.
Figure 4 Typical Power Timing Requirements
Figure 4 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD
goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee POR is
asserted low and the chip is held in reset. In this condition, all writes to the control interface are
ignored. After VMID rises to Vpord_hi and AVDD rises to Vpora_hi, POR is released high and all registers
are in their default state and writes to the control interface may take place.
On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum
threshold Vpora_low.
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Test Conditions
o
LINEVDD = AVDD = 3.3V AGND = LINEGND = 0V, TA = +25 C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
VDD level to POR defined
(LINEVDD/AVDD rising)
Vpora
Measured from LINEGND
VDD level to POR rising edge
(VMID rising)
Vpord_hi
Measured from LINEGND
0.63
0.8
1
V
VDD level to POR rising edge
(LINEVDD/AVDD rising)
Vpora_hi
Measured from LINEGND
1.44
1.8
2.18
V
VDD level to POR falling edge
(LINEVDD/AVDD falling)
Vpora_lo
Measured from LINEGND
0.96
1.46
1.97
V
158
mV
Table 2 Power on Reset
Note: All values are simulated results
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DEVICE DESCRIPTION
INTRODUCTION
The WM8524 provides high fidelity, 2Vrms ground referenced stereo line output from a single supply
line with minimal external components. The integrated DC servo eliminates the requirement for
external mute circuitry by minimising DC transients at the output during power up/down. The device
is well-suited to both stereo and multi-channel systems.
The device supports all common audio sampling rates between 8kHz and 192kHz using common
MCLK fs rates, with a slave mode audio interface.
The WM8524 supports a simple hardware control mode, allowing access to 24-bit LJ, RJ and I2S
audio interface formats, as well as a mute control. An internal audio interface clock monitor
automatically mutes the DAC output if the BCLK is interrupted.
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting audio data to the WM8524. The digital audio interface
uses three pins:

DACDAT: DAC data input

LRCLK: Left/Right data alignment clock

BCLK: Bit clock, for synchronisation
The WM8524 digital audio interface operates as a slave as shown in Figure 5.
Figure 5 Slave Mode
INTERFACE FORMATS
The WM8524 supports three different audio data formats:

Left justified

Right justified

IS
2
All three of these modes are MSB first. They are described in Audio Data Formats on page 13. Refer
to the “Electrical Characteristics” section for timing information.
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AUDIO DATA FORMATS
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 6 Right Justified Audio Interface (24-bit word length)
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 7 Left Justified Audio Interface (assuming n-bit word length)
2
In I S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
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Figure 8 I S Justified Audio Interface (assuming n-bit word length)
DIGITAL AUDIO DATA SAMPLING RATES
The external master clock is applied directly to the MCLK input pin. In a system where there are a
number of possible sources for the reference clock, it is recommended that the clock source with the
lowest jitter be used for the master clock to optimise the performance of the WM8524.
The WM8524 has a detection circuit that automatically determines the relationship between the
master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system clock periods.
The MCLK must be synchronised with the LRCLK, although the device is tolerant of phase variations
or jitter on the MCLK.
If during sample rate change the ratio between MCLK and LRCLK varies more than once within 1026
LRCLK periods, then it is recommended that the device be taken into the standby state or the off
state before the sample rate change and held in standby until the sample rate change is complete.
This will ensure correct operation of the detection circuit on the return to the enabled state. For details
on the standby state, please refer to the Power up and down control section of the datasheet on page
16.
The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz.
Table 3 shows typical master clock frequencies and sampling rates supported by the WM8524 DAC.
MASTER CLOCK FREQUENCY (MHz)
Sampling Rate
LRCLK
128fs
192fs
256fs
384fs
512fs
768fs
8kHz
Unavailable
Unavailable
2.048
3.072
4.096
6.144
1152fs
9.216
32kHz
Unavailable
Unavailable
8.192
12.288
16.384
24.576
36.864
Unavailable
44.1kHz
Unavailable
Unavailable
11.2896
16.9344
22.5792
33.8688
48kHz
Unavailable
Unavailable
12.288
18.432
24.576
36.864
Unavailable
88.2kHz
11.2896
16.9344
22.5792
33.8688
Unavailable
Unavailable
Unavailable
Unavailable
96kHz
12.288
18.432
24.576
36.864
Unavailable
Unavailable
176.4kHz
22.5792
33.8688
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
192kHz
24.576
36.864
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
Table 3 MCLK Frequencies and Audio Sample Rates
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HARDWARE CONTROL INTERFACE
The device is configured according to logic levels applied to the hardware control pins as described in
Table 4.
PIN NAME
MUTE
¯¯¯¯¯
PIN
NUMBER
11
DESCRIPTION
Mute Control
0 = Mute
1 = Normal operation
AIFMODE
12
Audio Interface Mode
0 = 24-bit LJ
2
1 = 24-bit I S
Z = 24-bit RJ
Table 4 Hardware Control Pin Configuration
MUTE
The MUTE
¯¯¯¯¯ pin controls the DAC mute to both left and right channels. When the mute is asserted a
softmute is applied to ramp the signal down in 800 samples. When the mute is de-asserted the signal
returns to full scale in one step.
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POWER UP AND DOWN CONTROL
The MCLK, BCLK and MUTE
¯¯¯¯¯ pins are monitored to control how the device powers up or down, and
this is summarised in Figure 9 below.
MCLK
Disabled
Off
MCLK Enabled
BCLK Enabled
MUTE=0
Standby
MCLK
Disabled
MCLK Enabled
BCLK Enabled
MUTE=1
BCLK
Disabled
BCLK Enabled
MUTE=1
MUTE=0
Enabled
Figure 9 Hardware Power Sequence Diagram
Off to Enable
To power up the device to enabled, start MCLK and BCLK and set MUTE
¯¯¯¯¯ = 1.
Off to Standby
To power up the device to standby, start MCLK and BCLK and set MUTE
¯¯¯¯¯ = 0. Once the
device is in standby mode, BCLK can be disabled and the device will remain in standby
mode.
Standby to Enable
To transition from the standby state to the enabled state, set the MUTE
¯¯¯¯¯ pin to logic 1 and start BCLK.
Enable to Standby
To power down to a standby state leaving the charge pump running, either set the MUTE
¯¯¯¯¯ pin to logic
0 or stop BCLK. MCLK must continue to run in these situations. The device will automatically mute
and power down quietly in either case.
Note: It is recommended that the device is placed in standby mode before sample rate change if the sample rate changes more than
once in 1026 LRCLK periods, as detailed in Digital Audio Data Sampling Rates on page 14.
Enable to Off
To power down the device completely, stop MCLK at any time. It is recommended that the device is
placed into standby mode as described above before stopping MCLK to allow a quiet shutdown.
For the timing of the off state to enabled state transition (power on to audio out timing), and the
enabled state to standby state transition (the shutdown timing), please refer to WTN0302.
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POWER DOMAINS
Supply Rail
2.97V … 3.63V
AVDD
LINEVDD
Device
DAC L/R
DC Servo
Charge
Pump
Line Driver
AGND
Digital
Input Pins
LDO
Digital
Core
POR
LINEGND
Ground Rail
Figure 10 Power Domain Diagram
POWER DOMAIN
NAME
BLOCKS USING
THIS DOMAIN
DOMAIN DESCRIPTION
DAC Power Supplies
3.3V ± 10%
AVDD
Line Driver
Analogue Supply
DAC
DC Servo
3.3V ± 10%
LINEVDD
Charge Pump
Digital LDO
Analogue Supply
Digital Pad buffers
Internally Generated Power Supplies and References
1.65V ± 10%
VMID
DAC, LDO
Ext decoupled resistor string
-3.3V ± 10%
CPVOUTN
Line Driver
Charge pump generated voltage
Table 5 Power Domains
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DIGITAL FILTER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC Filter – 256fs to 1152fs
Passband
 0.1dB
0.454fs
Passband Ripple
0.1
Stopband
Stopband attenuation
dB
0.546fs
f > 0.546fs
-50
Group Delay
dB
10
Fs
DAC Filter – 128fs and 192fs
Passband
 0.1dB
0.247fs
Passband Ripple
0.1
Stopband
Stopband attenuation
Group Delay
dB
0.753fs
f > 0.753fs
-50
dB
10
Fs
TERMINOLOGY
1.
Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2.
Pass-band Ripple – any variation of the frequency response in the pass-band region
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DAC FILTER RESPONSES
0.2
0
0.15
0.1
Response (dB)
Response (dB)
-20
-40
-60
0.05
0
-0.05
-0.1
-80
-0.15
-100
-0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
-120
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Figure 11 DAC Digital Filter Frequency Response
– 256fs to 1152fs Clock Modes
Figure 12 DAC Digital Filter Ripple – 256fs to 1152fs Clock
Modes
0.2
0
0
Response (dB)
Response (dB)
-20
-40
-60
-0.2
-0.4
-0.6
-0.8
-80
-1
0
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
1
Frequency (Fs)
Figure 13 DAC Digital Filter Frequency Response
– 128fs and 192fs Clock Modes
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Figure 14 DAC Digital Filter Ripple – 128fs to 192fs Clock
Modes
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 15 Recommended External Components
Notes:
1.
Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to
optimize split ground configuration for audio performance.
2.
Charge Pump fly-back capacitor C5 should be placed as close to WM8524 as possible, followed by Charge Pump
decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. See Recommended PCB Layout on p21.
3.
Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum
performance.
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RECOMMENDED ANALOGUE LOW PASS FILTER
Figure 16 Recommended Analogue Low Pass Filter (one channel shown)
An external single-pole RC filter is recommended if the device is driving a wideband amplifier. Other
filter architectures may provide equally good results.
The filter shown in Figure 16 has a -3dB cut-off at 105.26kHz and a droop of 0.15dB at 20kHz. The
typical output from the WM8524 is 2.1Vrms – when a 10kΩ load is placed at the output of this
recommended filter the amplitude across this load is 1.99Vrms.
RECOMMENDED PCB LAYOUT
To LINEVDD
Supply
Top Layer Copper
Via
C2
C1
CPVOUTN
LINEGND
CPCB
CPCA
LINEVDD
C5
AVDD
VMID
AGND
WM8524
C4
C3
To AVDD
Supply
Figure 17 Recommended PCB Layout
Notes:
1.
C5 should be placed as close to WM8524 as possible, with minimal track lengths to reduce inductance and maximise
performance of the charge pump. Vias should be avoided in the tracking to C5.
2.
C1 is then next most important and should also be placed as close as possible to the WM8524. Again, minimise track
lengths and avoid vias to reduce parasitic inductance.
3.
C2 and C4 are then next most important, and lastly C3.
4.
The WM8524 evaluation board, details available at www.wolfsonmicro.com, shows an example of good component
placement and layout to maximise performance with a minimal BOM.
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WM8524
Production Data
RELEVANT APPLICATION NOTES
The following application notes, available from www.wolfsonmicro.com, may provide additional
guidance for use of the WM8524.
DEVICE PERFORMANCE:
WTN0302 – WM8524 Recommended Power Sequence and Timing
WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs
WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies
GENERAL:
WAN0108 – Moisture Sensitivity Classification and Plastic IC Packaging
WAN0109 – ESD Damage in Integrated Circuits: Causes and Prevention
WAN0158 – Lead-Free Solder Profiles for Lead-Free Components
WAN0161 – Electronic End-Product Design for ESD
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WM8524
Production Data
PACKAGE DIMENSIONS
DT: 16 PIN TSSOP (5.0 x 4.4 x 1.0 mm)
b
DM013.B
e
16
9
E1
E
GAUGE
PLANE
1

8
D
0.25
c
A A2
L
A1
-C0.1 C
Symbols
A
A1
A2
b
c
D
e
E
E1
L

MIN
----0.05
0.80
0.19
0.09
4.90
4.30
0.45
o
0
REF:
SEATING PLANE
Dimensions
(mm)
NOM
--------1.00
--------5.00
0.65 BSC
6.4 BSC
4.40
0.60
-----
MAX
1.20
0.15
1.05
0.30
0.20
5.10
4.50
0.75
o
8
JEDEC.95, MO-153
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8524
Production Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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WM8524
Production Data
REVISION HISTORY
DATE
REV
ORIGINATOR
CHANGES
25/10/11
4.1
JMacD
Order codes changed from WM8524GEDT and WM8524GEDT/R to
WM8524CGEDT and WM8524CGEDT/R to reflect change to copper wire
bonding.
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