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WM8758B
Stereo CODEC with Headphone Driver and Line Out
DESCRIPTION
FEATURES
The WM8758B is a low power, high quality stereo CODEC
designed for portable applications such as MP3 audio player.
Stereo CODEC:
DAC SNR 100dB, THD -86dB (‘A’ weighted @ 48kHz)
ADC SNR 92.5dB, THD -75dB (‘A’ weighted @ 48kHz)
Headphone Driver
40mW per channel output power into 16 / 3.3V AVDD2
Line output
Mic Preamps:
Stereo Differential or mono microphone Interfaces
Programmable preamp gain
Psuedo differential inputs with common mode rejection
Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for electret microphones
Other Features:
Enhanced 3-D function for improved stereo separation
Digital playback limiter
5-band Equaliser (record or playback)
Programmable ADC High Pass Filter (wind noise reduction)
Programmable ADC Notch Filter
PLL supporting various clocks between 8MHz-50MHz
Sample rates supported (kHz): 8, 11.025, 12, 16, 22.05, 24,
32, 44.1, 48
Low power, low voltage
2.5V to 3.6V analogue supplies
1.71V to 3.6V digital supplies
5x5mm 32-lead QFN package
The device integrates preamps for stereo differential mics, and
drivers for headphone and differential or stereo line output.
External component requirements are reduced as no separate
microphone or headphone amplifiers are required. Headphone
and line common feedback improves crosstalk and noise
performance.
Advanced on-chip digital signal processing includes a 5-band
equaliser, a mixed signal Automatic Level Control for the
microphone or line input through the ADC as well as a purely
digital limiter function for record or playback. Additional digital
filtering options are available in the ADC path, to cater for
application filtering such as ‘wind noise reduction’ and notch
filter.
The WM8758B digital audio interface can operate in master or
slave mode with an integrated PLL.
The WM8758B operates at analogue supply voltages from 2.5V
to 3.3V, although the digital supply voltages can operate at
voltages down to 1.71V to save power. Additional power
management control enables individual sections of the chip to
be powered down under software control.
APPLICATIONS
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Portable audio player
Production Data, January 2012, Rev 4.4
Copyright 2012 Wolfson Microelectronics plc
WM8758B
Production Data
TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1
BLOCK DIAGRAM ................................................................................................ 1
FEATURES ............................................................................................................ 1
APPLICATIONS..................................................................................................... 1
TABLE OF CONTENTS ......................................................................................... 2
PIN CONFIGURATION .......................................................................................... 4
ORDERING INFORMATION .................................................................................. 4
PIN DESCRIPTION ................................................................................................ 5
RECOMMENDED OPERATING CONDITIONS ..................................................... 6
ELECTRICAL CHARACTERISTICS ..................................................................... 7
TERMINOLOGY ............................................................................................................ 12
HEADPHONE OUTPUT PERFORMANCE .......................................................... 13
POWER CONSUMPTION .................................................................................... 14
AUDIO PATHS OVERVIEW ................................................................................ 15
SIGNAL TIMING REQUIREMENTS .................................................................... 16
SYSTEM CLOCK TIMING ............................................................................................. 16
AUDIO INTERFACE TIMING – MASTER MODE .......................................................... 16
AUDIO INTERFACE TIMING – SLAVE MODE ............................................................. 17
CONTROL INTERFACE TIMING – 3-WIRE MODE ...................................................... 18
CONTROL INTERFACE TIMING – 2-WIRE MODE ...................................................... 19
INTERNAL POWER ON RESET CIRCUIT .......................................................... 20
RECOMMENDED POWER UP/DOWN SEQUENCE .................................................... 22
DEVICE DESCRIPTION ...................................................................................... 25
INTRODUCTION ........................................................................................................... 25
INPUT SIGNAL PATH ................................................................................................... 26
ANALOGUE TO DIGITAL CONVERTER (ADC) ........................................................... 33
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)............................................ 37
OUTPUT SIGNAL PATH ............................................................................................... 42
3D STEREO ENHANCEMENT ...................................................................................... 49
ANALOGUE OUTPUTS ................................................................................................. 49
DIGITAL AUDIO INTERFACES ..................................................................................... 61
AUDIO SAMPLE RATES ............................................................................................... 68
MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ................................................ 68
GENERAL PURPOSE INPUT/OUTPUT........................................................................ 70
OUTPUT SWITCHING (JACK DETECT)....................................................................... 72
CONTROL INTERFACE ................................................................................................ 73
RESETTING THE CHIP ................................................................................................ 74
POWER SUPPLIES....................................................................................................... 75
POWER MANAGEMENT .............................................................................................. 75
POP MINIMISATION ..................................................................................................... 77
REGISTER MAP .................................................................................................. 78
DIGITAL FILTER CHARACTERISTICS .............................................................. 80
TERMINOLOGY ............................................................................................................ 80
DAC FILTER RESPONSES .......................................................................................... 81
ADC FILTER RESPONSES .......................................................................................... 81
HIGHPASS FILTER ....................................................................................................... 82
5-BAND EQUALISER .................................................................................................... 83
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WM8758B
APPLICATIONS INFORMATION ........................................................................ 87
RECOMMENDED EXTERNAL COMPONENTS ........................................................... 87
PACKAGE DIAGRAM ......................................................................................... 88
IMPORTANT NOTICE ......................................................................................... 89
ADDRESS: .................................................................................................................... 89
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PIN CONFIGURATION
32
31
30
29
28
27
26
25
LIP
1
24
AGND2
LIN
2
23
ROUT2
L2/GPIO2
3
22
OUT3
RIP
4
21
OUT4
TOP VIEW
RIN
5
20
LINE_COM
R2/GPIO3
6
19
HP_COM
LRC
7
18
MODE
BCLK
8
17
SDIN
9
10
11
12
13
14
15
16
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
WM8758CBGEFL/V
-40C to +85C
32-lead QFN (5 x 5 mm)
(Pb-free)
MSL3
260 C
WM8758CBGEFL/RV
-40C to +85C
32-lead QFN (5 x 5 mm)
(Pb-free, tape and reel)
MSL3
260 C
o
o
Note:
Reel quantity = 3,500
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PIN DESCRIPTION
PIN
NAME
TYPE
1
LIP
Analogue Input
Left MIC pre-amp positive input
DESCRIPTION
2
LIN
Analogue Input
Left MIC pre-amp negative input
3
L2/GPIO2
Analogue Input
Left channel line input/secondary mic pre-amp positive input/GPIO2 pin
4
RIP
Analogue Input
Right MIC pre-amp positive input
5
RIN
Analogue Input
Right MIC pre-amp negative input
6
R2/GPIO3
Analogue Input
Right channel line input/secondary mic pre-amp positive input/GPIO3 pin
7
LRC
Digital Input / Output
8
BCLK
Digital Input / Output
9
ADCDAT
Digital Output
10
DACDAT
Digital Input
DAC digital audio data input
11
MCLK
Digital Input
Master clock input
12
DGND
Supply
13
DCVDD
Supply
Digital core logic supply
14
DBVDD
Supply
Digital buffer (I/O) supply
15
CSB/GPIO1
Digital Input / Output
16
SCLK
Digital Input
17
SDIN
Digital Input / Output
18
MODE
Digital Input
19
HP_COM
Analogue Input
20
LINE_COM
Analogue Input
21
OUT4
Analogue Output
Right line output / mono mix output
22
OUT3
Analogue Output
Left line output / mono mix output
23
ROUT2
Analogue Output
24
AGND2
Supply
25
LOUT2
Analogue Output
26
AVDD2
Supply
27
VMID
Reference
28
AGND1
Supply
29
ROUT1
Analogue Output
Line or headphone output right 1
30
LOUT1
Analogue Output
Line or headphone output left 1
31
AVDD1
Supply
32
MICBIAS
Analogue Output
DAC and ADC sample rate clock
Digital audio bit clock
ADC digital audio data output
Digital ground
3-Wire control interface chip select / GPIO1 pin
3-Wire control interface clock input / 2-wire control interface clock input
3-Wire control interface data input / 2-Wire control interface data input
Control interface selection
Headphone ground common feedback input
Line out ground common feedback input
Line output right 2
Analogue ground (return path for ROUT2/LOUT2)
Line output left 2
Analogue supply (supply for output amplifiers ROUT2/LOUT2)
Decoupling for ADC and DAC reference voltage
Analogue ground (return path for all input amplifiers, PLL, ADC and
DAC, internal bias circuits, output amplifiers LOUT1, ROUT1 and
OUT3/OUT4 on AVDD1 AGND1)
Analogue supply (feeds all input amplifiers, PLL, ADC and DAC, internal
bias circuits, output amplifiers LOUT1, ROUT1))
Microphone bias
Note:
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
DBVDD, DCVDD, AVDD1, AVDD2 supply voltages
MIN
MAX
-0.3V
+3.63V
Voltage range digital inputs
DGND -0.3V
DVDD +0.3V
Voltage range analogue inputs
AGND1 -0.3V
AVDD1 +0.3V
Storage temperature prior to soldering
30C max / 85% RH max
Storage temperature after soldering
-65C
+150C
Notes
1.
Analogue and digital grounds must always be within 0.3V of each other.
2.
All digital and analogue supplies are internally independent (i.e. not connected).
3.
Analogue supply voltages should not be less than digital supply voltages.
4.
DBVDD must be greater than or equal to DCVDD.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Digital supply range (Core)
DCVDD
1.8
3.6
V
Digital supply range (Buffer)
DBVDD
1.71
3.3
3.6
V
AVDD1, AVDD2
2.5
1
3.3
3.6
Analogue supply range
Ground
TEST
CONDITIONS
DGND, AGND1, AGND2
MIN
1.71
1,2
TYP
0
MAX
UNIT
V
V
Notes
1.
Analogue supply voltages must not be less than digital supply voltages.
2.
DBVDD must be greater than or equal to DCVDD.
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ELECTRICAL CHARACTERISTICS
Test Conditions
o
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2)
Full-scale Input Signal Level –
Single-ended input via LIN/RIN
VINFS
Full-scale Input Signal Level –
Pseudo-differential input
VINFS
Mic PGA equivalent input noise
PGABOOST = 0dB
AVDD1/3.3
Vrms
Vrms
INPPGAVOL = 0dB
PGABOOST = 0dB
AVDD1*0.7/
INPPGAVOL = 0dB
3.3
At 35.25dB
gain
0 to 20kHz
150
Input resistance (LIN, RIN)
RMICIN
Gain set to 35.25dB
1.6
k
Input resistance (LIN, RIN)
RMICIN
Gain set to 0dB
46
k
Input resistance (LIN, RIN)
RMICIN
Gain set to -12dB
71
k
Input resistance (LIP, RIP)
RMICIP
90
k
Input resistance (L2, R2)
RL2R2
L/RIP2INPPGA = 1,
L/R2_2BOOSTVOL = 000
90
k
Input resistance (L2, R2)
RL2R2
L/RIP2INPPGA = 0, Gain set
to 6dB
11
k
Input resistance (L2, R2)
RL2R2
L/RIP2INPPGA = 0,
22
k
60
k
uV
Gain set to 0dB
Input resistance (L2, R2)
RL2R2
L/RIP2INPPGA = 0,
Gain set to -12dB
Input Capacitance
CMICIN
10
pF
Maximum Programmable Gain
+35.25
dB
Minimum Programmable Gain
-12
dB
Guaranteed monotonic
0.75
dB
INPPGAMUTEL/R=1
100
dB
PGABOOSTL/R=0
0
dB
PGABOOSTL/R=1
20
dB
Gain adjusted by
L2_2BOOSTVOL
R2_2BOOSTVOL
+6
dB
Gain adjusted by
-12
dB
Programmable Gain Step Size
MIC Mute Attenuation
MIC Gain Boost
L2, R2 Line Input Programmable Gain
Maximum Gain from L/R2 input
to boost/mixer
Minimum Gain from L/R2 input
to boost/mixer
L2/R2 boost step size
L2_2BOOSTVOL
R2_2BOOSTVOL
Guaranteed monotonic
3
dB
100
dB
Maximum Gain
+6
dB
Minimum Gain
-12
dB
3
dB
100
dB
L2/R2 Mute attenuation
OUT4 to Left or Right Input Boost Record Path
Gain step size
Guaranteed monotonic
Mute attenuation
Automatic Level Control (ALC)
Target Record Level
-22.5
-1.5
Programmable gain
-12
35.25
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Test Conditions
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DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue to Digital Converter (ADC) - Input from LIN/P and RIN/P, PGA and boost gains=0dB
Signal to Noise Ratio (Note 5,6)
SNR
A-weighted
92.5
dB
91.5
dB
90
dB
90
dB
-75
dB
-75
dB
-72
dB
-72
dB
100
dB
92.5
dB
92.5
dB
90
dB
90
dB
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 20kHz
AVDD1=AVDD2=3.0V
22Hz to 20kHz
AVDD1=AVDD2=2.5V
Total Harmonic Distortion
THD
(Note 7)
-12dBFS Input
AVDD1=AVDD2=3.0V
-12dBFS Input
AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise
THD+N
(Note 7)
-12dBFS Input
AVDD1=AVDD2=3.0V
-12dBFS Input
AVDD1=AVDD2=2.5V
Channel Separation (Note 8)
1kHz full scale input signal
Analogue to Digital Converter (ADC) - Input from L2, R2
Signal to Noise Ratio (Note 5,6)
SNR
A-weighted
85
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 20kHz
AVDD1=AVDD2=3.0V
22Hz to 20kHz
AVDD1=AVDD2=2.5V
Total Harmonic Distortion
THD
(Note 7)
-3dBFS Input
-83
-75
dB
AVDD1=AVDD2=3.0V
-3dBFS Input
-66
dB
AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise
(Note 7)
THD+N
-3dBFS Input
-81
-70
dB
AVDD1=AVDD2=3.0V
-3dBFS Input
-65
dB
100
dB
AVDD1=AVDD2=2.5V
Channel Separation (Note 8)
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1kHz input signal
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Production Data
Test Conditions
o
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC to L/R Mix to Line-Out (LOUT1/ROUT1 with 10k / 50pF load, analogue volume controls set to 0dB)
Full-scale output
Signal to Noise Ratio (Note 5,6)
SNR
PGA gains set to 0dB
AVDD1/3.3
Vrms
A-weighted
100
dB
96
dB
95.5
dB
93.5
dB
-86
dB
-86
dB
-84
dB
-84
dB
1kHz signal
100
dB
10mV, 20kHz noise on
HPCOM, HPCOM enabled
40
dB
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 20kHz
AVDD1=AVDD2=3.0V
22Hz to 20kHz
AVDD1=AVDD2=2.5V
Total Harmonic Distortion
THD
(Note 7)
full-scale signal
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise
THD+N
(Note 7)
full-scale signal
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
Channel Separation (Note 8)
Ground noise rejection
DAC to L/R Mix to Line-Out (LOUT2/ROUT2 with 10k / 50pF load, analogue volume controls set to 0dB)
Full-scale output
Signal to Noise Ratio (Note 5,6)
PGA gains set to 0dB
SNR
A-weighted
95
AVDD1/3.3
Vrms
100
dB
96
dB
95.5
dB
93.5
dB
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 20kHz
AVDD1=AVDD2=3.0V
22Hz to 20kHz
AVDD1=AVDD2=2.5V
Total Harmonic Distortion
THD
(Note 7)
full-scale signal
-87
-80
dB
AVDD1=AVDD2=3.0V
full-scale signal
-82
dB
AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise
(Note 7)
THD+N
full-scale signal
-85
-75
dB
AVDD1=AVDD2=3.0V
full-scale signal
-80
dB
1kHz signal
100
dB
10mV, 20kHz noise on
LCOM, LCOM enabled
40
dB
AVDD1=AVDD2=2.5V
Channel Separation (Note 8)
Ground noise rejection
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Test Conditions
o
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC to L/R Mix to Headphone (LOUT1/ROUT1, analogue volume controls set to 0dB)
Full-scale output
PGA gains set to 0dB
AVDD1/3.3
Vrms
A-weighted
100
dB
22Hz to 20kHz
95.5
dB
Po = 20mW
-75
dB
-79
dB
-75
dB
-79
dB
1kHz signal
100
dB
10mV, 20kHz noise on
HPCOM, HPCOM enabled
40
dB
AVDD1/3.3
Vrms
97
dB
22Hz to 20kHz
95.5
dB
Po = 20mW
-79
dB
-82
dB
1kHz signal
100
dB
10mV, 20kHz noise on
LCOM, LCOM enabled
40
dB
Maximum PGA gain into mixer
+6
dB
Minimum PGA gain into mixer
-15
dB
Signal to Noise Ratio (Note 5,6)
Total Harmonic Distortion
SNR
THD
(Note 7)
RL=16Ω
Po = 20mW
RL=32Ω
Total Harmonic Distortion + Noise
THD+N
Po = 20mW
(Note 7)
RL=16Ω
Po = 20mW
RL=32Ω
Channel Separation (Note 8)
Ground noise rejection
DAC to L/R Mix to Headphone (LOUT2/ROUT2, analogue volume controls set to 0dB)
Full-scale output
Signal to Noise Ratio (Note 5,6)
Total Harmonic Distortion
PGA gains set to 0dB
SNR
A-weighted
THD
(Note 7)
90
RL=16Ω
Po = 20mW
RL=32Ω
Channel Separation (Note 8)
Ground noise rejection
Bypass Paths to Output Mixers
PGA gain step into mixer
Guaranteed monotonic
3
dB
100
dB
Maximum Programmable Gain
+6
dB
Minimum Programmable Gain
-57
dB
Mute attenuation
Analogue Outputs (LOUT1, ROUT1, LOUT2, ROUT2)
Programmable Gain step size
Guaranteed monotonic
1
dB
Mute attenuation
1kHz, full scale signal
85
dB
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Test Conditions
o
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MIC PGA to Input Boost to OUT3/OUT4 outputs (with 10k / 50pF load)
Full-scale output voltage, 0dB
gain (Note 9)
Signal to Noise Ratio (Note 5,6)
SNR
A-weighted
90
AVDD2/3.3
Vrms
98
dB
96
dB
95.5
dB
93.5
dB
-84
dB
-82
dB
-82
dB
-80
dB
100
dB
AVDD1/3.3
Vrms
100
dB
96
dB
95.5
dB
93.5
dB
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 22kHz
AVDD1=AVDD2=3.0V
22Hz to 22kHz
AVDD1=AVDD2=2.5V
Total Harmonic Distortion
THD
(Note 7)
full-scale signal
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise
THD+N
(Note 7)
full-scale signal
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
Channel Separation
MIC PGA Bypass to LOUT1/ROUT1 (with 16 load)
Full-scale output voltage, 0dB
gain (Note 9)
Signal to Noise Ratio (Note 5,6)
SNR
A-weighted
90
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 22kHz
AVDD1=AVDD2=3.0V
22Hz to 22kHz
AVDD1=AVDD2=2.5V
Total Harmonic Distortion
THD
(Note 7)
-5dBFS signal
-87
-75
dB
AVDD1=AVDD2=3.0V
-5dBFS signal
-69
dB
AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise
(Note 7)
THD+N
-5dBFS signal
-85
-73
dB
AVDD1=AVDD2=3.0V
-5dBFS signal
-68
dB
100
dB
AVDD1=AVDD2=2.5V
Channel separation
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1kHz full scale signal
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Test Conditions
o
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Bias
Bias Voltage
VMICBIAS
MBVSEL=0
0.9*AVDD1
V
MBVSEL=1
0.65*AVDD1
V
Bias Current Source
IMICBIAS
for VMICBIAS within +/-3%
Output Noise Voltage
Vn
1kHz to 20kHz
3
15
mA
nV/Hz
Digital Input / Output
Input HIGH Level
VIH
Input LOW Level
VIL
0.7DBV
DD
V
0.3
V
DBVDD
Output HIGH Level
VOH
IOL=1mA
Output LOW Level
VOL
IOH-1mA
0.9DBV
DD
V
0.1x
V
DBVDD
TERMINOLOGY
1.
2.
Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
3.
Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
4.
THD (dB) – THD is a ratio of the rms value of the first seven harmonics compared to the rms value of the fundamental.
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WM8758B
HEADPHONE OUTPUT PERFORMANCE
SNR Graphs TBA:
SNR vs AVDD1=AVDD2 L/ROUT1 (DAC path) for 16, 32
SNR vs AVDD1=AVDD2 L/ROUT2 (DAC path) for 16, 32
THD+N Graphs TBA:
THD+N vs output power (Analogue in to L/ROUT1) 16, 32
Plots for AVDD1=AVDD2=2.7, 3.0, 3.3, 3.6V
THD+N vs output power (Analogue in to L/ROUT2) 16, 32
Plots for AVDD1=AVDD2=2.7, 3.0, 3.3, 3.6V
PSRR Graphs TBA:
AVDD1 PSRR vs Frequency (DAC to L/ROUT1), 16
AVDD1 PSRR vs Frequency (DAC to L/ROUT2), 16
AVDD2 PSRR vs Frequency (DAC to L/ROUT2), 16
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POWER CONSUMPTION
TYPICAL SCENARIOS
Estimated current consumption for typical scenarios are shown below.
All measurements are made with quiescent signal.
R1=009, R2=180, R3=06F, R4=050, R6=000,
R32=001, R33=001
L/ROUT2
Clocks on
None
R1=009, R3=06F, R4=050, R11=024, R17=004,
R6=000, R32=001, R33=001
OUT3/OUT4 Stereo line out
Clocks on
None
R1=1FF, R3=1EF, R4=050, R6=000, R38=001,
R39=001
ADC Stereo Record (psuedo MIC)
Clocks on
N/A
R1=OCD, R2=1BF, R4=050, R6=000, R2C=033,
R2D=110, R2F=000, R2E=110, R30=000
ADC Stereo Record (line in)
Clocks on
N/A
R1=0CD, R2=1BF, R4=050, R6=000, R2F=050,
R30=050
L/ROUT1 Master mode
Master mode / MCLK=13MHz
None
R1=029, R2=180, R3=00F, R4=050, R6=149,
R32=001, R33=001, R24=007,R25=023, R26=1EA,
R27=126
BYPASS to OUT3/OUT4
No clocks
None
R1= 009, R49 = 006
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R1=0CD, R2=03C, R3=180, R2F=050, R38=004,
R30=050, R39=004
Total Power
(mW)
None
AVDD2 (mA)
Clocks on
AVDD2 (V)
L/ROUT1
AVDD1 (mA)
None
AVDD1 (V)
No clocks
DBVDD (mA)
Standby
DBVDD (V)
All default
DCVDD (mA)
None
DCVDD (V)
No clocks
register
settings (Hex
values)
Clocking
Scheme
(Unless
otherwise
specified)
Slave Mode
MCLK =
12.288Mhz
LRC = 48kHz
BCLK =
3.048MHz
Ω
OFF
Load
Control
Register
Operational
Mode
Power delivered to the load is not included.
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
0.001
0
0
0.001
0
0
6.8
4.8
3.2
6.8
4.8
3.2
6.88
4.82
3.2
7.3
5.1
3.45
7.5
5.2
3.55
3.06
2.18
3.7
0.001
0
0
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
0
0
0
0
0
0
0.008
0.005
0.003
0.008
0.005
0.003
0.008
0.005
0.003
0.04
0.03
0.02
0.04
0.03
0.02
7.9
3.5
1.6
0.001
0
0
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
0.01
0.008
0.008
0.145
0.115
0.115
5.8
4.3
4.3
5.1
3.8
3.8
5.1
3.8
3.8
8.1
6.5
6.5
7.6
6.05
6.05
7.1
5.24
5.24
2.15
1.54
1.54
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
3.3
2.5
2.5
0
0
0
0
0
0
0.7
0.5
0.5
0.7
0.5
0.5
0.7
0.5
0.5
0
0
0
0
0
0
0
0
0
0
0
0
0.036
0.020
0.020
0.482
0.288
0.288
43.916
24.013
17.765
41.606
22.763
16.515
41.870
22.813
16.515
50.952
29.075
22.496
49.962
28.200
21.551
59.598
27.300
22.640
7.102
3.850
3.850
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WM8758B
AUDIO PATHS OVERVIEW
Figure 1 Audio Paths Overview
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 2 System Clock Timing Requirements
Test Conditions
o
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, TA = +25 C, Slave Mode
PARAMETER
SYMBOL
CONDITIONS
MIN
TMCLKY
MCLK=SYSCLK (=256fs)
TYP
MAX
UNIT
System Clock Timing Information
MCLK cycle time
MCLK duty cycle
MCLK input to PLL
TMCLKDS
Note 1
81.38
ns
20
ns
60:40
40:60
Note:
1. PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
AUDIO INTERFACE TIMING – MASTER MODE
Figure 3 Digital Audio Data Timing – Master Mode (see Control Interface)
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Test Conditions
o
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, TA=+25 C, Master Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRC propagation delay from BCLK falling edge
tDL
10
ns
ADCDAT propagation delay from BCLK falling edge
tDDA
10
ns
DACDAT setup time to BCLK rising edge
tDST
10
ns
DACDAT hold time from BCLK rising edge
tDHT
10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 4 Digital Audio Data Timing – Slave Mode
Test Conditions
o
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, TA=+25 C, Slave Mode, fs=48kHz,
MCLK= 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
BCLK cycle time
tBCY
50
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
LRC set-up time to BCLK rising edge
tLRSU
10
ns
LRC hold time from BCLK rising edge
tLRH
10
ns
DACDAT hold time from BCLK rising edge
tDH
10
ADCDAT propagation delay from BCLK falling edge
tDD
Audio Data Input Timing Information
ns
ns
10
ns
Note:
BCLK period should always be greater than or equal to MCLK period.
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CONTROL INTERFACE TIMING – 3-WIRE MODE
3-wire mode is selected by connecting the MODE pin high.
Figure 5 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
o
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND = AGND1 = AGND2 = 0V, TA=+25 C, Slave Mode, fs=48kHz,
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
80
ns
SCLK pulse cycle time
tSCY
200
ns
SCLK pulse width low
tSCL
80
ns
SCLK pulse width high
tSCH
80
ns
SDIN to SCLK set-up time
tDSU
40
ns
SCLK to SDIN hold time
tDHO
40
ns
CSB pulse width low
tCSL
40
ns
CSB pulse width high
tCSH
40
ns
CSB rising to SCLK rising
tCSS
40
tps
0
Pulse width of spikes that will be suppressed
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ns
5
ns
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CONTROL INTERFACE TIMING – 2-WIRE MODE
2-wire mode is selected by connecting the MODE pin low.
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t1
t9
t7
Figure 6 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
o
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, TA=+25 C, Slave Mode, fs=48kHz,
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
SCLK Low Pulse-Width
t1
1.3
526
kHz
us
SCLK High Pulse-Width
t2
600
ns
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
SDIN, SCLK Rise Time
t6
300
ns
SDIN, SCLK Fall Time
t7
300
ns
Setup Time (Stop Condition)
t8
Data Hold Time
t9
Pulse width of spikes that will be suppressed
tps
Program Register Input Information
SCLK Frequency
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0
ns
600
0
ns
900
ns
5
ns
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INTERNAL POWER ON RESET CIRCUIT
Figure 7 Internal Power on Reset Circuit Schematic
The WM8758B includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1 and
monitors DCVDD. It asserts PORB low if AVDD1 or DCVDD is below a minimum threshold.
Figure 8 Typical Power up Sequence where AVDD1 is Powered before DCVDD
Figure 8 shows a typical power-up sequence where AVDD1 comes up first. When AVDD1 goes
above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is
asserted low and the chip is held in reset. In this condition, all writes to the control interface are
ignored. Now AVDD1 is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high
and all registers are in their default state and writes to the control interface may take place.
On power down, where AVDD1 falls first, PORB is asserted low whenever AVDD1 drops below the
minimum threshold Vpora_off.
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Figure 9 Typical Power up Sequence where DCVDD is Powered before AVDD1
Figure 9 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that
DCVDD is already up to specified operating voltage. When AVDD1 goes above the minimum
threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the
chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD1
rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the
control interface may take place.
On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the
minimum threshold Vpord_off.
SYMBOL
MIN
TYP
MAX
UNIT
Vpora
0.4
0.6
0.8
V
Vpora_on
0.9
1.2
1.6
V
Vpora_off
0.4
0.6
0.8
V
Vpord_on
0.5
0.7
0.9
V
Vpord_off
0.4
0.6
0.8
V
Table 1 Typical POR Operation (typical values, not tested)
Notes:
If AVDD1 and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating level
but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal operation
when the voltage is back to the recommended level again.
The chip will enter reset at power down when AVDD1 or DCVDD falls below Vpora_off or Vpord_off. This
may be important if the supply is turned on and off frequently by a power management system.
The minimum tpor period is maintained even if DCVDD and AVDD1 have zero rise time. This
specification is guaranteed by design rather than test.
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RECOMMENDED POWER UP/DOWN SEQUENCE
In order to minimise output pop and click noise, it is recommended that the WM8758B device is
powered up and down under control using the following sequences:
Power Up:
1.
Turn on external power supplies. Wait for supply voltage to settle.
2.
Set low bias mode, BIASCUT = 1.
3.
Enable HPCOM = 1, LINECOM = 1.
4.
Mute all Outputs and set PGAs to minimum gain, R52 to R57 = 0x140h.
5.
Enable L/ROUT1
6.
Enable L/ROUT2
7.
Enable VMID independent current bias, POBCTRL = 1.
8.
Enable required DACs and mixers.
9.
Enable VMIDSEL=01, BIASEN = 1 and BUFIOEN = 1
10. Setup digital interface, input amplifiers, PLL, ADCs and DACs for desired operation.
11. Wait 100ms to allow VMID to rise sufficiently before unmuting outputs
12. Unmute L/ROUT1 and set desired volume, e.g. for 0dB R52 and R53 = 0x139h.
13. Unmute L/ROUT2 and set desired volume, e.g. for 0dB R54 and R55 = 0x139h.
14. Disable VMID independent current bias, POBCTRL = 0.
Power Down:
1.
Disable Thermal shutdown
2.
Enable VMIDTOG = 1
3.
Disable VMIDSEL=00 and BUFIOEN=0
4.
Wait for VMID to discharge
5.
Power off registers R1, R2, R3 = 0x000h
6.
Remove external power supplies
Notes:
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1.
Charging time constant is determined by impedance selected by VMIDSEL and the value of
decoupling capacitor connected to VMID pin.
2.
It is possible to interrupt the power down sequence and power up to VMID before the allocated
VMID discharge time.
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Figure 10 ADC Power Up and Down Sequence (not to scale)
SYMBOL
MIN
TYPICAL
MAX
UNIT
tmidrail_on
300
tmidrail_off
>6
ms
s
tadcint
2/fs
n/fs
ADC Group Delay
29/fs
n/fs
Table 2 Typical POR Operation (typical values, not tested)
Notes:
w
1.
The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This
time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance
and AVDD power supply rise time.
2.
The analogue input pin discharge time, tmidrail_off, is determined by the analogue input coupling
capacitor discharge time. The time, tmidrail_off, is measured using a 1μF capacitor on the analogue
input but will vary dependent upon the value of input coupling capacitor.
3.
While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system
noise but no significant digital output will be present.
4.
The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for
normal ADC operation.
5.
ADCDAT data output delay from power up - with power supplies starting from 0V - is determined
primarily by the VMID charge time. ADC initialisation and power management bits may be set
immediately after POR is released; VMID charge time will be significantly longer and will dictate
when the device is stabilised for analogue input.
6.
ADCDAT data output delay at power up from device standby (power supplies already applied) is
determined by ADC initialisation time, 2/fs.
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Vpor_on
Vpora
Power Supply
Vpor_off
DGND
POR
Device Ready
No Power
POR Undefined
Internal POR active
tpor
DNC
I2S Clocks
DNC
tdacint
DAC Internal State
Power down
Init
tdacint
Normal Operation
PD
Init
Normal Operation
tline_midrail_on
tline_midrail_off
(Note 1)
Line Out Outputs
Power down
(Note 3)
AVDD/2
(Note 2)
thp_midrail_on
thp_midrail_off
(Note 4)
(Note 5)
AVDD/2
HP Outputs
GD
GD
GD
DACDAT pin
DACEN bit
DAC enabled
DAC disabled
Analogue outputs
enable bits
VMIDSEL/
BIASEN bits
DAC off
DAC enabled
DAC disabled
Analogue outputs enabled
(Note 6)
VMID enabled
Figure 11 DAC Power Up and Down Sequence (not to scale)
SYMBOL
MIN
TYPICAL
MAX
UNIT
tline_midrail_on
300
tline_midrail_off
>6
ms
s
thp_midrail_on
300
ms
thp__midrail_off
>6
s
tdacint
2/fs
n/fs
DAC Group Delay
29/fs
n/fs
Table 3 Typical POR Operation (typical values, not tested)
Notes:
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1.
The lineout charge time, tline_midrail_on, is determined by the VMID pin charge time. This time is
dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and
AVDD power supply rise time. The values above were measured using a 4.7μF capacitor.
2.
It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data
value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue
outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute
function has been applied to the signal beforehand.
3.
The lineout discharge time, tline_midrail_off, is determined by the VMID pin discharge time. This time
is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance. The
values above were measured using a 4.7μF capacitor.
4.
The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling
capacitor and VMID pin input resistance and AVDD power supply rise time. The values above
were measured using a 4.7μF VMID decoupling capacitor.
5.
The headphone discharge time, thp_midrail_off, is dependent upon the value of VMID decoupling
capacitor and VMID pin input resistance. The values above were measured using a 4.7μF VMID
decoupling capacitor.
6.
The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for
normal DAC operation.
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DEVICE DESCRIPTION
INTRODUCTION
The WM8758B is a low power audio codec combining a high quality stereo audio DAC and ADC, with
flexible line and microphone input and output processing.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as
follows:
MICROPHONE INPUTS
Two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be
pseudo-differentially connected, with user defined gain. The provision of the common mode input pin
for each stereo input allows for rejection of common mode noise on the microphone inputs (level
depends on gain setting chosen). A microphone bias is output from the chip which can be used to
bias both microphones. The signal routing can be configured to allow manual adjustment of mic
levels, or to allow the ALC loop to control the level of mic signal that is transmitted.
Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually
or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the
recording volume constant.
ADC
The stereo ADC uses a 24-bit high-order oversampling architecture to deliver optimum performance
with low power consumption.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type
applications, including MP3 players and portable disc players of all types.
OUTPUT MIXERS
Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo
headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs
allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are
provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to allow
for all possible signal combinations.
OUT3 and OUT4 can be configured to provide an additional stereo or mono differential lineout from
the output of the DACs, the mixers or the input microphone boost stages. They can also provide a
midrail reference for pseudo differential inputs to external amplifiers. OUT3 and OUT4 should not be
used as a buffered midrail reference in capless mode.
AUDIO INTERFACES
The WM8758B has a standard audio interface, to support the transmission of stereo data to and from
the chip. This interface is a 3 wire standard audio interface which supports a number of audio data
formats including:
2
IS
DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words are
transmitted)
MSB-First, left justified
MSB-First, right justified
The interface can operate in master or slave modes.
CONTROL INTERFACES
To allow full software control over all features, the WM8758B offers a choice of 2 or 3 wire control
interface. It is fully compatible and an ideal partner for a wide range of industry standard
microprocessors, controllers and DSPs.
Selection of the mode is via the MODE pin. In 2 wire mode, the address of the device is fixed as
0011010b.
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CLOCKING SCHEMES
WM8758B offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to
the DAC and ADC. A PLL is included which may be used to generate these clocks in the event that
they are not available from the system controller. This PLL can accept a range of common input clock
frequencies between 8MHz and 50MHz to generate high quality audio clocks. If this PLL is not
required for generation of these clocks, it can be reconfigured to generate alternative clocks which
may then be output on the GPIO pins and used elsewhere in the system.
POWER CONTROL
The design of the WM8758B has given much attention to power consumption without compromising
performance. It operates at very low voltages, includes the ability to power off any unused parts of the
circuitry under software control, and includes standby and power off modes.
INPUT SIGNAL PATH
The WM8758B has a number of flexible analogue inputs. There are two input channels, Left and
Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into
the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to
accommodate single-ended, differential or dual differential microphones. A bypass path exists from
the output of the boost/mix stage into the output left/right mixers.
MICROPHONE INPUTS
The WM8758B can accommodate a variety of microphone configurations including single ended and
differential inputs. The inputs to the left differential input PGA are LIN, LIP and L2. The inputs to the
right differential input PGA are RIN, RIP and R2.
In single-ended microphone input configuration the microphone signal should be input to LIN or RIN
and the internal NOR gate configured to clamp the non-inverting input of the input PGA to VMID.
In differential mode the larger signal should be input to LIP or RIP and the smaller (e.g. noisy ground
connection) should be input to LIN or RIN.
Figure 12 Microphone Input PGA Circuit
The input PGAs are enabled by the IPPGAENL/R register bits.
REGISTER
ADDRESS
R2
Power
Management
2
BIT
2
LABEL
INPPGAENL
DEFAULT
0
DESCRIPTION
Left channel input PGA enable
0 = disabled
1 = enabled
3
INPPGAENR
0
Right channel input PGA enable
0 = disabled
1 = enabled
Table 4 Input PGA Enable Register Settings
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REGISTER
ADDRESS
BIT
R44
0
LABEL
LIP2INPPGA
DEFAULT
1
Input
Control
DESCRIPTION
Connect LIP pin to left channel input PGA
amplifier positive terminal.
0 = LIP not connected to input PGA
1 = input PGA amplifier positive terminal
connected to LIP (constant input
impedance)
1
LIN2INPPGA
1
Connect LIN pin to left channel input PGA
negative terminal.
0 = LIN not connected to input PGA
1 = LIN connected to input PGA amplifier
negative terminal.
2
L2_2INPPGA
0
Connect L2 pin to left channel input PGA
positive terminal.
0 = L2 not connected to input PGA
1 = L2 connected to input PGA amplifier
positive terminal (constant input
impedance).
4
RIP2INPPGA
1
Connect RIP pin to right channel input
PGA amplifier positive terminal.
0 = RIP not connected to input PGA
1 = right channel input PGA amplifier
positive terminal connected to RIP
(constant input impedance)
5
RIN2INPPGA
1
Connect RIN pin to right channel input
PGA negative terminal.
0 = RIN not connected to input PGA
1 = RIN connected to right channel input
PGA amplifier negative terminal.
6
R2_2INPPGA
0
Connect R2 pin to right channel input PGA
positive terminal.
0 = R2 not connected to input PGA
1 = R2 connected to input PGA amplifier
positive terminal (constant input
impedance).
Table 5 Input PGA Control
INPUT PGA VOLUME CONTROLS
The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain
from the LIN/RIN input to the PGA output and from the L2/R2 amplifier to the PGA output are always
common and controlled by the register bits INPPGAVOLL/R[5:0]. These register bits also affect the
LIP pin when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1, the RIP pin when RIP2INPPGA=1
and the L2 pin when L2_2INPPGA=1.
When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled automatically
and the INPPGAVOLL/R bits should not be used.
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REGISTER
ADDRESS
BIT
R45
5:0
LABEL
INPPGAVOLL
DEFAULT
010000
Left channel
input PGA
volume
control
DESCRIPTION
Left channel input PGA volume
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = +35.25dB
6
INPPGAMUTEL
0
Mute control for left channel input PGA:
0 = Input PGA not muted, normal
operation
1 = Input PGA muted (and disconnected
from the following input BOOST stage).
7
INPPGAZCL
0
Left channel input PGA zero cross
enable:
0 = Update gain when gain register
changes
st
1 = Update gain on 1 zero cross after
gain register write.
8
INPPGAVU
Not
latched
5:0
INPPGAVOLR
010000
INPPGA left and INPPGA right volume
do not update until a 1 is written to
INPPGAVU (in reg 45 or 46)
(See “Volume Updates” below)
R46
Right channel input PGA volume
000000 = -12dB
Right
channel
input PGA
volume
control
000001 = -11.25db
.
010000 = 0dB
.
111111 = +35.25dB
6
INPPGAMUTER
0
Mute control for right channel input PGA:
0 = Input PGA not muted, normal
operation
1 = Input PGA muted (and disconnected
from the following input BOOST stage).
7
INPPGAZCR
0
Right channel input PGA zero cross
enable:
0 = Update gain when gain register
changes
st
1 = Update gain on 1 zero cross after
gain register write.
8
INPPGAVU
Not
latched
INPPGA left and INPPGA right volume
do not update until a 1 is written to
INPPGAVU (in reg 45 or 46)
8:7
ALCSEL
00
ALC function select:
(See “Volume Updates” below)
R32
ALC control
1
00 = ALC off
01 = ALC right only
10 = ALC left only
11 = ALC both on
Table 6 Input PGA Volume Control
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VOLUME UPDATES
Volume settings will not be applied to the PGAs until a ‘1’ is written to one of the INPPGAVU bits.
This is to allow left and right channels to be updated at the same time, as shown in Figure 13.
Figure 13 Simultaneous Left and Right Volume Updates
If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in
Figure 14.
Figure 14 Click Noise during Volume Update
In order to prevent this click noise, a zero cross function is provided. When enabled, this will cause
the PGA volume to update only when a zero crossing occurs, equalizer click noise as shown in
Figure 15.
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Figure 15 Volume Update using Zero Cross Detection
If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8758B will
automatically update the volume. The volume updates will occur between one and two timeout
periods, depending on when the INPPGAVU bit is set as shown in Figure 16.
Figure 16 Volume Update after Timeout
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INPUT BOOST
Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST circuit
has 3 selectable inputs: the input microphone PGA output, the L2/R2 input pin (can be used as a line
input, bypassing the input PGA), and OUT4 mixer output. These three inputs can be mixed together
and have individual gain boost/adjust as shown in Figure 17.
Figure 17 Input Boost Stage
The input PGA paths can have a +20dB boost (PGABOOSTL/R=1), a 0dB pass through
(PGABOOSTL/R=0) or be completely isolated from the input boost circuit (INPPGAMUTEL/R=1).
REGISTER
ADDRESS
R47
BIT
8
LABEL
PGABOOSTL
DEFAULT
1
Left Input
BOOST
control
DESCRIPTION
Boost enable for left channel input
PGA:
0 = PGA output has +0dB gain through
input BOOST stage.
1 = PGA output has +20dB gain
through input BOOST stage.
R48
8
PGABOOSTR
Right Input
BOOST
control
1
Boost enable for right channel input
PGA:
0 = PGA output has +0dB gain through
input BOOST stage.
1 = PGA output has +20dB gain
through input BOOST stage.
Table 7 Input BOOST Stage Control
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REGISTER
ADDRESS
R42
BIT
8:6
LABEL
DEFAULT
OUT4_2ADCVOL
000
OUT4 to ADC
DESCRIPTION
Controls the OUT4 to ADC input
boost stage:
000 = Path disabled
(disconnected)
001 = -12dB gain through boost
stage
010 = -9dB gain through boost
stage
…
111 = +6dB gain through boost
stage
5
OUT4_2LNR
0
OUT4 to L or R ADC input
0 = Right ADC input
1 = Left ADC input
R47
6:4
L2_2BOOSTVOL
000
Left channel
Input BOOST
control
Controls the L2 pin to the left
channel input boost stage:
000 = Path disabled
(disconnected)
001 = -12dB gain through boost
stage
010 = -9dB gain through boost
stage
…
111 = +6dB gain through boost
stage
R48
6:4
R2_2BOOSTVOL
000
Right channel
Input BOOST
control
Controls the R2 pin to the right
channel input boost stage:
000 = Path disabled
(disconnected)
001 = -12dB gain through boost
stage
010 = -9dB gain through boost
stage
…
111 = +6dB gain through boost
stage
Table 8 Input BOOST Stage Control
The BOOST stage is enabled under control of the BOOSTEN register bit.
REGISTER
ADDRESS
R2
Power
management
2
BIT
4
LABEL
BOOSTENL
DEFAULT
0
DESCRIPTION
Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
5
BOOSTENR
0
Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Table 9 Input BOOST Enable Control
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MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. Refer to the Applications
Information section for recommended external components. The MICBIAS voltage can be altered via
the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD1 and when MBVSEL=1,
MICBIAS=0.65*AVDD1. The output can be enabled or disabled using the MICBEN control bit.
REGISTER
ADDRESS
R1
BIT
4
LABEL
DEFAULT
MICBEN
0
DESCRIPTION
Microphone Bias Enable
Power
management 1
0 = OFF (high impedance output)
1 = ON
Table 10 Microphone Bias Enable Control
REGISTER
ADDRESS
R44
BIT
8
LABEL
MBVSEL
DEFAULT
0
DESCRIPTION
Microphone Bias Voltage Control
Input control
0 = 0.9 * AVDD1
1 = 0.65 * AVDD1
Table 11 Microphone Bias Voltage Control
The internal MICBIAS circuitry is shown in Figure 18. Note that the maximum source current
capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit
the MICBIAS current to 3mA.
MICBE
internal
resistor
internal
resistor
MICBIAS
VMI
MBVSEL=0
MICBIAS
= 1.8 x VMID
= 0.9 X AVDD
MBVSEL=1
MICBIAS
= 1.3 x VMID
= 0.65 X AVDD
AGND1
Figure 18 Microphone Bias Schematic
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8758B uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full
Scale input level is proportional to AVDD1. With a 3.3V supply voltage, the full scale level is 1.0Vrms.
Any voltage greater than full scale may overload the ADC and cause distortion.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital
filter path for each ADC channel is illustrated in Figure 19.
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Figure 19 ADC Digital Filter Path
The ADCs are enabled by the ADCENL/R register bit.
REGISTER
ADDRESS
R2
BIT
0
LABEL
ADCENL
DEFAULT
0
DESCRIPTION
Enable ADC left channel:
Power
management 2
0 = ADC disabled
1 = ADC enabled
1
ADCENR
0
Enable ADC right channel:
0 = ADC disabled
1 = ADC enabled
Table 12 ADC Enable Control
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the
ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
REGISTER
ADDRESS
R14
BIT
0
LABEL
ADCLPOL
DEFAULT
0
ADC Control
DESCRIPTION
ADC left channel polarity adjust:
0 = normal
1 = inverted
1
ADCRPOL
0
ADC right channel polarity adjust:
0 = normal
1 = inverted
3
ADCOSR
0
ADC oversample rate select:
0 = 64x (lower power)
1 = 128x (best performance)
Table 13 ADC Control
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two
modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off
frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off
frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown
in Table 15.
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REGISTER
ADDRESS
BIT
R14
LABEL
DEFAULT
8
HPFEN
1
7
HPFAPP
0
DESCRIPTION
High Pass Filter Enable
0 = disabled
ADC Control
1 = enabled
Select audio mode or application mode
st
0 = Audio mode (1 order, fc = ~3.7Hz)
nd
1 = Application mode (2 order, fc =
HPFCUT)
6:4
HPFCUT
000
Application mode cut-off frequency
See Table 15 for details.
Table 14 ADC Enable Control
HPFCUT
SR=101/100
SR=011/010
[2:0]
SR=001/000
fs (kHz)
8
11.025
12
16
22.05
24
32
44.1
48
000
82
113
122
82
113
122
82
113
122
001
102
141
153
102
141
153
102
141
153
010
131
180
156
131
180
156
131
180
156
011
163
225
245
163
225
245
163
225
245
100
204
281
306
204
281
306
204
281
306
101
261
360
392
261
360
392
261
360
392
110
327
450
490
327
450
490
327
450
490
111
408
563
612
408
563
612
408
563
612
Table 15 High Pass Filter Cut-off Frequencies (HPFAPP=1)
Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the
SR register bits are set correctly for the actual sample rate as shown in Table 15.
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PROGRAMMABLE NOTCH FILTER
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth,
programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits
NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup
there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R27
6:0
NFA0[13:7]
0
Notch Filter a0 coefficient, bits [13:7]
Notch Filter 1
7
NFEN
0
Notch filter enable:
0 = Disabled
8
NFU
0
1 = Enabled
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
R28
NFA0[6:0]
0
Notch Filter a0 coefficient, bits [6:0]
8
NFU
0
Notch filter update. The notch filter
values used internally only update
R29
6:0
NFA1[13:7]
0
Notch Filter a1 coefficient, bits [13:7]
Notch Filter 3
8
NFU
0
Notch filter update. The notch filter
6:0
Notch Filter 2
when one of the NFU bits is set high.
values used internally only update
when one of the NFU bits is set high.
R30
0-6
Notch Filter 4
8
NFA1[6:0]
0
Notch Filter a1 coefficient, bits [6:0]
NFU
0
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
Table 16 Notch Filter Function
The coefficients are calculated as follows:
a0
1 tan( wb / 2)
1 tan( wb / 2)
a1 (1 a0 ) cos( w0 )
Where:
w0 2f c / f s
wb 2f b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz
The actual register values can be determined from the coefficients as follows:
13
NFA0 = -a0 x 2
12
NFA1 = -a1 x 2
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps.
The gain for a given eight-bit code X is given by:
0.5 (G-255) dB for 1 G 255;
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REGISTER
ADDRESS
R15
BIT
7:0
Left channel
ADC Digital
Volume
LABEL
DEFAULT
DESCRIPTION
ADCLVOL
11111111
Left ADC Digital Volume Control
[7:0]
( 0dB )
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
R16
8
ADCVU
Not
latched
ADC left and ADC right volume do not
update until a 1 is written to ADCVU (in
reg 15 or 16)
7:0
ADCRVOL
11111111
Right ADC Digital Volume Control
[7:0]
( 0dB )
0000 0000 = Digital Mute
Right channel
ADC Digital
Volume
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
8
ADCVU
Not
latched
ADC left and ADC right volume do not
update until a 1 is written to ADCVU (in
reg 15 or 16)
Table 17 ADC Digital Volume Control
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
The WM8758B has an automatic PGA gain control circuit, which can function as an input peak limiter
or as an automatic level control (ALC).
In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal
goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too
large for the input range of the ADC. When the signal returns to a level below the threshold, the PGA
gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain above its
static level.
Figure 20 Input Peak Limiter Operation
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In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective of
the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level
at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the
PGA gain if necessary.
Figure 21 ALC Operation
The ALC/Limiter function is enabled by setting the register bit ALCSEL. When enabled, the recording
volume can be programmed between –1dB and –22.5dB (relative to ADC full scale) using the
ALCLVL register bits. An upper limit for the PGA gain can be imposed by setting the ALCMAX
control bits and a lower limit for the PGA gain can be imposed by setting the ALCMIN control bits.
ALCHLD, ALCDCY and ALCATK control the hold, decay and attack times, respectively:
Hold time is the time delay between the peak level detected being below target and the PGA gain
n
beginning to ramp up. It can be programmed in power-of-two (2 ) steps, e.g. 2.67ms, 5.33ms,
10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time is not
active in limiter mode (ALCMODE = 1). The hold time only applies to gain ramp-up, there is no delay
before ramping the gain down when the signal level is above target.
Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up and is given as a
time per gain step, time per 6dB change and time to ramp up over 90% of it’s range. The decay time
n
can be programmed in power-of-two (2 ) steps, from 3.3ms/6dB, 6.6ms/6dB, 13.1ms/6dB, etc. to
3.36s/6dB.
Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down and is given
as a time per gain step, time per 6dB change and time to ramp down over 90% of it’s range. The
n
attack time can be programmed in power-of-two (2 ) steps, from 832us/6dB, 1.66ms/6dB,
3.328us/6dB, etc. to 852ms/6dB.
NB, In peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of fast
peaks. Attack and Decay times for peak limiter mode are given below.
The hold, decay and attack times given in Table 18 are constant across sample rates so long as the
SR bits are set correctly. E.g. when sampling at 48kHz the sample rates stated in Table 18 will only
be correct if the SR bits are set to 000 (48kHz). If the actual sample rate was only 44.1kHz then the
hold, decay and attack times would be scaled down by 44.1/48.
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REGISTER
ADDRESS
R32
BIT
8:7
LABEL
ALCSEL
DEFAULT
00
ALC Control
1
DESCRIPTION
ALC function select
00 = ALC disabled
01 = Right channel ALC enabled
10 = Left channel ALC enabled
11 = Both channels ALC enabled
5:3
ALCMAXGAIN
[2:0]
111
(+35.25dB)
Set Maximum Gain of PGA
111 = +35.25dB
110 = +29.25dB
101 = +23.25dB
100 = +17.25dB
011 = +11.25dB
010 = +5.25dB
001 = -0.75dB
000 = -6.75dB
2:0
ALCMINGAIN
000 (-12dB)
[2:0]
Set minimum gain of PGA
000 = -12dB
001 = -6dB
010 = 0dB
011 = +6dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +30dB
R33
7:4
ALC Control
2
ALCHLD
0000
[3:0]
(0ms)
ALC hold time before gain is
increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.7s
3:0
ALCLVL
1011
[3:0]
(-6dB)
ALC target – sets signal level at ADC
input
1111 = -1.5dBFS
1110 = -1.5dBFS
1101 = -3dBFS
1100 = -4.5dBFS
...... (-1.5dB steps)
0001 = -21dBFS
0000 = -22.5dBFS
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REGISTER
ADDRESS
R34
BIT
8
LABEL
ALCMODE
DEFAULT
0
ALC Control
3
DESCRIPTION
Determines the ALC mode of
operation:
0 = ALC mode
1 = Limiter mode.
7:4
ALCDCY
0011
Decay (gain ramp-up) time
[3:0]
(13.1ms/6dB)
(ALCMODE ==0)
Per
step
Per
6dB
90% of
range
0000
410us
3.3ms
24ms
0001
820us
6.6ms
48ms
0010
1.64ms
13.1ms
192ms
… (time doubles with every step)
1010
or
higher
420ms
3.36s
0011
Decay (gain ramp-up) time
(2.9ms/6dB)
(ALCMODE ==1)
Per
step
Per
6dB
24.576s
90% of
range
0000
90.8us
726.4us
5.26ms
0001
181.6us
1.453ms
10.53ms
0010
363.2us
2.905ms
21.06ms
… (time doubles with every step)
1010
3:0
93ms
744ms
5.39s
ALCATK
0010
ALC attack (gain ramp-down) time
[3:0]
(832us/6dB)
(ALCMODE == 0)
Per
step
Per
6dB
90% of
range
0000
104us
832us
6ms
0001
208us
1.664ms
12ms
0010
416us
3.328ms
24.1ms
… (time doubles with every step)
1010
or
higher
106ms
852ms
6.18s
0010
ALC attack (gain ramp-down) time
(182us/6dB)
(ALCMODE == 1)
Per
step
Per
6dB
90% of
range
0000
22.7us
182.4us
1.31ms
0001
45.4us
363.2us
2.62ms
0010
90.8us
726.4us
5.26ms
… (time doubles with every step)
1010
23.2ms
186ms
1.348s
Table 18 ALC Control Registers
When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input
gain update must be made by writing to the INPPGAVOLL/R register bits.
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MINIMUM AND MAXIMUM GAIN
The ALCMINGAIN and ALCMAXGAIN register sets the minimum/maximum gain value that the PGA
can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not
enabled.
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is
ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
(Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is
designed to prevent clipping when long attack times are used).
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8758B has a noise gate function
that prevents noise pumping by comparing the signal level at the input pins against a noise gate
threshold, NGTH. The noise gate cuts in when:
Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to:
Signal level at input pin [dBFS] < NGTH [dBFS]
The PGA gain is then held constant (preventing it from ramping up as it normally would when the
signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise
gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.
Levels at the extremes of the range may cause inappropriate operation, so care should be taken with
set–up of the function. The noise gate only operates in conjunction with the ALC and cannot be used
in limiter mode.
REGISTER
ADDRESS
R35
BIT
2:0
LABEL
NGTH
DEFAULT
000
DESCRIPTION
Noise gate threshold:
ALC Noise Gate
000 = -39dB
Control
001 = -45dB
010 = -51db
… (6dB steps)
111 = -81dB
3
NGATEN
0
Noise gate function enable
1 = enable
0 = disable
Table 19 ALC Noise Gate Control
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OUTPUT SIGNAL PATH
The WM8758B output signal paths consist of digital application filters, up-sampling filters, stereo
Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The
digital filters and DAC are enabled by register bits DACENL and DACENR. The mixers and output
drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is
possible to equalizer the analogue mixing and amplification provided by the WM8758B, irrespective
of whether the DACs are running or not.
The WM8758B DACs receive digital input data on the DACDAT pin. The digital filter block processes
the data to provide the following functions:
Digital volume control
Graphic equaliser
A digital peak limiter.
Sigma-Delta Modulation
High performance sigma-delta audio DAC converts the digital data into an analogue signal.
Figure 22 DAC Digital Filter Path
The analogue outputs from the DACs can then be mixed with the ADC analogue inputs. The mix is
fed to the output drivers for headphone (LOUT1/ROUT1, LOUT2/ROUT2) or line (OUT3/OUT4).
OUT3 and OUT4 have additional mixers which allow them to output different signals to the
headphone and line outputs.
DIGITAL PLAYBACK (DAC) PATH
Digital data is passed to the WM8758B via the flexible audio interface and is then passed through a
variety of advanced digital filters as shown in Figure 22 to the hi-fi DACs. The DACs are enabled by
the DACENL/R register bits.
REGISTER
ADDRESS
R3
BIT
0
LABEL
DACENL
DEFAULT
0
Power
Management 3
DESCRIPTION
Left channel DAC enable
0 = DAC disabled
1 = DAC enabled
1
DACENR
0
Right channel DAC enable
0 = DAC disabled
1 = DAC enabled
Table 20 DAC Enable Control
The WM8758B also has a Soft Mute function, which when enabled, gradually attenuates the volume
of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This
function is enabled by default. To play back an audio signal, it must first be disabled by setting the
SOFTMUTE bit to zero.
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REGISTER
ADDRESS
R10
BIT
0
LABEL
DEFAULT
DACPOL
0
DAC Control
DESCRIPTION
Left DAC output polarity:
0 = non-inverted
1 = inverted (180 degrees phase shift)
1
DACRPOL
0
Right DAC output polarity:
0 = non-inverted
1 = inverted (180 degrees phase shift)
2
AMUTE
0
Automute enable
0 = Amute disabled
1 = Amute enabled
3
DACOSR
0
DAC oversampling rate:
0 = 64x (lowest power & best
performance)
1 = 128x
6
SOFTMUTE
0
Softmute enable:
0 = Enabled
1 = Disabled
Table 21 DAC Control Register
The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital
interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a
high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and
sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low
distortion.
The DAC output phase defaults to non-inverted. Setting DACLPOL will invert the DAC output phase
on the left channel and DACRPOL inverts the phase on the right channel.
AUTO-MUTE
The DAC has an auto-mute function which applies an analogue mute when 1024 consecutive zeros
are detected. The mute is released as soon as a non-zero sample is detected. Auto-mute can be
disabled using the AMUTE control bit.
DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain range is –127dB to 0dB
in 0.5dB steps. The level of attenuation for an eight-bit code X is given by:
0.5 (X-255) dB for 1 X 255;
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REGISTER
ADDRESS
R11
BIT
7:0
Left DAC
Digital Volume
LABEL
DEFAULT
DESCRIPTION
DACLVOL
11111111
Left DAC Digital Volume Control
[7:0]
( 0dB )
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
R12
8
DACVU
Not
latched
DAC left and DAC right volume do
not update until a 1 is written to
DACVU (in reg 11 or 12)
7:0
DACRVOL
11111111
Right DAC Digital Volume Control
[7:0]
( 0dB )
0000 0000 = Digital Mute
Right DAC
Digital Volume
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
8
DACVU
Not
latched
DAC left and DAC right volume do
not update until a 1 is written to
DACVU (in reg 11 or 12)
Table 22 DAC Digital Volume Control
Note: An additional gain of up to 12dB can be added using the gain block embedded in the
digital peak limiter circuit (see DAC OUTPUT LIMITER section).
5-BAND EQUALISER
A 5-band graphic equalizer function which can be used to change the output frequency levels to suit
the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND
EQUALISER section for further details on this feature.
3-D ENHANCEMENT
The WM8758B has an advanced digital 3-D enhancement feature which can be used to vary the
perceived stereo separation of the left and right channels. Like the 5-band equalizer this feature can
be applied to either the ADC record path or the DAC equalizer path but not both simultaneously.
Refer to the 3-D STEREO ENHANCEMENT section for further details on this feature.
DAC DIGITAL OUTPUT LIMITER
The WM8758B has a digital output limiter function. The operation of this is shown in Figure 23. In
this diagram the upper graph shows the envelope of the input/output signals and the lower graph
shows the gain characteristic.
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Figure 23 DAC Digital Limiter Operation
The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 23, in
normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the
limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK
register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB
below the upper threshold. When the signal falls below the lower threshold the signal is amplified at
a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both
threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the
value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value.
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VOLUME BOOST
The limiter has programmable upper gain which boosts signals below the threshold to compress the
dynamic range of the signal and increase its perceived loudness. This operates as an ALC function
with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the
LIMBOOST register bits.
The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter
is disabled.
REGISTER
ADDRESS
R24
BIT
3:0
LABEL
LIMATK
DEFAULT
0010
DAC digital
limiter control
1
DESCRIPTION
Limiter Attack time (per 6dB gain
change) for 44.1kHz sampling. Note
that these are proportionally related to
sample rate.
0000 = 94us
0001 = 188s
0010 = 375us
0011 = 750us
0100 = 1.5ms
0101 = 3ms
0110 = 6ms
0111 = 12ms
1000 = 24ms
1001 = 48ms
1010 = 96ms
1011 to 1111 = 192ms
7:4
LIMDCY
0011
Limiter Decay time (per 6dB gain
change) for 44.1kHz sampling. Note
that these are proportionally related to
sample rate:
0000 = 750us
0001 = 1.5ms
0010 = 3ms
0011 = 6ms
0100 = 12ms
0101 = 24ms
0110 = 48ms
0111 = 96ms
1000 = 192ms
1001 = 384ms
1010 = 768ms
1011 to 1111 = 1.536s
8
LIMEN
0
3:0
LIMBOOST
0000
Enable the DAC digital limiter:
0=disabled
1=enabled
R25
DAC digital
limiter control
2
Limiter volume boost (can be used as a
stand alone volume boost when
LIMEN=0):
0000 = 0dB
0001 = +1dB
0010 = +2dB
… (1dB steps)
1011 = +11dB
1100 = +12dB
1101 to 1111 = reserved
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REGISTER
ADDRESS
BIT
6:4
LABEL
LIMLVL
DEFAULT
000
DESCRIPTION
Programmable signal threshold level
(determines level at which the limiter
starts to operate)
000 = -1dB
001 = -2dB
010 = -3dB
011 = -4dB
100 = -5dB
101 to 111 = -6dB
Table 23 DAC Digital Limiter Control
5-BAND GRAPHIC EQUALISER
A 5-band graphic equalizer is provided, which can be applied to the ADC or DAC path, together with
3D enhancement, under control of the EQ3DMODE register bit. The ADCs and DACs should be
disabled before changing the EQ3DMODE bit.
By default, the WM8758B operates in low power mode, and the DSP core runs at half of the normal
rate. In DAC low power mode, only 2-Band equalizer functionality is permitted, where only Band 1
(low shelf) and Band 5 (high shelf) can be used. For ADC low power, the equalizer and 3D cannot be
used. To enable full 5-band operation, set M128ENB = 1.
REGISTER
ADDRESS
R18
BIT
8
LABEL
EQ3DMODE
DEFAULT
1
EQ Control 1
DESCRIPTION
0 = Equaliser and 3D Enhancement
applied to ADC path
1 = Equaliser and 3D Enhancement
applied to DAC path
Table 24 EQ and 3D Enhancement DAC or ADC Path Select
The equalizer consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters
for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB
in 1dB steps). The peak filters have selectable bandwidth.
REGISTER
ADDRESS
R18
BIT
4:0
LABEL
EQ1G
EQ Band 1
Control
6:5
EQ1C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 1 Gain Control. See Table 30 for
details.
01
Band 1 Cut-off Frequency:
00 = 80Hz
01 = 105Hz
10 = 135Hz
11 = 175Hz
Table 25 EQ Band 1 Control
REGISTER
ADDRESS
R19
BIT
4:0
LABEL
EQ2G
EQ Band 2
Control
6:5
EQ2C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 2 Gain Control. See Table 30 for
details.
01
Band 2 Centre Frequency:
00 = 230Hz
01 = 300Hz
8
EQ2BW
0
10 = 385Hz
11 = 500Hz
Band 2 Bandwidth Control
0 = narrow bandwidth
1 = wide bandwidth
Table 26 EQ Band 2 Control
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REGISTER
ADDRESS
R20
BIT
4:0
LABEL
EQ3G
EQ Band 3
Control
6:5
EQ3C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 3 Gain Control. See Table 30 for
details.
01
Band 3 Centre Frequency:
00 = 650Hz
01 = 850Hz
8
EQ3BW
10 = 1.1kHz
11 = 1.4kHz
Band 3 Bandwidth Control
0
0 = narrow bandwidth
1 = wide bandwidth
Table 27 EQ Band 3 Control
REGISTER
ADDRESS
R21
BIT
4:0
LABEL
EQ4G
EQ Band 4
Control
6:5
EQ4C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 4 Gain Control. See Table 30 for
details
01
Band 4 Centre Frequency:
00 = 1.8kHz
01 = 2.4kHz
10 = 3.2kHz
8
EQ4BW
11 = 4.1kHz
Band 4 Bandwidth Control
0
0 = narrow bandwidth
1 = wide bandwidth
Table 28 EQ Band 4 Control
REGISTER
ADDRESS
R22
BIT
4:0
LABEL
EQ5G
EQ Band 5
Gain Control
6:5
EQ5C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 5 Gain Control. See Table 30 for
details.
01
Band 5 Cut-off Frequency:
00 = 5.3kHz
01 = 6.9kHz
10 = 9kHz
11 = 11.7kHz
Table 29 EQ Band 5 Control
GAIN REGISTER
GAIN
00000
+12dB
00001
+11dB
00010
+10dB
…. (1dB steps)
01100
0dB
01101
-1dB
11000 to 11111
-12dB
Table 30 Gain Register Table
See also Figure 49 to Figure 66 for equaliser and high pass filter responses.
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3D STEREO ENHANCEMENT
The WM8758B has a digital 3D enhancement option to increase the perceived separation between
the left and right channels. Selection of 3D for record or playback is controlled by register bit
EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done
when ADC and DAC are disabled. The WM8758B control interface will only allow EQ3DMODE to be
changed when ADC and DAC are disabled (ie ADCENL = 0, ADCENR = 0, DACENL = 0 and
DACENR = 0).
The DEPTH3D setting controls the degree of stereo expansion.
When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting.
In ADC low power mode (See Power Management section), the equaliser and 3D cannot be used. To
enable 3D enhancement and 5-band EQ operation, set M128ENB = 1.
REGISTER
ADDRESS
R41 (29h)
BIT
3:0
LABEL
DEPTH3D[3:0]
DEFAULT
0000
3D Control
DESCRIPTION
Stereo depth
0000 = 0% (minimum 3D effect)
0001 = 6.67%
....
1110 = 93.3%
1111 = 100% (maximum 3D effect)
Table 31 3D Stereo Enhancement Function
ANALOGUE OUTPUTS
The WM8758B has three sets of stereo analogue outputs. These are:
LOUT1 and ROUT1 which can be used as headphone or line drivers.
LOUT2 and ROUT2 – which can be used as headphone or line drivers.
OUT3 and OUT4 – can be configured as a stereo line out (OUT3 is left output and
OUT4 is right output). OUT4 can also be used to provide a mono mix of left and
right channels.
The outputs LOUT2 and ROUT2 are powered from AVDD2 and are capable of driving a 1V rms
signal (AVDD1/3.3).
LOUT1, ROUT1, OUT3 and OUT4 are powered from AVDD1.
LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB
gain ranges.
There are four output mixers in the output signal path, the left and right channel mixers which control
the signals to headphone (and optionally the line outputs) and also dedicated OUT3 and OUT4
mixers.
LEFT AND RIGHT OUTPUT CHANNEL MIXERS
The left and right output channel mixers are shown in Figure 24. These mixers allow the ADC bypass
and the DAC left and right channels to be combined as desired. This allows a mono mix of the DAC
channels to be performed as well as mixing in speech from the input bypass path.
The bypass inputs have individual volume control from -15dB to +6dB and the DAC volume can be
adjusted in the digital domain if required. The output of these mixers is connected to both the stereo
headphone drivers (LOUT1, ROUT1, LOUT2 and ROUT2) and can optionally be connected to the
OUT3 and OUT4 mixers.
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Figure 24 Left/Right Output Channel Mixers
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REGISTER
ADDRESS
R43
BIT
8
LABEL
BYPL2RMIX
DEFAULT
0
Output mixer
control
DESCRIPTION
Left bypass path (from the Left
channel input PGA stage) to right
output mixer
0 = not selected
1 = selected
R43
7
BYPR2LMIX
0
Output mixer
control
Right bypass path (from the right
channel input PGA stage) to Left
output mixer
0 = not selected
1 = selected
R49
5
DACR2LMIX
0
Output mixer
control
Right DAC output to left output mixer
0 = not selected
1 = selected
6
DACL2RMIX
0
Left DAC output to right output mixer
0 = not selected
1 = selected
R50
Left channel
output mixer
control
0
DACL2LMIX
0
Left DAC output to left output mixer
0 = not selected
1 = selected
1
BYPL2LMIX
0
Left bypass path (from the left
channel input PGA stage) to left
output mixer
0 = not selected
1 = selected
4:2
BYPLMIXVOL
000
Left bypass volume contol to output
channel mixer:
000 = -15dB
001 = -12dB
…
101 = 0dB
110 = +3dB
111 = +6dB
R51
0
DACR2RMIX
0
Right channel
output mixer
control
Right DAC output to right output
mixer
0 = not selected
1 = selected
1
BYPR2RMIX
0
Right bypass path (from the right
channel input PGA stage) to right
output mixer
0 = not selected
1 = selected
4:2
BYPRMIXVOL
000
Right bypass volume control to
output channel mixer:
000 = -15dB
001 = -12dB
…
101 = 0dB
110 = +3dB
111 = +6dB
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REGISTER
ADDRESS
R3
Power
management
3
BIT
2
LABEL
DEFAULT
LMIXEN
0
DESCRIPTION
Left output channel mixer enable:
0 = disabled
1= enabled
3
RMIXEN
0
Right output channel mixer enable:
0 = disabled
1 = enabled
Table 32 Left and Right Output Mixer Control
HEADPHONE OUTPUTS (LOUT1 AND ROUT1)
The headphone outputs LOUT1 and ROUT1 can drive a 16 or 32 headphone load, either through
DC blocking capacitors, or DC-coupled to a buffered midrail reference (LOUT2 or ROUT2), saving a
capacitor (capless mode). When using capless mode, AVDD1 and AVDD2 should use the same
supply to equalize supply rejection. OUT3 and OUT4 should not be used as a buffered midrail
reference in capless mode.
Each headphone output has an analogue volume control PGA with a gain range of -57dB to +6dB as
shown in Figure 25.
In order to provide common mode rejection of ground noise on the left and right outputs, a
headphone common ground feedback option is provided. HP_COM input may be used as HPCOM
common ground feedback signal. This signal is compared to the chip internal midrail voltage and the
difference used as the reference input to the headphone output buffer amplifier, as shown in Figure
25, and in more detail in the analog internal circuit diagram.
Figure 25 Headphone Outputs LOUT1 and ROUT1
Headphone Output using DC Blocking Capacitors: with HPCOM
common mode feedback applied
DC Coupled Headphone Output: no HPCOM feedback
Figure 26 Recommended Headphone Output Configurations
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When DC blocking capacitors are used, their capacitance and the load resistance together determine
the lower cut-off frequency of the output signal, fc. Increasing the capacitance lowers fc, improving the
bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load
and C1, C2 = 220F:
fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz
The AC coupling capacitor into the HP_COM feedback input requires to be a much smaller value,
typically 4.7uF as the internal resistance it is driving into is typically 22kohm.
In the DC coupled configuration, the headphone pseudo-ground is connected to the buffered midrail
reference pin (LOUT2 or ROUT2). The L/ROUT2 pins can be configured as a DC output driver by
setting the LOUT2MUTE and ROUT2MUTE register bits. The DC voltage on VMID in this
configuration is equal to the DC offset on the LOUT1 and ROUT1 pins therefore no DC blocking
capacitors are required. This saves space and material cost in portable applications.
It is not recommended to use DC-coupling to line inputs of another device. Although the built-in short
circuit protection on the headphone outputs would be tolerant of shorts to ground, such a connection
may be noisy, and may not function properly if the other device is grounded. DC-coupled
configurations should only be used with headphones.
COMMON MODE DEFAULT
The common mode feedback mode is enabled by writing a 1 to HP_COM or LINE_COM (reg 49 bits
7 and 8). Under normal operation these registers defaults 0 (common mode disabled). However the
polarity of these registers can be inverted by using 2-wire control interface mode and holding the
CSB_GPIO1 pin high. In this mode of operation HP_COM=0 enables HP common mode, and
HP_COM=1 disables HP common mode. Similarly LINE_COM=0 enables LINE common mode and
LINE_COM=1 disables LINE common mode. Note that if the CSB_GPIO1 is configured as a GPIO
the operation of HP_COM and LINE_COM revert back to non-inverted operation.
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REGISTER
ADDRESS
R49
BIT
8
LABEL
HP_COMEN
DEFAULT
0
DESCRIPTION
Headphone common ground enable:
1 = Use external common ground
0 = use internal VMID
0
Function inverts if MODE = 2-wire
And CSB/GPIO1 = ‘hi’
0 = Use external common ground
1 = Use internal VMID
R52
7
LOUT1ZC
0
LOUT1
Headphone volume zero cross
enable:
1 = Change gain on zero cross only
Volume
control
0 = Change gain immediately
6
LOUT1MUTE
0
Left headphone output mute:
0 = Normal operation
1 = Mute
5:0
LOUT1VOL
111001
Left headphone output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
R53
8
HPVU
7
ROUT1ZC
Not latched
0
ROUT1
Volume
control
LOUT1 and ROUT1 volumes do not
update until a 1 is written to HPVU
(in reg 52 or 53)
Headphone volume zero cross
enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6
ROUT1MUTE
0
Right headphone output mute:
0 = Normal operation
1 = Mute
5:0
ROUT1VOL
111001
Right headphone output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
8
HPVU
Not latched
LOUT1 and ROUT1 volumes do not
update until a 1 is written to HPVU
(in reg 52 or 53)
Table 33 OUT1 Volume Control
HEADPHONE OUTPUTS (LOUT2 AND ROUT2)
The outputs LOUT2 and ROUT2 are designed to drive two headphone loads of 16 or 32 or line
outputs (See Headphone Output and Line Output sections, respectively). Each output has an
individual volume control PGA, a mute and an enable control bit as shown in Figure 27. LOUT2 and
ROUT2 output the left and right channel mixer outputs respectively.
The LOUT2/ROUT2 outputs also have the option of incorporating common ground feedback from the
output signal ground, via a connection to the LINE_COM input. This common ground feedback signal
should be AC-coupled via a 4.7uF capacitor as for the headphone common mode feedback path. AC
coupling of these outputs if they are used as LINE level outputs requires similar 1 to 4.7uF AC
coupling capacitors depending upon LINE load resistance.
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Figure 27 LOUT2 and ROUT2 Headphone Configuration with Feedback
Figure 28 LOUT2 and ROUT2 Line Output Configuration with Feedback
The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any
combination of the DAC output and the bypass path (output of the input boost stage). The
LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Gains over 0dB
may cause clipping if the input signal is too high. The LOUT2MUTE/ ROUT2MUTE register bits
cause these outputs to be muted (the output DC level is driven out). The output pins remain at the
same DC level, so that no click noise is produced when muting or un-muting.
REGISTER
ADDRESS
R49
BIT
7
LABEL
LINE_COMEN
DEFAULT
0
DESCRIPTION
Line common ground enable:
1 = Use external common ground
0 = use internal VMID
0
Function inverts if MODE = 2-wire
And CSB/GPIO1 = ‘hi’
0 = Use external common ground
1 = Use internal VMID
Table 34 Line Common Control
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REGISTER
ADDRESS
R54
LOUT2
Volume
control
BIT
7
LABEL
DEFAULT
LOUT2ZC
0
DESCRIPTION
LOUT2 volume zero cross enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6
LOUT2MUTE
0
Left output mute:
0 = Normal operation
1 = Mute
5:0
LOUT2VOL
111001
Left output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
R55
ROUT2
Volume
control
8
SPKVU
7
ROUT2ZC
Not latched
LOUT2 and ROUT2 volumes do not
update until a 1 is written to SPKVU
(in reg 54 or 55)
0
ROUT2 volume zero cross enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6
ROUT2MUTE
0
Right output mute:
0 = Normal operation
1 = Mute
5:0
ROUT2VOL
111001
Right output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
8
SPKVU
Not latched
LOUT2 and ROUT2 volumes do not
update until a 1 is written to SPKVU
(in reg 54 or 55)
Table 35 OUT2 Volume Control
ZERO CROSS TIMEOUT
A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs
the gain will automatically update after a timeout period if a zero cross has not occurred. This is
enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital
21
and is equal to 2 * SYSCLK period.
REGISTER
ADDRESS
R7
BIT
0
LABEL
SLOWCLKEN
Additional
Control
DEFAULT
0
DESCRIPTION
Slow clock enable. Used for both the
jack insert detect debounce circuit and
the zero cross timeout.
0 = slow clock disabled
1 = slow clock enabled
Table 36 Timeout Clock Enable Control
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OUT3/OUT4 MIXERS AND OUTPUT STAGES
The OUT3/OUT4 pins provide an additional stereo line output, a mono output, or a differential line
output. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 29.
The OUT3 and OUT4 output stages are powered from AVDD1 and AGND1.
Figure 29 OUT3 and OUT4 Mixers
OUT3 can provide a midrail reference, a left line output, or a mono mix line output.
OUT4 can provide a midrail reference, a right line output, or a mono mix line output.
Note: OUT3 and OUT4 should not be used as a buffered midrail pseudo GND in capless mode.
A 6dB attenuation function is provided for OUT4, to prevent clipping during mixing of left and right
signals. This function is enabled by the OUT4ATTN register bit.
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REGISTER
ADDRESS
R56
BIT
6
LABEL
OUT3MUTE
DEFAULT
0
DESCRIPTION
0 = Output stage outputs OUT3 mixer
1 = Output stage muted – drives out
VMID. Can be used as VMID reference
in this mode. (Not to be used for Capless
HP pseudo GND)
OUT3 mixer
control
3
OUT4_2OUT3
0
OUT4 mixer output to OUT3
0 = disabled
1 = enabled
2
BYPL2OUT3
0
Left ADC input to OUT3
0 = disabled
1 = enabled
1
LMIX2OUT3
0
Left DAC mixer to OUT3
0 = disabled
1 = enabled
0
LDAC2OUT3
1
Left DAC output to OUT3
0 = disabled
1 = enabled
R57
7
OUT3_2OUT4
0
OUT3 mixer output to OUT4
0 = disabled
OUT4 mixer
control
1 = enabled
6
OUT4MUTE
0
0 = Output stage outputs OUT4 mixer
1 = Output stage muted – drives out
VMID. Can be used as VMID reference
in this mode. (Not to be used for Capless
HP pseudo GND)
5
OUT4ATTN
0
0 = OUT4 normal output
1 = OUT4 attenuated by 6dB
4
LMIX2OUT4
0
Left DAC mixer to OUT4
0 = disabled
1 = enabled
3
LDAC2OUT4
0
Left DAC to OUT4
0 = disabled
1 = enabled
2
BYPR2OUT4
0
Right ADC input to OUT4
0 = disabled
1 = enabled
1
RMIX2OUT4
0
Right DAC mixer to OUT4
0 = disabled
1 = enabled
0
RDAC2OUT4
1
Right DAC output to OUT4
0 = disabled
1 = enabled
Table 37 OUT3/OUT4 Mixer Registers
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ENABLING THE OUTPUTS
Each analogue output of the WM8758B can be independently enabled or disabled. The analogue
mixer associated with each output has a separate enable bit. All outputs are disabled by default. To
save power, unused parts of the WM8758B should remain disabled.
Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled
(BUFIOEN=0), as this may cause pop noise (see “Power Management” and “Applications
Information” sections).
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1
2
BUFIOEN
0
Unused input/output bias buffer enable
Power
Management
1
6
OUT3MIXEN
0
OUT3 mixer enable
7
OUT4MIXEN
0
OUT4 mixer enable
R2
8
ROUT1EN
0
ROUT1 output enable
Power
Management
2
7
LOUT1EN
0
LOUT1 output enable
6
SLEEP
0
0 = Normal device operation
1 = Supply current reduced in device
standby mode (see note)
R3
2
LMIXEN
0
Left mixer enable
Power
Management
3
3
RMIXEN
0
Right mixer enable
5
ROUT2EN
0
ROUT2 output enable
6
LOUT2EN
0
LOUT2 output enable
7
OUT3EN
0
OUT3 enable
8
OUT4EN
0
OUT4 enable
Note: All “Enable” bits are 1 = ON, 0 = OFF
Table 38 Output Stages Power Management Control
Note: The SLEEP bit R2[6] should only be used when the device is already in standby mode. The
SLEEP bit prevents the MCLK from propagating round the device when the external MCLK signal
cannot be removed.
THERMAL SHUTDOWN
To protect the WM8758B from becoming too hot, a thermal sensor has been built in. If the chip
temperature reaches approximately 150C and the TSDEN and TSOPCTRL bit are set, then all
outputs will be disabled to avoid further increase of the chip temperature.
Additionally, when the device is too hot and TSDEN is set, then the WM8758B de-asserts GPIO bit
11, a virtual GPIO that can be set up to generate an interrupt to the CPU (see “GPIO and Interrupt
Control” section).
REGISTER
ADDRESS
R49
BIT
1
LABEL
TSDEN
DEFAULT
0
Output Control
DESCRIPTION
Thermal Sensor Enable
0 = disabled
1 = enabled
2
TSOPCTRL
0
Thermal Shutdown Output enable
0 = Disabled
1 = Enabled, i.e. all outputs will be
disabled if TI set, i.e. temperature above
150ºC
Table 39 Thermal Shutdown
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to a voltage source (AVDD1/2)
through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance
between the voltage buffer and the output pins can be controlled using the VROI control bit. The
default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a
high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance
to about 30k.
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REGISTER
ADDRESS
R49
BIT
0
LABEL
VROI
DEFAULT
0
DESCRIPTION
VREF (AVDD1/2) to analogue output
resistance
0 = approx 1k
1 = approx 30 k
Table 40 Disabled Outputs to VREF Resistance
A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 30. This
buffer can be enabled using the BUFIOEN register bit.
Figure 30 summarises the bias options for the output pins.
Figure 30 Unused Input/Output Pin Tie-off Buffers
L/ROUT2EN/
VROI
OUTPUT CONFIGURATION
OUT3/4EN
0
0
1kΩ to AVDD1/2
0
1
30kΩ to AVDD1/2
1
X
Output enabled (DC level=AVDD1/2)
Table 41 Unused Output Pin Bias Options
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DIGITAL AUDIO INTERFACES
The audio interface has four pins:
ADCDAT: ADC data output
DACDAT: DAC data input
LRC: Data Left/Right alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK, and LRC can be outputs when the WM8758B operates as a master, or
inputs when it is a slave (see Master and Slave Mode Operation, below).
Five different audio data formats are supported:
Left justified
Right justified
IS
DSP mode A
DSP mode B
2
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8758B audio interface may be configured as either master or slave. As a master interface
device the WM8758B generates BCLK and LRC and thus controls sequencing of the data transfer on
ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In
slave mode (MS=0), the WM8758B responds with data to clocks it receives over the digital audio
interfaces.
In master mode, the BCLK and LRC clocks are not stopped when the ADC’s are disabled using
register R2[1:0] and the DAC’s are disabled using register R3{[:0]. The ADCDAT pin continuously
outputs the last word of data which was transmitted when the ADC was disabled. To prevent this in
master mode, it is necessary to disable the ADC’s R2[1:0] and DAC’s R3{[:0] and remove the MCLK
input clock OR by switching the digital audio interface to slave mode.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.
Figure 31 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition.
All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and
sample rate, there may be unused BCLK cycles after each LRC transition.
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Figure 32 Right Justified Audio Interface (assuming n-bit word length)
2
In I S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The
other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency
and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of
the next.
2
Figure 33 I S Audio Interface (assuming n-bit word length)
st
nd
In DSP/PCM mode, the left channel MSB is available on either the 1 (mode B) or 2 (mode A) rising
edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately
follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be
unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the LRC pulse shown in Figure 34 and Figure
35. In device slave mode, Figure 36 and Figure 37, it is possible to use any length of LRC pulse less
than 1/fs, providing the falling edge of the LRC pulse occurs greater than one BCLK period before the
rising edge of the next LRC pulse.
Figure 34 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
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Figure 35 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)
Figure 36 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
Figure 37 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)
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REGISTER
ADDRESS
R4
BIT
0
LABEL
MONO
DEFAULT
0
Audio
Interface
Control
DESCRIPTION
Selects between stereo and mono
device operation:
0 = Stereo device operation
1 = Mono device operation. Data
appears in ‘left’ phase of LRC.
1
ADCLRSWAP
0
Controls whether ADC data appears in
‘right’ or ‘left’ phases of LRC clock:
0 = ADC left data appear in ‘left’ phase
of LRC and right data in ‘right’ phase
1 = ADC left data appear in ‘right’ phase
of LRC and right data in ‘left’ phase
2
DACLRSWAP
0
Controls whether DAC data appears in
‘right’ or ‘left’ phases of LRC clock:
0 = DAC left data appear in ‘left’ phase
of LRC and right data in ‘right’ phase
1 = DAC left data appear in ‘right’ phase
of LRC and right data in ‘left’ phase
4:3
FMT
10
Audio interface Data Format Select:
00 = Right Justified
01 = Left Justified
2
10 = I S format
11 = DSP/PCM mode
6:5
WL
10
Word length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits (see note)
7
LRP
0
2
RJ, LJ & I S modes – LRC polarity
0 = normal LRC polarity
1 = invert LRC polarity
DSP Mode – mode A/B select
nd
0 = MSB is available on 2 BCLK rising
edge after LRC rising edge (mode A)
st
1 = MSB is available on 1 BCLK rising
edge after LRC rising edge (mode B)
8
BCP
0
BCLK polarity
0 = normal
1 = inverted
R5
0
LOOPBACK
0
Digital loopback function
0 = No loopback
1 = Loopback enabled, ADC data output
is fed directly into DAC data input.
Table 42 Audio Interface Control
Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the
device will operate in 24-bit mode.
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below.
Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK and
LRC are outputs. The frequency of BCLK and LRC in master mode is controlled with BCLKDIV.
These are divided down versions of master clock. This may result in short BCLK pulses at the end of
a LRC if there is a non-integer ratio of BCLKs to LRC clocks.
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REGISTER
ADDRESS
R6
BIT
0
LABEL
MS
DEFAULT
0
Clock
Generation
Control
DESCRIPTION
Sets the chip to be master over LRC and
BCLK
0 = BCLK and LRC clock are inputs
1 = BCLK and LRC clock are outputs
generated by the WM8758B (MASTER)
4:2
BCLKDIV
000
Configures the BCLK and LRC output
frequency, for use when the chip is
master over BCLK.
000 = divide by 1 (BCLK=SYSCLK)
001 = divide by 2 (BCLK=SYSCLK/2)
010 = divide by 4
011 = divide by 8
100 = divide by 16
101 = divide by 32
110 = reserved
111 = reserved
7:5
MCLKDIV
010
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000 = divide by 1
001 = divide by 1.5
010 = divide by 2
011 = divide by 3
100 = divide by 4
101 = divide by 6
110 = divide by 8
111 = divide by 12
8
CLKSEL
1
Controls the source of the clock for all
internal operation:
0 = MCLK
1 = PLL output
Table 43 Clock Control
The CLKSEL bit selects the internal source of the Master clock from the PLL (MCLK=1) or from
MCLK (MCLKSEL=0). When the internal clock is switched from one source to another using the
CLKSEL bit, the clock originally selected must generate at least one falling edge after CLKSEL has
changed for the switching of clocks to be successful.
EXAMPLE:
If the PLL is the current source of the internal clock (CLKSEL=1) and it is required to switch to the
MCLK, change CLKSEL to select MCLK (CLKSEL=0) and then disable PLL (PLLEN=0).
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8758B supports A-law and -law companding on both transmit (ADC) and receive (DAC)
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate
value to the DAC_COMP or ADC_COMP register bits respectively.
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REGISTER
ADDRESS
R5
BIT
2:1
LABEL
DEFAULT
ADC_COMP
0
DESCRIPTION
ADC companding
00 = off
Companding
Control
01 = reserved
10 = µ-law
11 = A-law
4:3
DAC_COMP
0
DAC companding
00 = off
01 = reserved
10 = µ-law
11 = A-law
5
WL8
0
0 = off
1 = device operates in 8-bit mode.
Table 44 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
-law (where =255 for the U.S. and Japan):
F(x) = ln( 1 + |x|) / ln( 1 + )
-1 ≤ x ≤ 1
law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
for x ≤ 1/A
F(x) = ( 1 + lnA|x|) / (1 + lnA)
for 1/A ≤ x ≤ 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s
of data.
Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The
input data range is separated into 8 levels, allowing low amplitude signals better precision than that
of high amplitude signals. This is to exploit the operation of the human auditory system, where louder
sounds do not require as much resolution as quieter sounds. The companded signal is an 8-bit word
containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to
use 8 BCLK’s per LRC frame. When using DSP mode B, this allows 8-bit data words to be output
consecutively every 8 BCLK’s and can be used with 8-bit data words using the A-law and u-law
companding functions.
BIT7
BIT[6:4]
BIT[3:0]
SIGN
EXPONENT
MANTISSA
Table 45 8-bit Companded Word Composition
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u-law Companding
1
120
0.9
Companded Output
0.7
80
0.6
0.5
60
0.4
40
0.3
Normalised Output
0.8
100
0.2
20
0.1
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalised Input
Figure 38 µ-Law Companding
A-law Companding
1
120
0.9
Companded Output
0.7
80
0.6
0.5
60
0.4
40
0.3
Normalised Output
0.8
100
0.2
20
0.1
0
0
0
0.2
0.4
0.6
0.8
1
Normalised Input
Figure 39 A-Law Companding
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AUDIO SAMPLE RATES
The WM8758B filter characteristics for the ADCs and the DACs are set using the SR register bits.
The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these
values and assume a 256fs master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the closest
SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay
and hold times will scale appropriately.
REGISTER
ADDRESS
R7
BIT
LABEL
3:1
SR
DEFAULT
000
Additional
Control
DESCRIPTION
Approximate sample rate (configures the
coefficients for the internal digital filters):
000 = 48kHz
001 = 32kHz
010 = 24kHz
011 = 16kHz
100 = 12kHz
101 = 8kHz
110-111 = reserved
Table 46 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8758B has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8758B audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from
an existing audio master clock.
Figure 40 shows the PLL and internal clocking on the WM8758B.
The PLL can be enabled or disabled by the PLLEN register bit.
REGISTER
ADDRESS
R1
BIT
5
Power
management 1
LABEL
PLLEN
DEFAULT
0
DESCRIPTION
PLL enable
0 = PLL off
1 = PLL on
Table 47 PLLEN Control Bit
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Figure 40 PLL and Clock Select Circuit
The PLL frequency ratio R = f2/f1 (see Figure 40) can be set using the register bits PLLK and PLLN:
PLLN = int R
24
PLLK = int (2 (R-PLLN))
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable
divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
PLLN = int R = 8
24
k = int ( 2 x (8.192 – 8)) = 3221225 = 3126E9h
REGISTER
ADDRESS
R36
BIT
4
LABEL
PLLPRESCALE
DEFAULT
0
PLL N value
R37
0 = MCLK input not divided (default)
1= Divide MCLK by 2 before input to
PLL
3:0
PLLN
1000
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
5:0
PLLK [23:18]
0Ch
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
8:0
PLLK [17:9]
093h
8:0
PLLK [8:0]
0E9h
PLL K value
1
R38
DESCRIPTION
PLL K Value
2
R39
PLL K Value
3
Table 48 PLL Frequency Ratio Control
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PRESCALE DIVIDE
POSTSCALE DIVIDE
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown below.
1
2
12
12.288
98.304
1
2
13
11.29
90.3168
1
2
6.947446 6h F28BD4h 0110 (XX6h) 000111100 (03Ch) 101000101 (145h) 111010100 (1D4h)
7.561846 7h 8FD525h 0111 (XX7h) 000100011 (023h) 111101010 (1Eah) 100100101 (125h)
MCLK
(MHz)
(f1)
DESIRED
OUTPUT
(SYSCLK)
f2
(MHz)
(MHz)
12
11.2889025 90.31122
R
N
K
N
REGISTER
R36[3:0]
K REGISTERS
R37
R38
R39
7.525935 7h 86A3ACh 0111 (XX7h) 000100001 (021h) 101010001 (151h) 110101100 (1ACh)
8.192
8h
3126E8h 1000 (XX8h) 000001100 (00Ch) 010010011 (093h) 011101000 (0E8h)
13
12.288
98.304
1
2
14.4
11.29
90.3168
1
2
14.4
12.288
98.304
1
2
19.2
11.29
90.3168
2
2
9.408
9h
19.2
12.288
98.304
2
2
10.24
Ah 3D70A3h 1010 (XXAh) 000001111 (00Fh) 010111000 (0B8h) 010100011 (0A3h)
19.68
11.29
90.3168
2
2
9.178537 9h 2DB492h 1001 (XX9h) 000001011 (00Bh) 011011010 (0Dah) 010010010 (092h)
19.68
12.288
98.304
2
2
9.990243 9h FD809Fh 1001 (XX9h) 000111111 (03Fh) 011000000 (0C0h) 010011111 (09Fh)
19.8
11.29
90.3168
2
2
9.122909 9h 1F76F7h 1001 (XX9h) 000000111 (007h) 110111011 (1BBh) 011110111 (0F7h)
19.8
12.288
98.304
2
2
9.929697 9h EE009Eh 1001 (XX9h) 000111011 (03Bh) 100000000 (100h) 010011110 (09Eh)
7.525935 7h 86A3ACh 0111 (XX7h) 000100001 (021h) 101010001 (151h) 110101100 (1ACh)
24
11.2889025 90.31122
6.272
6h 45A1Cah 0110 (XX6h) 000010001 (011h) 011010000 (0D0h) 111001010 (1Cah)
6.826667 6h D3A06Eh 0110 (XX6h) 000110100 (034h) 111010000 (1D0h) 001101110 (06Eh)
6872Afh
1001 (XX9h) 000011010 (01Ah) 000111001 (039h)
010101111 (0Afh)
2
2
24
12.288
98.304
2
2
26
11.29
90.3168
2
2
26
12.288
98.304
2
2
7.561846 7h 8FD525h 0111 (XX7h) 000100011 (023h) 111101010 (1Eah) 100100101 (125h)
27
11.29
90.3168
2
2
6.690133 6h B0AC93h 0110 (XX6h) 000101100 (02Ch) 001010110 (056h)
010010011 (093h)
27
12.288
98.304
2
2
7.281778 7h
010010110 (096h)
8.192
8h
3126E8h 1000 (XX8h) 000001100 (00Ch) 010010011 (093h) 011101000 (0E8h)
6.947446 6h F28BD4h 0110 (XX6h) 000111100 (03Ch) 101000101 (145h) 111010100 (1D4h)
482296h
0111 (XX7h) 000010010 (012h) 000010001 (011h)
Table 49 PLL Frequency Examples
GENERAL PURPOSE INPUT/OUTPUT
The WM8758B has three dual purpose input/output pins.
CSB/GPIO1: CSB / GPIO1 pin
L2/GPIO2: Left channel line input / headphone detection input
R2/GPIO3: Right channel line input / headphone detection input
The GPIO2 and GPIO3 functions are provided for use as jack detection inputs.
The GPIO1 and GPIO2 functions are provided for use as jack detection inputs or general purpose
outputs.
The default configuration for the CSB/GPIO1 is to be an input.
When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection,
depending on how the MODE pin is set.
Table 50 illustrates the functionality of the GPIO1 pin when used as a general purpose output.
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REGISTER
ADDRESS
R8
BIT
2:0
LABEL
GPIO1SEL
DEFAULT
000
GPIO
DESCRIPTION
CSB/GPIO1 pin function select:
000 = input (CSB / Jack detection:
depending on MODE setting)
Control
001 = reserved
010 = Temp ok
011 = Amute active
100 = PLL clk output
101 = PLL lock
110 = logic 0
111 = logic 1
3
GPIO1POL
0
GPIO1 Polarity invert
0 = Non inverted
1 = Inverted
5:4
OPCLKDIV
00
PLL Output clock division ratio
00 = divide by 1
01 = divide by 2
10 = divide by 3
11 = divide by 4
6
GPIO1GPD
0
GPIO1 Internal pull-down enable:
0 = Internal pull-down disabled
1 = Internal pull-down enabled
7
GPIO1GPU
0
GPIO1 Internal pull-up enable:
0 = Internal pull-up disabled
1 = Internal pull-up enabled
8
GPIO1GP
0
GPIO1 Open drain enable
0 = Open drain disabled
1 = Open drain enabled
Table 50 CSB/GPIO Control
Note: If MODE is set to 3 wire mode, CSB/GPIO1 is used as CSB input irrespective of the
GPIO1SEL[2:0] bits.
For further details of the jack detect operation see the OUTPUT SWITCHING section.
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OUTPUT SWITCHING (JACK DETECT)
When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch
control input to automatically disable one set of outputs and enable another. The L2/GPIO2 and
R2/GPIO3 pins can also be used for this purpose.
The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output
enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a
21
slow clock with period 2 x MCLK.
Note that the GPIOPOL bit is not relevant for jack detection, it is the signal detected at the pin which
is used.
The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3
and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0 are
the output enable signals which are used if the selected jack detection pin is at logic 0 (after debounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output enable signals
which are used if the selected jack detection pin is at logic 1 (after de-bounce).
Similar to the output enables, VMID can be output to OUT3. This VMID output can be configured to
be on/off depending on the jack detection input polarity of VMID_EN_0 and VMID_EN_1.
The jack detection enables operate as follows:
All OUT_EN signals have an AND function performed with their normal enable signals (in Table 38).
When an output is normally enabled at per Table 38, the selected jack detection enable (controlled
by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is
already OFF (0), the jack detection signal will have no effect due to the AND function.
During jack detection if the user desires an output to be un-changed whether the jack is in or not,
both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000.
The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the
VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should
set to 0 for all JD_EN0 or JD_EN1 settings.
If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs
to be controlled as normal via the normal output enables found in Table 38. Similarly the VMID_EN
signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit.
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REGISTER
ADDRESS
BIT
R9
5:4
LABEL
DEFAULT
JD_SEL
00
GPIO control
DESCRIPTION
Pin selected as jack detection input
00 = GPIO1
01 = GPIO2
10 = GPIO3
11 = Reserved
6
JD_EN
0
Jack Detection Enable
0 = disabled
1 = enabled
8:7
JD_VMID
00
3:0
JD_EN0
0000
[7] VMID_EN_0
[8] VMID_EN_1
R13
Output enables when selected jack
detection input is logic 0.
0000 = OUT1_EN_0
0001 = OUT2_EN_0
0010 = OUT3_EN_0
0011 = OUT4_EN_0
0100-1111 = Reserved
7:4
JD_EN1
0000
Output enables when selected jack
detection input is logic 1
0000-0011 = Reserved
0100 = OUT1_EN_1
0101 = OUT2_EN_1
0110 = OUT3_EN_1
0111 = OUT4_EN_1
1000-1111 = Reserved
Table 51 Jack Detect Register Control Bits
CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire control interface. The MODE pin
determines the 2 or 3 wire mode as shown in Table 52.
The WM8758B is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are register address bits that select which control
register is accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 data bits in
each control register.
MODE
INTERFACE FORMAT
Low
2 wire
High
3 wire
Table 52 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB/GPIO latches in a complete control word consisting of the last 16 bits.
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Figure 41 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8758B supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit
address of each register in the WM8758B).
The WM8758B operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8758B, the WM8758B responds by pulling SDIN low on the next clock pulse
(ACK). If the address is not equalized or the R/W bit is ‘1’ when operating in write only mode, the
WM8758B returns to the idle condition and waits for a new start condition and valid address.
During a write, once the WM8758B has acknowledged a correct address, the controller sends the
first byte of control data (B15 to B8, i.e. the WM8758B register address plus the first bit of register
data). The WM8758B then acknowledges the first data byte by driving SDIN low for one clock cycle.
The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of
register data), and the WM8758B acknowledges again by pulling SDIN low.
Transfer is complete when there is a low to high transition on SDIN while SCLK is high. After a
complete sequence the WM8758B returns to the idle state and waits for another start condition. If a
start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN
changes while SCLK is high), the control interface returns to the idle condition.
DEVICE ADDRESS
(7 BITS)
SDIN
RD / WR
BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 1
(BITS 7 TO 0)
ACK
(LOW)
SCLK
START
register address and
1st register data bit
remaining 8 bits of
register data
STOP
Figure 42 2-Wire Serial Control Interface
In 2-wire mode the WM8758B has a fixed device address, 0011010.
In 2-wire mode the CSB/GPIO1 pin controls the inversion of the HP_COM and LINE_COM register
bits. When CSB/GPIO1 is set, these register bits are inverted (providing CSB/GPIO1 is not
configured as a GPIO). See the section titled COMMON MODE DEFAULT for more details.
RESETTING THE CHIP
The WM8758B can be reset by performing a write of any value to the software reset register (address
0h). This will cause all register values to be reset to their default values. In addition to this there is a
Power-On Reset (POR) circuit which ensures that the registers are initially set to default when the
device is powered up.
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POWER SUPPLIES
The WM8758B requires four separate power supplies:
AVDD1 and AGND1: Analogue supply, powers all internal analogue functions and
output drivers LOUT1, ROUT1, OUT3 and OUT4. AVDD1 must be between 2.5V and
3.6V and has the most significant impact on overall power consumption (except for
power consumed in the headphones). Higher AVDD will improve audio quality.
AVDD2 and AGND2: Output driver supplies, power LOUT2 and ROUT2. AVDD2 must
be between 2.5V and 3.6V. AVDD2 can be tied to AVDD1, but it requires separate
layout and decoupling capacitors to curb harmonic distortion.
DCVDD: Digital core supply, powers all digital functions except the audio and control
interfaces. DCVDD must be between 1.71V and 3.6V, and has no effect on audio
quality. The return path for DCVDD is DGND, which is shared with DBVDD.
DBVDD must be between 1.71V and 3.6V. DBVDD return path is through DGND.
It is possible to use the same supply voltage for all four supplies. However, digital and analogue
supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of
the analogue signal paths.
POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under
the control of ADCOSR128 the oversampling rate may be doubled. 64x oversampling results in a
slight decrease in noise performance compared to 128x but lowers the power consumption of the
device.
REGISTER
ADDRESS
R14
BIT
3
LABEL
ADCOSR128
DEFAULT
0
ADC control
DESCRIPTION
ADC oversample rate select
0 = 64x (lowest power)
1 = 128x (best SNR)
Table 53 ADC Oversampling Rate Selection
LOW POWER MODE
If only DAC or ADC functionality is required, the WM8758B can be put into a low power mode. In this
mode, the DSP core runs at half of the normal rate, reducing digital power consumption of the core
by half. For DAC low power only, 3D enhancement with 2-Band equalizer functionality is permitted,
where only Band 1 (low shelf) and Band 5 (high shelf) can be used. For ADC low power, the
equalizer and 3D cannot be used.
REGISTER
ADDRESS
R7
BIT
8
LABEL
M128ENB
Additional Ctrl
DEFAULT
0
DESCRIPTION
0 = low power mode enabled
1 = low power mode disabled
Table 54 DSP Core Low Power Mode Control
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There are 3 modes of low power operation, as detailed below. The device will not enter low power
unless in one of these register configurations, regardless of M128ENB.
FUNCTION
ADC low power
DAC low power
REGISTER BITS
SETTING
M128ENB
0
ADCENL
1
ADCENR
1
DACENL
0
DACENR
0
EQ3DMODE
1 (DAC path)
M128ENB
0
ADCENL
0
ADCENR
0
DACENL
1
DACENR
1
DESCRIPTION
Either or both of ADCENL and
ADCENR must be set (mono or
stereo mode)
Either or both of DACENL and
DACENR must be set (mono or
stereo mode)
EQ3DMODE = 0: EQ in ADC path
EQ3DMODE = 1: EQ in DAC path
Table 55 DSP Core Low Power Modes for ADC Only and DAC Only Modes
VMID
The analogue equalizer will not operate unless VMID is enabled. The impedance of the VMID resistor
string, together with the decoupling capacitor on the VMID pin will determine the startup time of the
VMID circuit.
REGISTER
ADDRESS
BIT
1:0
R1
LABEL
DEFAULT
VMIDSEL
00
Power
management 1
DESCRIPTION
Reference string impedance to VMID pin
(Determines startup time):
00 = off (250kΩ VMID to AGND1)
01 = 100kΩ
10 = 500kΩ
11 = 10kΩ (for fast startup)
Table 56 VMID Impedance Control
BIASEN
The analogue amplifiers will not operate unless BIASEN is enabled.
REGISTER
ADDRESS
R1
BIT
3
LABEL
BIASEN
DEFAULT
0
DESCRIPTION
Analogue amplifier bias control
0 = disabled
Power
management 1
1 = enabled
Table 57 Analogue Bias Control
HALFOPBIAS
HALFOPBIAS halves the bias current to the output drivers (OUT1, OUT2, OUT3). Setting
HALFOPBIAS will reduce the quiescent current from AVDD by 0.5mA but will degrade the THD+N
significantly.
REGISTER
ADDRESS
R61
Bias Control
BIT
0
LABEL
HALFO
PBIAS
DEFAULT
0
DESCRIPTION
HALFOPBIAS (Do not use)
0 = disabled
1 = enabled (Reduces AVDD current by
0.5mA)
Table 58 HALFOPBIAS Control
Wolfson’s recommendation is: Do not use HALFOPBIAS
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POP MINIMISATION
POBCTRL
WM8758B has two bias generators. A noisy bias derived from AVDD and a low noise bias derived
from VMID. POBCTRL is use to switch between the two bias generators. During power up, the
AVDD derived bias is available as soon as AVDD is applied; the VMID derived bias is available once
the VMID node has charged up.
VMIDTOG
Fast VMID discharge is enabled using VMIDTOG bit. Setting to 1 opens a low impedance discharge
path from VMID to GND. This function can be used during power down to reduce the discharge time
of the VMID decoupling capacitor. Must be set to 0 for normal operation.
REGISTER
ADDRESS
R42
BIT
2
OUT4 to ADC
LABEL
POB
DEFAULT
0
CTRL
DESCRIPTION
POBCTRL (Use during power Up. Reset
when VMID bias is stable)
0 = Bias derived from VMID
1 = Bias derived from AVDD
4
VMID
0
TOG
Fast VMID discharge
0 = normal operation
1 = enabled (used during power-down
sequence
Table 59 POBCTRL and VMIDTOG Control
POBCTRL should be asserted during power up to minimize pops and then de-asserted at the end of
the power up sequence to give best performance. Refer to Recommended Power Up/Down
Sequence
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REGISTER MAP
ADDR
B[15:9]
REGISTER
NAME
B8
B7
B6
B5
B4
B3
B2
B1
B0
VAL
DEC HEX
(HEX)
0
00
Software Reset
1
01
Power manage’t 1
2
02
DEF’T
Power manage’t 2
Software reset
0
ROUT1EN
OUT4MIX
OUT3MIX
EN
EN
LOUT1EN
SLEEP
PLLEN
MICBEN
BIASEN
BUFIOEN
BOOST
BOOST
INPGA
INPPGA
ENR
ENL
ENR
ENL
3
03
Power manage’t 3
OUT4EN
OUT3EN
LOUT2EN ROUT2EN
4
04
Audio Interface
BCP
LRP
WL
5
05
Companding ctrl
0
0
0
0
WL8
RMIXEN
VMIDSEL
LMIXEN
000
ADCENR
ADCENL
DACENR
000
DACENL
000
FMT
DLRSWAP ALRSWAP
MONO
050
DAC_COMP
ADC_COMP
LOOP
000
BACK
6
06
Clock Gen ctrl
CLKSEL
7
07
Additional ctrl
M128ENB
MCLKDIV
8
08
GPIO Stuff
GPIO1GP
GPIO1GPU GPIO1GPD
9
09
Jack detect control
JD_VMID1
JD_VMID0
JD_EN
10
0A
DAC Control
0
0
SOFT
11
0B
Left DAC digital Vol
DACVU
DACLVOL
0FF
12
0C
Right DAC dig’l Vol
DACVU
DACRVOL
0FF
13
0D
Jack Detect Control
14
0E
ADC Control
0
BCLKDIV
0
0
0
0
SR
MS
140
SLOWCLK
000
EN
OPCLKDIV
GPIO1POL
JD_SEL
0
0
DACOSR
AMUTE
0
0
MUTE
0
GPIO1SEL[2:0]
HPFAPP
000
0
DACRPOL DACLPOL
000
000
128
JD_EN1
HPFEN
0
JD_EN0
HPFCUT
ADCOSR
0
000
ADCRPOL ADCLPOL
100
128
15
0F
Left ADC Digital Vol
ADCVU
ADCLVOL
0FF
16
10
Right ADC Digital
Vol
ADCVU
ADCRVOL
0FF
18
12
EQ1 – low shelf
EQ3DMODE
0
EQ1C
EQ1G
12C
19
13
EQ2 – peak 1
EQ2BW
0
EQ2C
EQ2G
02C
20
14
EQ3 – peak 2
EQ3BW
0
EQ3C
EQ3G
02C
21
15
EQ4 – peak 3
EQ4BW
0
EQ4C
EQ4G
02C
22
16
EQ5 – high shelf
0
0
EQ5C
EQ5G
02C
24
18
DAC Limiter 1
LIMEN
25
19
DAC Limiter 2
0
0
27
1B
Notch Filter 1
NFU
NFEN
NFA0[13:7]
000
28
1C
Notch Filter 2
NFU
0
NFA0[6:0]
000
29
1D
Notch Filter 3
NFU
0
NFA1[13:7]
000
30
1E
Notch Filter 4
NFU
0
NFA1[6:0]
32
20
ALC control 1
33
21
ALC control 2
0
34
22
ALC control 3
ALCMODE
35
23
Noise Gate
0
0
0
0
0
36
24
PLL N
0
0
0
0
PLLPRE
LIMDCY
ALCSEL
LIMLVL
0
LIMATK
032
LIMBOOST
000
000
ALCMAX
ALCMIN
ALCHLD
ALCDCY
038
ALCLVL
00B
ALCATK
032
NGEN
NGTH
000
PLLN[3:0]
008
SCALE
37
25
PLL K 1
0
0
0
PLLK[23:18]
38
26
PLL K 2
PLLK[17:9]
093
39
27
PLL K 3
PLLK[8:0]
0E9
41
29
3D control
42
2A
OUT4 to ADC
43
2B
Beep control
00C
DEPTH3D
OUT4_2ADCVOL
OUT4_2
VMIDTOG OUT2DEL POBCTRL
000
DELEN
OUT1DEL
000
0
0
000
LNR
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BYPL2
BYPR2
RMIX
LMIX
0
0
0
0
DELEN2
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ADDR
B[15:9]
REGISTER
NAME
B8
B7
B6
B5
B4
B3
B2
B1
B0
VAL
DEC HEX
44
45
46
47
2C
2D
2E
2F
DEF’T
(HEX)
Input ctrl
Left INP PGA gain
ctrl
MICBVSEL
INPGAVU
Right INP PGA gain INPGAVU
ctrl
Left ADC Boost ctrl
PGA
0
R2_2
RIN2
RIP2
INPPGA
INPPGA
INPPGA
INPPGA
INPPGA
ZCL
MUTEL
INPPGA
INPPGA
ZCR
MUTER
0
L2_2
LIN2
LIP2
INPPGA
INPPGA
INPPGA
003
INPPGAVOLL
010
INPPGAVOLR
010
0
L2_2BOOSTVOL
0
000
100
0
R2_2BOOSTVOL
0
000
100
BOOSTL
48
49
50
51
52
53
54
55
56
30
31
32
33
34
35
36
37
38
Right ADC Boost
ctrl
BOOSTR
PGA
Output ctrl
HP_COM
Left mixer ctrl
LINE_COM
DACL2
DACR2
OUT4
OUT3
TSOP
RMIX
LMIX
ENDEL
ENDEL
CTRL
0
Right mixer ctrl
0
0
LOUT1 (HP)
volume ctrl
OUT1VU
ROUT1 (HP)
volume ctrl
OUT1VU
LOUT2 (SPK)
volume ctrl
OUT2VU
ROUT2 (SPK)
volume ctrl
OUT2VU
OUT3 mixer ctrl
0
LOUT1ZC
BYPLMIXVOL
0
BYPRMIXVOL
LOUT1
61
39
3D
OUT4 (MONO)
mixer ctrl
Bias Control
VROI
002
BYPL2
DACL2
001
LMIX
LMIX
BYPR2
DACR2
RMIX
RMIX
001
LOUT1VOL
039
ROUT1VOL
039
LOUT2VOL
039
ROUT2VOL
039
MUTE
ROUT1ZC
ROUT1
MUTE
LOUT2ZC
LOUT2
MUTE
ROUT2ZC
ROUT2
MUTE
0
OUT3
0
0
MUTE
57
TSDEN
0
BIASCUT
OUT4_
BYPL2
LMIX2
LDAC2
2OUT3
OUT3
OUT3
OUT3
OUT
OUT4
OUT4
LMIX2
LDAC2
BYPR2
RMIX2
RDAC2
3_2OUT4
MUTE
ATTN
OUT4
OUT4
OUT4
OUT4
OUT4
HALF
0
0
I_IPGA
BUFBIAS[1:0]
ADCBIAS[1:0]
HALFOP
001
001
000
BIAS
Table 59 WM8758B Register Map
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DIGITAL FILTER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
+/- 0.025dB
0
TYP
MAX
UNIT
ADC Filter
Passband
-6dB
0.454fs
0.5fs
Passband Ripple
+/- 0.025
Stopband
Stopband Attenuation
dB
0.546fs
f > 0.546fs
-60
Group Delay
dB
21/fs
ADC High Pass Filter
High Pass Filter Corner
Frequency
-3dB
3.7
-0.5dB
10.4
-0.1dB
21.6
Hz
DAC Filter
Passband
+/- 0.035dB
0
-6dB
0.454fs
0.5fs
Passband Ripple
+/-0.035
Stopband
Stopband Attenuation
Group Delay
dB
0.546fs
f > 0.546fs
-55
dB
29/fs
Table 60 Digital Filter Characteristics
TERMINOLOGY
1.
Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2.
Pass-band Ripple – any variation of the frequency response in the pass-band region
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DAC FILTER RESPONSES
3.05
0
3
-20
2.95
-40
Response (dB)
Response (dB)
20
-60
-80
-100
2.9
2.85
2.8
2.75
2.7
-120
2.65
-140
2.6
-160
0
0.5
1
1.5
2
0
2.5
0.05
0.1
0.15
Figure 43 DAC Digital Filter Frequency Response
(128xOSR)
0.25
0.3
0.35
0.4
0.45
0.5
0.45
0.5
Figure 44 DAC Digital Filter Ripple (128xOSR)
3.05
20
0
3
-20
2.95
-40
Response (dB)
Response (dB)
0.2
Frequency (fs)
Frequency (fs)
-60
-80
-100
2.9
2.85
2.8
2.75
-120
2.7
-140
2.65
2.6
-160
0
0.5
1
1.5
2
0
2.5
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Frequency (fs)
Frequency (fs)
Figure 45 DAC Digital Filter Frequency Response (64xOSR)
Figure 46 DAC Digital Filter Ripple (64xOSR)
ADC FILTER RESPONSES
0.2
0
0.15
0.1
Response (dB)
Response (dB)
-20
-40
-60
-80
0.05
0
-0.05
-0.1
-100
-0.15
-0.2
-120
0
0.5
1
1.5
2
Frequency (Fs)
Figure 47 ADC Digital Filter Frequency Response
w
2.5
3
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 48 ADC Digital Filter Ripple
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HIGHPASS FILTER
The WM8758B has a selectable digital highpass filter in the ADC filter path. This filter has two
st
modes, audio and applications. In audio mode the filter is a 1 order IIR with a cut-off of around
nd
3.7Hz. In applications mode the filter is a 2 order high pass filter with a selectable cut-off frequency.
5
0
-5
Response (dB)
-10
-15
-20
-25
-30
-35
-40
0
5
10
15
20
25
30
35
40
45
Frequency (Hz)
Figure 49 ADC Highpass Filter Response, HPFAPP=0
10
10
0
0
-10
-20
Response (dB)
Response (dB)
-10
-20
-30
-30
-40
-50
-40
-60
-50
-70
-80
-60
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
Frequency (Hz)
Frequency (Hz)
Figure 50 ADC Highpass Filter Responses (48kHz),
Figure 51 ADC Highpass Filter Responses (24kHz),
HPFAPP=1, all cut-off settings shown.
HPFAPP=1, all cut-off settings shown.
10
0
-10
Response (dB)
-20
-30
-40
-50
-60
-70
-80
-90
0
200
400
600
800
1000
1200
Frequency (Hz)
Figure 52 ADC Highpass Filter Responses (12kHz),
HPFAPP=1, all cut-off settings shown.
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5-BAND EQUALISER
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
The WM8758B has a 5-band equalizer which can be applied to either the ADC path or the DAC path.
The plots from Figure 53 to Figure 66 show the frequency responses of each filter with a sampling
frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and
secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each
filter.
0
-5
-5
-10
-15
-1
10
-10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 53 EQ Band 1 Low Frequency Shelf Filter Cut-offs
-15
-1
10
15
15
10
10
5
5
0
-5
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
0
-5
-10
-15
-1
10
10
Figure 54 EQ Band 1 Gains for Lowest Cut-off Frequency
Magnitude (dB)
Magnitude (dB)
0
-10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 55 EQ Band 2 – Peak Filter Centre Frequencies,
EQ2BW=0
-15
-1
10
Figure 56
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
EQ Band 2 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ2BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
Figure 57 EQ Band 2 – EQ2BW=0, EQ2BW=1
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Production Data
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
WM8758B
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
-15
-1
10
Figure 58 EQ Band 3 – Peak Filter Centre Frequencies, EQ3B Figure 59
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
EQ Band 3 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ3BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
Figure 60 EQ Band 3 – EQ3BW=0, EQ3BW=1
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84
WM8758B
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
Production Data
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
-15
-1
10
5
Figure 61 EQ Band 4 – Peak Filter Centre Frequencies, EQ3B Figure 62
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
EQ Band 4 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ4BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
Figure 63 EQ Band 4 – EQ3BW=0, EQ3BW=1
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 64 EQ Band 5 High Frequency Shelf Filter Cut-offs
w
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 65 EQ Band 5 Gains for Lowest Cut-off Frequency
PD, Rev 4.4, January 2012
85
WM8758B
Production Data
Figure 66 shows the result of having the gain set on more than one channel simultaneously. The
blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show
the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the
peak filters.
20
15
Magnitude (dB)
10
5
0
-5
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 66 Cumulative Frequency Boost/Cut
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Production Data
WM8758B
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 67 External Component Diagram
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WM8758B
Production Data
PACKAGE DIAGRAM
FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DM101.A
D
DETAIL 1
D2
32
25
L
1
24
4
EXPOSED
GROUND 6
PADDLE
INDEX AREA
(D/2 X E/2)
E2
17
E
8
2X
16
15
9
b
B
e
1
bbb M C A B
2X
aaa C
aaa C
TOP VIEW
BOTTOM VIEW
ccc C
A3
A
5
0.08 C
C
A1
SIDE VIEW
SEATING PLANE
M
M
45°
DETAIL 2
0.30
EXPOSED
GROUND
PADDLE
DETAIL 1
W
Exposed lead
T
A3
G
H
b
Half etch tie bar
DETAIL 2
Symbols
A
A1
A3
b
D
D2
E
E2
e
G
H
L
T
W
MIN
0.80
0
0.18
3.30
3.30
0.30
Dimensions (mm)
NOM
MAX
NOTE
0.90
1.00
0.02
0.05
0.203 REF
1
0.30
0.25
5.00 BSC
3.45
5.00 BSC
3.45
0.50 BSC
0.20
0.1
0.40
0.103
3.60
2
3.60
2
0.50
0.15
Tolerances of Form and Position
aaa
bbb
ccc
REF:
0.15
0.10
0.10
JEDEC, MO-220, VARIATION VHHD-5.
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC, MO-220, VARIATION VHHD-5.
3. ALL DIMENSIONS ARE IN MILLIMETRES.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002.
5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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Production Data
WM8758B
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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WM8758B
Production Data
REVISION HISTORY
DATE
REV
ORIGINATOR
CHANGES
12/12/11
4.4
JMacD
Order codes changed from WM8758BGEFL/V and WM8758BGEFL/RV to
WM8758CBGEFL/V and WM8758CBGEFL/RV to reflect change to copper wire
bonding.
12/12/11
4.4
JMacD
Package diagram changed to DM101.A.
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