WOLFSON WM8980GEFL/V

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WM8980
Stereo CODEC With Speaker Driver and Video Buffer
DESCRIPTION
FEATURES
The WM8980 is a low power, high quality stereo codec with
integrated video buffer designed for portable applications such
as Digital still camera or Digital Camcorder.
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The device integrates preamps for stereo differential mics, and
includes drivers for speakers, headphone and differential or
stereo line output. External component requirements are
reduced as no separate microphone or headphone amplifiers
are required.
An integrated video buffer is provided which has programmable
gain from 0-6dB, sync-tip clamp and a 3rd order input low pass
filter for signal re-construction.
Advanced on-chip digital signal processing includes a 5-band
equaliser, a mixed signal Automatic Level Control for the
microphone or line input through the ADC as well as a purely
digital limiter function for record or playback. Additional digital
filtering options are available in the ADC path, to cater for
application filtering such as ‘wind noise reduction’.
The WM8980 CODEC can operate as a master or a slave. An
internal PLL can generate all required audio clocks for the
Codec from common reference clock frequencies, such as
12MHz and 13MHz.
The WM8980 operates at analogue supply voltages from 2.5V
to 3.3V, although the digital core can operate at voltages down
to 1.62V to save power. The speaker outputs and OUT3/4 line
outputs can run from a 5V supply if increased output power is
required. Individual sections of the chip can also be powered
down under software control.
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
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Stereo Codec:
DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz)
ADC SNR 90dB, THD -80dB (‘A’ weighted @ 48kHz)
On-chip Headphone Driver with ‘capless’ option
- 40mW output power into 16Ω / 3.3V SPKVDD
0.9W output power into 8Ω BTL speaker / 5V SPKVDD
- Capable of driving piezo speakers
- Stereo speaker drive configuration
Mic Preamps:
Stereo Differential or mono microphone Interfaces
- Programmable preamp gain
- Psuedo differential inputs with common mode rejection
- Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for electret microphones
Other features:
Integrated 0-6dB video buffer with LPF filter and clamp.
Enhanced 3-D function for improved stereo separation
Digital playback limiter
5-band Equaliser (record or playback)
Programmable ADC High Pass Filter (wind noise reduction)
Programmable ADC Notch Filter
Aux inputs for stereo analog input signals or ‘beep’
On-chip PLL supporting 12, 13, 19.2MHz and other clocks
Low power, low voltage
- 2.5V to 3.6V (digital core: 1.62V to 3.6V)
- power consumption <30mW all-on with 2.5V supplies
6x6mm 40-pin QFN package
APPLICATIONS
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Stereo Camcorder or DSC
Product Preview, January 2005, Rev 1.6
Copyright 2005 Wolfson Microelectronics plc.
WM8980
Product Preview
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 9
POWER CONSUMPTION ....................................................................................10
SIGNAL TIMING REQUIREMENTS .....................................................................11
SYSTEM CLOCK TIMING ........................................................................................... 11
AUDIO INTERFACE TIMING – MASTER MODE ........................................................ 11
AUDIO INTERFACE TIMING – SLAVE MODE............................................................ 12
CONTROL INTERFACE TIMING – 3-WIRE MODE .................................................... 13
CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 14
DEVICE DESCRIPTION.......................................................................................15
INTRODUCTION ......................................................................................................... 15
INPUT SIGNAL PATH ................................................................................................. 17
ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 23
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 27
OUTPUT SIGNAL PATH ............................................................................................. 31
3D STEREO ENHANCEMENT .................................................................................... 37
ANALOGUE OUTPUTS............................................................................................... 38
VIDEO BUFFER .......................................................................................................... 53
DIGITAL AUDIO INTERFACES................................................................................... 54
AUDIO SAMPLE RATES ............................................................................................. 61
MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 61
GENERAL PURPOSE INPUT/OUTPUT...................................................................... 63
OUTPUT SWITCHING (JACK DETECT)..................................................................... 64
CONTROL INTERFACE.............................................................................................. 66
RESETTING THE CHIP .............................................................................................. 67
POWER SUPPLIES .................................................................................................... 67
POWER MANAGEMENT ............................................................................................ 68
REGISTER MAP...................................................................................................70
DIGITAL FILTER CHARACTERISTICS ...............................................................72
TERMINOLOGY .......................................................................................................... 72
DAC FILTER RESPONSES......................................................................................... 73
ADC FILTER RESPONSES......................................................................................... 73
HIGHPASS FILTER..................................................................................................... 74
5-BAND EQUALISER .................................................................................................. 75
APPLICATION INFORMATION............................................................................79
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 79
PACKAGE DIAGRAM ..........................................................................................80
IMPORTANT NOTICE ..........................................................................................81
ADDRESS: .................................................................................................................. 81
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PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
WM8980GEFL/V
-25°C to +85°C
40-pin QFN (6 x 6 mm)
(lead free)
MSL3
260oC
WM8980GEFL/RV
-25°C to +85°C
40-pin QFN (6 x 6 mm)
(lead free, tape and reel)
MSL3
260oC
Note:
Reel quantity = 3,500
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PIN DESCRIPTION
PIN
NAME
TYPE
1
L2/GPIO2
Analogue input
DESCRIPTION
2
RIP
Analogue input
Right Mic Pre-amp positive input
3
RIN
Analogue input
Right Mic Pre-amp negative input
4
R2/GPIO3
Analogue input
5
VBGND
Supply
Left channel line input/secondary mic pre-amp positive input/GPIO pin
Right channel line input/secondary mic pre-amp positive input/GPIO pin
Video buffer ground pin
6
VBIN
Analogue input
7
VBREF
Analogue output
Video buffer reference resistor pin
8
VBOUT
Analogue output
Video buffer output
9
VBVDD
Supply
10
NC
Not internally
connected
11
LRC
Digital Input / Output
DAC and ADC Sample Rate Clock
12
BCLK
Digital Input / Output
Digital Audio Port Clock
13
ADCDAT
Digital Output
14
DACDAT
Digital Input
15
MCLK
Digital Input
16
DGND
Supply
Digital ground
17
DCVDD
Supply
Digital core logic supply
18
DBVDD
Supply
19
CSB/GPIO1
Digital Input / Output
20
SCLK
Digital Input
21
SDIN
Digital Input / Output
22
MODE
Digital Input
23
GPIO4
Digital input/output
24
NC
Not internally
connected
Video buffer signal input
Video buffer analogue supply
ADC Digital Audio Data Output
DAC Digital Audio Data Input
Master Clock Input
Digital buffer (I/O) supply
3-Wire MPU Chip Select / General purpose input/output 1
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
3-Wire MPU Data Input / 2-Wire MPU Data Input
Control Interface Selection
General purpose input/output 4
25
AUXL
Analogue input
26
AUXR
Analogue input
27
OUT4
Analogue Output
Buffered midrail Headphone pseudo-ground, or Right line output or MONO
mix output
28
OUT3
Analogue Output
Buffered midrail Headphone pseudo-ground, or Left line output
ROUT2
Analogue Output
Second right output, or BTL speaker driver negative output
SPKGND
Supply
Speaker ground (feeds speaker amp and OUT3/OUT4)
31
LOUT2
Analogue Output
Second left output, or BTL speaker driver positive output
32
SPKVDD
Supply
33
VMID
Reference
29
30
Left Auxillary input
Right Auxillary input
Speaker supply (feed speaker amp only)
Decoupling for ADC and DAC reference voltage
34
AGND
Supply
35
ROUT1
Analogue Output
Headphone Output Right
Analogue ground (feeds ADC and DAC)
36
LOUT1
Analogue Output
Headphone Output Left
37
AVDD
Supply
38
MICBIAS
Analogue Output
39
LIP
Analogue input
Left Mic Pre-amp positive input
40
LIN
Analogue input
Left Mic Pre-amp negative input
Analogue supply (feeds ADC and DAC)
Microphone Bias
Note:
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
DBVDD, DCVDD, AVDD, VBVDD supply voltages
SPKVDD supply voltage
MIN
MAX
-0.3V
+3.63V
-0.3V
+7V
Voltage range digital inputs
DGND -0.3V
DVDD +0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
Operating temperature range, TA
-25°C
+85°C
Storage temperature after soldering
-65°C
+150°C
Notes
1.
Analogue and digital grounds must always be within 0.3V of each other.
2.
All digital and analogue supplies are completely independent from each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Digital supply range (Core)
DCVDD
1.62
3.6
V
Digital supply range (Buffer)
DBVDD
1.8
3.6
V
V
Analogue core supply range
Video buffer supply range
Analogue output supply range
Ground
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TEST
CONDITIONS
MIN
TYP
MAX
UNIT
AVDD
2.5
3.6
VBVDD
2.5
3.6
V
SPKVDD
2.5
5.5
V
DGND,AGND,
SPKGND,VBGND
0
V
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ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2)
Full-scale Input Signal Level –
note this changes with AVDD
(Note 1)
VINFS
Mic PGA equivalent input noise
At 35.25dB
gain
Input resistance
Recommended coupling cap
PGABOOST = 0dB
INPPGAVOL = 0dB
1.0
0
Vrms
dBV
TBD
uV
kΩ
RMICIN
Gain set to 35.25dB
1.6
RMICIN
Gain set to 0dB
47
kΩ
RMICIN
Gain set to -12dB
75
kΩ
RMICIP
MICP2INPPGA = 1
94
kΩ
RMICIP
MICP2INPPGA = 0
TBD
kΩ
CMICIN
10
pF
CCOUP
220
pF
MIC Programmable Gain Amplifier (PGA)
Programmable Gain
-12
Programmable Gain Step Size
Guaranteed monotonic
35.25
dB
0.75
dB
TBD
dB
Boost disabled
0
dB
Boost enabled
20
Mute Attenuation
Selectable Input Gain Boost (0/+20dB)
Gain Boost on PGA input
Gain range from AUXL/R or
L/R2 input to boost/mixer
-12
Gain step size to boost/mixer
dB
+6
dB
3
dB
AVDD/3.3
0
Vrms
dBV
Auxilliary Analogue Inputs (AUXL, AUXR)
Full-scale Input Signal Level
(0dB) – note this changes with
AVDD
Input Resistance
(Note 2)
Input Capacitance
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VINFS
RAUXINLMIN
Left Input boost and mixer
enabled, at max gain
4.3
kΩ
RAUXINLTYP
Left Input boost and mixer
enabled, at 0dB gain
8.6
kΩ
RAUXINLMAX
Left Input boost and mixer
enabled, at min gain
39.1
kΩ
RAUXINRMIN
ight Input boost, mixer and
beep enabled, at max gain
3
kΩ
RAUXINRTYP
ight Input boost, mixer and
beep enabled, at 0dB gain
6
kΩ
RAUXINRMAX
ight Input boost, mixer and
beep enabled, at min gain
29
kΩ
10
pF
CMICIN
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Test Conditions
DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Automatic Level Control (ALC)
Target Record Level
-28.5
-6
Programmable gain
-12
35.25
Gain Hold Time (Note 3,5)
tHOLD
MCLK = 12.288MHz
(Note 3)
0, 2.67, 5.33, 10.67, … , 43691
(time doubles with each step)
ms
Gain Ramp-Up (Decay) Time
(Note 4,5)
tDCY
ALCMODE=0 (ALC),
MCLK=12.288MHz
(Note 3)
3.3, 6.6, 13.1, … , 3360
(time doubles with each step)
ms
ALCMODE=1 (limiter),
MCLK=12.288MHz
(Note 3)
0.73, 1.45, 2.91, … , 744
(time doubles with each step)
ALCMODE=0 (ALC),
MCLK=12.288MHz
(Note 3)
0.83, 1.66, 3.33, … , 852
(time doubles with each step)
ALCMODE=1 (limiter),
MCLK=12.288MHz
(Note 3)
0.18, 0.36, 0.73, … , 186
(time doubles with each step)
Gain Ramp-Down (Attack) Time
(Note 4,5)
tATK
Mute Attenuation
ms
TBD
dB
A-weighted, 0dB gain
90
dB
full-scale, 0dB gain
-80
dB
1kHz input signal
100
dB
Analogue to Digital Converter (ADC)
Signal to Noise Ratio (Note 6,7)
Total Harmonic Distortion
(Note 8)
Channel Separation (Note 9)
Digital to Analogue Converter (DAC) to Line-Out (LOUT1, ROUT1 with 10kΩ
Ω / 50pF load)
Full-scale output
PGA gains set to 0dB,
OUT34BOOST=0
AVDD/3.3
PGA gains set to 0dB,
OUT34BOOST=1
1.5x
(AVDD/3.3)
Signal to Noise Ratio (Note 6, 7)
SNR
A-weighted
Total Harmonic Distortion
(Note 8)
THD
RL = 10kΩ
full-scale signal
Channel Separation (Note 9)
1kHz signal
TBD
80
Vrms
98
dB
-84
dB
100
dB
Output Mixers (LMX1, RMX1)
PGA gain range into mixer
-15
PGA gain step into mixer
0
+6
3
dB
dB
Analogue Outputs (LOUT1, ROUT1, LOUT2, ROUT2)
Programmable Gain range
-57
Programmable Gain step size
Mute attenuation
0
+6
dB
Monotonic
1
dB
1kHz, full scale signal
85
dB
AVDD/3.3
Vrms
93
dB
Headphone Output (LOUT1, ROUT1 with 32Ω
Ω load)
0dB full scale output voltage
Signal to Noise Ratio
SNR
A-weighted
Total Harmonic Distortion
THD
RL = 16Ω, Po=20mW
AVDD=3.3V
0.008
-81
%
dB
RL = 32 Ω, Po=20mW
AVDD=3.3V
0.007
- 83
%
dB
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TBD
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Test Conditions
DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Speaker Output (LOUT2, ROUT2 with 8Ω
Ω bridge tied load, INVROUT2=1)
Full scale output voltage, 0dB
gain. (Note 10)
Output Power
Total Harmonic Distortion
Signal to Noise Ratio
PO
THD
SNR
SPKRBOOST=0
SPKVDD/3.3
SPKRBOOST=1
(SPKVDD/3.3)*1.5
Vrms
Output power is very closely correlated with THD; see below
PO =180mW, RL = 8Ω,
SPKVDD=3.3V
0.3
-50
%
dB
PO =400mW, RL = 8Ω,
SPKVDD=3.3V
1.0
-40
%
dB
PO =360mW, RL = 8Ω,
SPKVDD=5V
0.3
-50
%
dB
PO =800mW, RL = 8Ω,
SPKVDD=5V
1
-40
%
dB
SPKVDD=3.3V,
RL = 8Ω
90
dB
SPKVDD=5V,
RL = 8Ω
90
dB
50
dB
OUT3BOOST=0/
OUT4BOOST=0
SPKVDD/3.3
Vrms
OUT3BOOST=1
OUT4BOOST=1
(SPKVDD/3.3)*1.5
Vrms
Power Supply Rejection Ratio
OUT3/OUT4 outputs (with 10kΩ
Ω / 50pF load)
Full-scale output voltage, 0dB
gain (Note 10)
Signal to Noise Ratio (Note 6,7)
SNR
A-weighted
Total Harmonic Distortion
(Note 8)
THD
RL = 10 kΩ
full-scale signal
Channel Separation (Note 9)
1kHz signal
TBD
80
98
dB
-84
dB
100
dB
Microphone Bias
Bias Voltage
VMICBIAS
Bias Current Source
IMICBIAS
Output Noise Voltage
Vn
MBVSEL=0
0.9*AVDD
V
MBVSEL=1
0.75*AVDD
V
1K to 20kHz
15
3
mA
nV/√Hz
Video Buffer
3rd order
Low pass filter order
LPF -3dB cutoff
10
MHz
LPF gain flat to within 0.1dB
5.3
MHz
Maximum output voltage swing
Vom
f=100kHz, THD=1%
1.25
Vp-p
Programmable Voltage Gain
Av
Differential gain
DG
Vin=1Vp-p
1
%
Differential phase
DP
Vin=1Vp-p
1
Deg
+60
dB
Signal to Noise Ratio
0
VSNR
6
dB
Digital Input / Output
Input HIGH Level
VIH
Input LOW Level
VIL
Output HIGH Level
VOH
IOL=1mA
Output LOW Level
VOL
IOH-1mA
0.7×DBVDD
V
0.3×DBVDD
V
0.1xDBVDD
V
0.9×DBVDD
V
Input capacitance
TBD
pF
Input leakage
TBD
pA
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WM8980
TERMINOLOGY
1.
2.
3.
4.
5.
Input level to RIP and LIP in pseudo-differential configurations is limited to a maximum of -3dB or THD+N
performance will be reduced.
Note when BEEP path is not enabled then AUXL and AUXR have the same input impedances.
Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does
not apply to ramping down the gain when the signal is too loud, which happens without a delay.
Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to sweep across 90% of its gain range.
All hold, ramp-up and ramp-down times scale proportionally with MCLK
6.
Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
7.
Dynamic range (dB) – DR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
8.
9.
THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
10. The maximum output voltage can be limited by the speaker power supply. If OUT3BOOST, OUT4BOOST or
SPKRBOOST is set then SPKVDD should be 1.5xAVDD to prevent clipping taking place in the output stage (when
PGA gains are set to 0dB).
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POWER CONSUMPTION
Estimated current consumption for typical scenarios are shown below.
For more information on current consumption of individual blocks, see "Estimated Supply Currents"
section.
Unless otherwise specified, all supply voltages are 3.3V.
DCVDD
VBVDD
Off
MODE
0
AVDD
0
0
UNITS
Sleep (VREF maintained)
0.1
0
0
mA
Stereo Record (8kHz,
PLL enabled)
8.1
0.8
0
mA
mA
Stereo HP Playback (44.1kHz, PLL enabled)
6.6
4.3
0
mA
Stereo HP Playback (44.1kHz, PLL enabled,
Video Buffer enabled)
6.6
4.3
1.0
mA
Table 1 Power Consumption
Notes:
1.
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DBVDD Supply current is not shown, as this is determined by loading on the digital I/O pins.
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK =
256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
TMCLKY
Tbd
MCLK duty cycle
TMCLKDS
60:40
ns
40:60
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
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Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V,
MCLK=256fs, 24-bit data, unless otherwise stated.
DGND=AGND=SPKGND=0V,
PARAMETER
SYMBOL
TA=+25oC,
MIN
Slave
TYP
Mode,
fs=48kHz,
MAX
UNIT
Audio Data Input Timing Information
FRAME propagation delay from BCLK falling edge
tDL
10
ns
ADCDAT propagation delay from BCLK falling edge
tDDA
10
ns
DACDAT setup time to BCLK rising edge
tDST
10
ns
DACDAT hold time from BCLK rising edge
tDHT
10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz,
MCLK= 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
FRAME set-up time to BCLK rising edge
tLRSU
10
ns
FRAME hold time from BCLK rising edge
tLRH
10
ns
DACDAT hold time from BCLK rising edge
tDH
10
ADCDAT propagation delay from BCLK falling edge
tDD
Audio Data Input Timing Information
ns
10
ns
Note:
BCLK period should always be greater than or equal to MCLK period.
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CONTROL INTERFACE TIMING – 3-WIRE MODE
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
o
DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA=+25 C, Slave Mode, fs=48kHz,
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
80
SCLK pulse cycle time
tSCY
200
ns
SCLK pulse width low
tSCL
80
ns
SCLK pulse width high
tSCH
80
ns
SDIN to SCLK set-up time
tDSU
40
ns
SCLK to SDIN hold time
tDHO
40
ns
CSB pulse width low
tCSL
40
ns
CSB pulse width high
tCSH
40
ns
CSB rising to SCLK rising
tCSS
40
ns
tps
0
Pulse width of spikes that will be suppressed
w
ns
5
ns
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CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t1
t9
t7
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V,
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
TA=+25oC,
Slave
TYP
Mode,
fs=48kHz,
MAX
UNIT
400
kHz
SYMBOL
MIN
SCLK Low Pulse-Width
t1
1.3
us
SCLK High Pulse-Width
t2
600
ns
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
SDIN, SCLK Rise Time
t6
SDIN, SCLK Fall Time
t7
Setup Time (Stop Condition)
t8
Data Hold Time
t9
Pulse width of spikes that will be suppressed
tps
Program Register Input Information
SCLK Frequency
w
0
ns
300
ns
300
ns
900
ns
5
ns
600
0
ns
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DEVICE DESCRIPTION
INTRODUCTION
The WM8980 is a low power audio codec combining a high quality stereo audio DAC and ADC, with
flexible line and microphone input and output processing. Applications for this device include stereo
digital camcorders, and digital still cameras with either mono or stereo, audio and video, record and
playback capability. The integrated video buffer makes the device suitable for driving both audio
and video signals directly to a television or VCR.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as
follows:
MICROPHONE INPUTS
Two pairs of stereo microphone inputs are provided, allowing for a pair of stereo microphones to be
pseudo-differentially connected, with user defined gain using internal resistors. The provision of the
common mode input pin for each stereo input allows for rejection of common mode noise on the
microphone inputs (level depends on gain setting chosen). A microphone bias is output from the chip
which can be used to bias both microphones. The signal routing can be configured to allow manual
adjustment of mic levels, or indeed to allow the ALC loop to control the level of mic signal that is
transmitted.
Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually
or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the
recording volume constant.
LINE INPUTS (AUXL, AUXR)
The inputs, AUXL and AUXR, can be used as a stereo line input or as an input for warning tones (or
‘beeps’) etc. These inputs can be summed into the record paths, along with the microphone preamp
outputs, so allowing for mixing of audio with ‘backing music’ etc as required.
ADC
The stereo ADC uses a multi-bit high-order oversampling architecture to deliver optimum
performance with low power consumption.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type
applications, including MP3 players and portable disc players of all types.
OUTPUT MIXERS
Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo
headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs
allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are
provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to
allow for all possible signal combinations. The output buffers can be configured in several ways,
allowing support of up to three sets of external transducers; ie stereo headphone, BTL speaker, and
BTL earpiece may be connected simultaneously. Thermal implications should be considered before
simultaneous full power operation of all outputs is attempted.
Alternatively, if a speaker output is not required, the LOUT2 and ROUT2 pins might be used as a
stereo headphone driver, (disable output invert buffer on ROUT2). In that case two sets of
headphones might be driven, or the LOUT2 and ROUT2 pins used as a line output driver.
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OUT3 and OUT4 can be configured to provide an additional stereo lineout from the output of the
DACs, the mixers or the input microphone boost stages. Alternatively OUT4 can be configured as a
mono mix of left and right DACs or mixers, or simply a buffered version of the chip midrail reference
voltage. OUT3 can also be configured as a buffered VMID output. This voltage may then be used as
a headphone ‘pseudo ground’ allowing removal of the large AC coupling capacitors often used in the
output path.
AUDIO INTERFACES
The WM8980 has a standard audio interface, to support the transmission of stereo data to and from
the chip. This interface is a 3 wire standard audio interface which supports a number of audio data
formats including I2S, DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words
are transmitted), MSB-First, left justified and MSB-First, right justified, and can operate in master or
slave modes.
CONTROL INTERFACES
To allow full software control over all its features, the WM8980 offers a choice of 2 or 3 wire MPU
control interface. It is fully compatible and an ideal partner for a wide range of industry standard
microprocessors, controllers and DSPs.
Selection between the modes is via the MODE pin. In 2 wire mode the address of the device is fixed
as 0011010.
CLOCKING SCHEMES
WM8980 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to
the DAC and ADC.
A PLL is included which may be used to generate these clocks in the event that they are not
available from the system controller. This PLL uses an input clock, typically the 12MHz USB or ilink
clock, to generate high quality audio clocks. If this PLL is not required for generation of these clocks,
it can be reconfigured to generate alternative clocks which may then be output on the GPIO pins and
used elsewhere in the system.
VIDEO BUFFER
The WM8980 incorporates a current mode output video buffer with an input 3rd order Low Pass Filter
(LPF) and clamp. The gain through this buffer can be programmed as 0dB or 6dB via the control
interface. The current mode output means that the signal swing seen at the output of the buffer will
be the same as that at the connection to the receiving equipment (e.g. a TV). Note that the input to
the receiver should be AC coupled and terminated to 75Ω, as is standard, for best performance.
POWER CONTROL
The design of the WM8980 has given much attention to power consumption without compromising
performance. It operates at very low voltages, and includes the ability to power off any unused parts
of the circuitry under software control, and includes standby and power off modes.
OPERATION SCENARIOS
Flexibility in the design of the WM8980 allows for a wide range of operational scenarios, some of
which are proposed below:
Stereo Camcorder; The provision of two stereo microphone preamplifiers, allows support for both
internal and external microphones. All drivers for speaker, headphone and line output connections
are integrated. The selectable ‘application filters’ after the ADC provide for features such as ‘wind
noise’ reduction, or mechanical noise reducing filters. The integrated video buffer allows direct
connection to a TV or VCR for both video and audio (via line outputs).
Stereo Digital still camera recording; Support for digital stereo video with audio recording is similar to
the camcorder case. But additionally if the DSC supports MP3 playback, and perhaps recording, the
ability of the ADCs to support full 48ks/s high quality stereo recording increases device flexibility.
The integrated video buffer allows direct connection to the TV for display of moving and still images.
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Mono Digital still camera; Full control over device functionality, and power control is provided,
allowing for the case of mono DSC recording, when half of the ADC and mic and line functionality
may be disabled to save power. In the mono case, the single ADC channel of audio data is sent out
over both Left and Right channels of the audio interface when normal I2S type interface format is
used. In the case where DSP mode is used, and mono data is being sent, only the signal channel of
mono data is sent. The integrated video buffer allows direct connection to the TV for display of
moving and still images.
ANALOG FM TUNER SUPPORT
An analog stereo FM tuner might be connected to the Line inputs of WM8980, and the stereo signal
listened to via headphones, or recorded, simultaneously if required.
INPUT SIGNAL PATH
The WM8980 has a number of flexible analogue inputs. There are two input channels, Left and
Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into
the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to
accommodate single-ended, differential or dual differential microphones. There are two auxiliary
input pins which can be fed into to the input boost/mix stage as well as driving into the output path.
A bypass path exists from the output of the boost/mix stage into the output left/right mixers.
MICROPHONE INPUTS
The WM8980 can accommodate a variety of microphone configurations including single ended and
differential inputs. The inputs to the left differential input PGA are LIN, LIP and L2. The inputs to the
right differential input PGA are RIN, RIP and R2.
In single-ended microphone input configuration the microphone signal should be input to LIN or RIN
and the internal NOR gate configured to clamp the non-inverting input of the input PGA to VMID.
Figure 6 Microphone Input PGA Circuit
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The input PGAs are enabled by the IPPGAENL/R register bits.
REGISTER
ADDRESS
BIT
R2
Power
Management
2
LABEL
DEFAULT
DESCRIPTION
2
INPPGAENL
0
Left channel input PGA enable
0 = disabled
1 = enabled
3
INPPGAENR
0
Right channel input PGA enable
0 = disabled
1 = enabled
Table 2 Input PGA Enable Register Settings
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R44
Input
Control
0
LIP2INPPGA
1
Connect LIP pin to left channel input PGA
amplifier positive terminal.
0 = LIP not connected to input PGA
1 = input PGA amplifier positive terminal
connected to LIP (constant input
impedance)
1
LIN2INPPGA
1
Connect LIN pin to left channel input PGA
negative terminal.
0=LIN not connected to input PGA
1=LIN connected to input PGA amplifier
negative terminal.
2
L2_2INPPGA
0
Connect L2 pin to left channel input PGA
positive terminal.
0=L2 not connected to input PGA
1=L2 connected to input PGA amplifier
positive terminal (constant input
impedance).
4
RIP2INPPGA
1
Connect RIP pin to right channel input
PGA amplifier positive terminal.
0 = RIP not connected to input PGA
1 = right channel input PGA amplifier
positive terminal connected to RIP
(constant input impedance)
5
RIN2INPPGA
1
Connect RIN pin to right channel input
PGA negative terminal.
0=RIN not connected to input PGA
1=RIN connected to right channel input
PGA amplifier negative terminal.
6
R2_2INPPGA
0
Connect R2 pin to right channel input PGA
positive terminal.
0=R2 not connected to input PGA
1=R2 connected to input PGA amplifier
positive terminal (constant input
impedance).
Table 3 Input PGA Control
INPUT PGA VOLUME CONTROLS
The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain
from the LIN/RIN input to the PGA output and from the L2/R2 amplifier to the PGA output are always
common and controlled by the register bits INPPGAVOLL/R[5:0]. These register bits also effect the
LIP pin when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1, the RIP pin when RIP2INPPGA=1
and the L2 pin when L2_2INPPGA=1.
When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled
automatically and the INPPGAVOLL/R bits should not be used.
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REGISTER
ADDRESS
BIT
R45
Left channel
input PGA
volume
control
5:0
INPPGAVOLL
010000
Left channel input PGA volume
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = 35.25dB
6
INPPGAMUTEL
0
Mute control for left channel input PGA:
0=Input PGA not muted, normal
operation
1=Input PGA muted (and disconnected
from the following input BOOST stage).
7
INPPGAZCL
0
Left channel input PGA zero cross
enable:
0=Update gain when gain register
changes
1=Update gain on 1st zero cross after
gain register write.
8
INPPGAUPDATE
Not
latched
INPPGAVOLL and INPPGAVOLR
volume do not update until a 1 is written
to INPGAUPDATE (in reg 45 or 46)
5:0
INPPGAVOLR
010000
Right channel input PGA volume
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = +35.25dB
6
INPPGAMUTER
0
Mute control for right channel input
PGA:
0=Input PGA not muted, normal
operation
1=Input PGA muted (and disconnected
from the following input BOOST stage).
7
INPPGAZCR
0
Right channel input PGA zero cross
enable:
0=Update gain when gain register
changes
1=Update gain on 1st zero cross after
gain register write.
8
INPPGAUPDATE
Not
latched
INPPGAVOLL and INPPGAVOLR
volume do not update until a 1 is written
to INPGAUPDATE (in reg 45 or 46)
8:7
ALCSEL
00
ALC function select:
00=ALC off
01=ALC right only
10=ALC left only
11=ALC both on
R46
Right
channel
input PGA
volume
control
R32
ALC control
1
LABEL
DEFAULT
DESCRIPTION
Table 4 Input PGA Volume Control
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AUXILLIARY INPUTS
There are two auxilliary inputs, AUXL and AUXR which can be used for a variety of purposes such
as stereo line inputs or as a ‘beep’ input signal to be mixed with the outputs.
The AUXL/R inputs can be used as a line input to the input BOOST stage which has gain adjust of 12dB to +6dB in 3dB steps (plus off). See the INPUT BOOST section for further details.
The AUXL/R inputs can also be mixed into the output channel mixers, with a gain of -15dB to +6dB
plus off.
In addition the AUXR input can be summed into the Right speaker output path (ROUT2) with a gain
adjust of -15 to +6dB. This allows a ‘beep’ input to be output on the speaker outputs only without
affecting the headphone or lineout signals.
INPUT BOOST
Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST
circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the
L2/R2 input pin (can be used as a line input, bypassing the input PGA). These three inputs can be
mixed together and have individual gain boost/adjust as shown in Figure 7.
Figure 7 Input Boost Stage
The input PGA paths can have a +20dB boost (PGABOOSTL/R=1) , a 0dB pass through
(PGABOOSTL/R=0) or be completely isolated from the input boost circuit (INPPGAMUTEL/R=1).
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R47
Left Input
BOOST
control
8
PGABOOSTL
1
Boost enable for left channel input
PGA:
0 = PGA output has +0dB gain
through input BOOST stage.
1 = PGA output has +20dB gain
through input BOOST stage.
R48
Right Input
BOOST
control
8
PGABOOSTR
1
Boost enable for right channel input
PGA:
0 = PGA output has +0dB gain
through input BOOST stage.
1 = PGA output has +20dB gain
through input BOOST stage.
Table 5 Input BOOST Stage Control
The Auxilliary amplifier path to the BOOST stages is controlled by the AUXL2BOOSTVOL[2:0] and
AUXR2BOOSTVOL[2:0] register bits. When AUXL2BOOSTVOL/AUXR2BOOSTVOL=000 this path
is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in
3dB steps from -12dB to +6dB.
The L2/R2 path to the BOOST stage is controlled by the LIP2BOOSTVOL[2:0] and the
RIP2BOOSTVOL[2:0] register bits. When L2_2BOOSTVOL/R2_2BOOSTVOL=000 the L2/R2 input
pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain
in 3dB steps from -12dB to +6dB.
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REGISTER
ADDRESS
R47
Left channel
Input BOOST
control
R48
Right channel
Input BOOST
control
BIT
LABEL
DEFAULT
DESCRIPTION
2:0
AUXL2BOOSTVOL
000
Controls the auxilliary amplifer to
the left channel input boost stage:
000=Path disabled (disconnected)
001=-12dB gain through boost
stage
010=-9dB gain through boost
stage
…
111=+6dB gain through boost
stage
6:4
L2_2BOOSTVOL
000
Controls the L2 pin to the left
channel input boost stage:
000=Path disabled (disconnected)
001=-12dB gain through boost
stage
010=-9dB gain through boost
stage
…
111=+6dB gain through boost
stage
2:0
AUXR2BOOSTVOL
000
Controls the auxilliary amplifer to
the right channel input boost
stage:
000=Path disabled (disconnected)
001=-12dB gain through boost
stage
010=-9dB gain through boost
stage
…
111=+6dB gain through boost
stage
6:4
R2_2BOOSTVOL
000
Controls the R2 pin to the right
channel input boost stage:
000=Path disabled (disconnected)
001=-12dB gain through boost
stage
010=-9dB gain through boost
stage
…
111=+6dB gain through boost
stage
Table 6 Input BOOST Stage Control
The BOOST stage is enabled under control of the BOOSTEN register bit.
REGISTER
ADDRESS
R2
Power
management
2
BIT
LABEL
DEFAULT
DESCRIPTION
4
BOOSTENL
0
Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
5
BOOSTENR
0
Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Table 7 Input BOOST Enable Control
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MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. Refer to the Applications
Information section for recommended external components. The MICBIAS voltage can be altered via
the MBVSEL register bit.
When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1,
MICBIAS=0.6*AVDD. The output can be enabled or disabled using the MICBEN control bit.
REGISTER
ADDRESS
BIT
R1
Power
management 1
4
LABEL
DEFAULT
MICBEN
0
DESCRIPTION
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Table 8 Microphone Bias Enable Control
REGISTER
ADDRESS
R44
Input control
BIT
8
LABEL
MBVSEL
DEFAULT
0
DESCRIPTION
Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.6 * AVDD
Table 9 Microphone Bias Voltage Control
The internal MICBIAS circuitry is shown in Figure 8. Note that the maximum source current
capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit
the MICBIAS current to 3mA.
VMID
MB
internal
resistor
internal
resistor
MBVSEL=0
MICBIAS
= 1.8 x VMID
= 0.9 X AVDD
MBVSEL=1
MICBIAS
= 1.2 x VMID
= 0.6 X AVDD
AGND
Figure 8 Microphone Bias Schematic
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8980 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full
Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms.
Any voltage greater than full scale may overload the ADC and cause distortion.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The
digital filter path for each ADC channel is illustrated in Figure 9.
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Figure 9 ADC Digital Filter Path
The ADCs are enabled by the ADCENL/R register bit.
REGISTER
ADDRESS
R2
Power
management 2
BIT
LABEL
DEFAULT
DESCRIPTION
0
ADCENL
0
Enable ADC left channel:
0 = ADC disabled
1 = ADC enabled
1
ADCENR
0
Enable ADC right channel:
0 = ADC disabled
1 = ADC enabled
Table 10 ADC Enable Control
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the
ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
REGISTER
ADDRESS
R14
ADC Control
BIT
LABEL
DEFAULT
DESCRIPTION
0
ADCLPOL
0
ADC left channel polarity adjust:
0=normal
1=inverted
1
ADCRPOL
0
ADC right channel polarity adjust:
0=normal
1=inverted
3
ADCOSR
0
ADC oversample rate select:
0=64x (lower power)
1=128x (best performance)
Table 11 ADC Control
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two
modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off
frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off
frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown
in Table 13.
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REGISTER
ADDRESS
BIT
R14
ADC Control
LABEL
DEFAULT
8
HPFEN
1
7
HPFAPP
0
6:4
HPFCUT
000
DESCRIPTION
High Pass Filter Enable
0=disabled
1=enabled
Select audio mode or application mode
0=Audio mode (1st order, fc = ~3.7Hz)
1=Application mode (2nd order, fc =
HPFCUT)
Application mode cut-off frequency
See Table 13 for details.
Table 12 ADC Enable Control
FS (KHZ)
HPFCUT
SR=101/100
SR=011/010
8
11.025
12
000
82
113
001
102
141
010
131
011
SR=001/000
16
22.05
24
32
44.1
48
122
82
113
153
102
141
122
82
113
122
153
102
141
180
156
131
153
180
156
131
180
163
225
245
156
163
225
245
163
225
100
204
281
245
306
204
281
306
204
281
101
261
306
360
392
261
360
392
261
360
110
392
327
450
490
327
450
490
327
450
111
490
408
563
612
408
563
612
408
563
612
Table 13 High Pass Filter Cut-off Frequencies (HPFAPP=1)
Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits
are set correctly for the actual sample rate as shown in Table 13.
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PROGRAMMABLE NOTCH FILTER
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth,
programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits
NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup
there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
6:0
NFA0[6:0]
0
Notch Filter a0 coefficient, bits [6:0]
7
NFEN
0
Notch filter enable:
0=Disabled
8
NFU
0
Notch filter update. The notch filter
values used internally only update
R28
Notch Filter 2
6:0
NFA0[13:7]
0
Notch Filter a0 coefficient, bits [13:7]
8
NFU
0
Notch filter update. The notch filter
values used internally only update
R29
Notch Filter 3
6:0
NFA1[6:0]
0
Notch Filter a1 coefficient, bits [6:0]
8
NFU
0
Notch filter update. The notch filter
values used internally only update
R30
Notch Filter 4
0-6
NFA1[13:7]
0
Notch Filter a1 coefficient, bits [13:7]
8
NFU
0
Notch filter update. The notch filter
R27
Notch Filter 1
1=Enabled
when one of the NFU bits is set high.
when one of the NFU bits is set high.
when one of the NFU bits is set high.
values used internally only update
when one of the NFU bits is set high.
Table 14 Notch Filter Function
The coefficients are calculated as follows:
a0 =
1 − tan( wb / 2)
1 + tan( wb / 2)
a1 = −(1 + a0 ) cos(w0 )
Where:
w0 = 2πf c / f s
wb = 2πf b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz
The actual register values can be determined from the coefficients as follows:
NFA0 = -a0 x 213
NFA1 = -a1 x 212
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps.
The gain for a given eight-bit code X is given by:
0.5 × (G-255) dB for 1 ≤ G ≤ 255;
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REGISTER
ADDRESS
R15
Left channel
ADC Digital
Volume
R16
Right channel
ADC Digital
Volume
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
ADCVOLL
[7:0]
11111111
( 0dB )
Left ADC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
8
ADCVU
Not
latched
ADC left and ADC right volume do not
update until a 1 is written to ADCVU (in
reg 16 or 17)
7:0
ADCVOLR
[7:0]
11111111
( 0dB )
Right ADC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
8
ADCVU
Not
latched
ADC left and ADC right volume do not
update until a 1 is written to ADCVU (in
reg 16 or 17)
Table 15 ADC Digital Volume Control
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
The WM8980 has an automatic PGA gain control circuit, which can function as an input peak limiter
or as an automatic level control (ALC).
In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal
goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too
large for the input range of the ADC. When the signal returns to a level below the threshold, the
PGA gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain
above its static level.
Figure 10 Input Peak Limiter Operation
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In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective
of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal
level at the ADC input remains constant. A digital peak detector monitors the ADC output and
changes the PGA gain if necessary.
Figure 11 ALC Operation
The ALC/Limiter function is enabled by setting the register bit ALCSEL. When enabled, the
recording volume can be programmed between –6dB and –28.5dB (relative to ADC full scale) using
the ALCLVL register bits. An upper limit for the PGA gain can be imposed by setting the ALCMAX
control bits and a lower limit for the PGA gain can be imposed by setting the ALCMIN control bits.
ALCHLD, ALCDCY and ALCATK control the hold, decay and attack times, respectively:
Hold time is the time delay between the peak level detected being below target and the PGA gain
beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms,
10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time is not
active in limiter mode (ALCMODE = 1). The hold time only applies to gain ramp-up, there is no delay
before ramping the gain down when the signal level is above target.
Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up and is given as a
time per gain step, time per 6dB change and time to ramp up over 90% of it’s range. The decay
time can be programmed in power-of-two (2n) steps, from 3.3ms/6dB, 6.6ms/6dB, 13.1ms/6dB, etc.
to 3.36s/6dB.
Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down and is given
as a time per gain step, time per 6dB change and time to ramp down over 90% of it’s range. The
n
attack time can be programmed in power-of-two (2 ) steps, from 832us/6dB, 1.66ms/6dB,
3.328us/6dB, etc. to 852ms/6dB.
NB, In peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of
fast peaks. Attack and Decay times for peak limiter mode are given below.
The hold, decay and attack times given in Table 16 are constant across sample rates so long as the
SR bits are set correctly. E.g. when sampling at 48kHz the sample rates stated in Table 16 will only
be correct if the SR bits are set to 000 (48kHz). If the actual sample rate was only 44.1kHz then the
hold, decay and attack times would be scaled down by 44.1/48.
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REGISTER
ADDRESS
BIT
R32
ALC Control
1
8:7
ALCSEL
00
ALC function select
00=ALC disabled
01=Right channel ALC enabled
10=Left channel ALC enabled
11=Both channels ALC enabled
5:3
ALCMAXGAIN
[2:0]
111
(+35.25dB)
Set Maximum Gain of PGA
111=+35.25dB
110=+29.25dB
101=+23.25dB
100=+17.25dB
011=+11.25dB
010=+5.25dB
001=-0.75dB
000=-6.75dB
2:0
ALCMINGAIN
[2:0]
000 (-12dB)
Set minimum gain of PGA
000=-12dB
001=-6dB
010=0dB
011=+6dB
100=+12dB
101=+18dB
110=+24dB
111=+30dB
7:4
ALCHLD
[3:0]
0000
(0ms)
ALC hold time before gain is increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
3:0
ALCLVL
[3:0]
1011
(-12dB)
ALC target – sets signal level at ADC
input
0000 = -28.5dB FS
0001 = -27.0dB FS
… (1.5dB steps)
1110 = -7.5dB FS
1111 = -6dB FS
8
ALCZC
0 (zero
cross off)
ALC uses zero cross detection circuit.
R33
ALC Control
2
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DESCRIPTION
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R34
ALC Control
3
8
ALCMODE
0
Determines the ALC mode of operation:
0=ALC mode
1=Limiter mode
7:4
ALCDCY
[3:0]
0011
(13ms/6dB)
Decay (gain ramp-up) time
(ALCMODE ==0)
Per
step
Per
6dB
90% of
range
0000
410us
3.3ms
24ms
0001
820us
6.6ms
48ms
0010
1.64ms
13.1ms
192ms
… (time doubles with every step)
1010
or
higher
0011
(2.9ms/6dB)
420ms
3.36s
24.576s
Decay (gain ramp-up) time
(ALCMODE ==1)
Per
step
Per 6dB
90% of
range
0000
90.8us
726.4us
5.26ms
0001
181.6us
1.453ms
10.53ms
0010
363.2us
2.905ms
21.06ms
… (time doubles with every step)
1010
3:0
ALCATK
[3:0]
0010
(832us/6dB)
93ms
744ms
5.39s
ALC attack (gain ramp-down) time
(ALCMODE == 0)
Per
step
Per 6dB
90% of
range
0000
104us
832us
6ms
0001
208us
1.664ms
12ms
0010
416us
3.328ms
24.1ms
… (time doubles with every step)
1010
or
higher
0010
(182us/6dB)
106ms
852ms
6.18s
ALC attack (gain ramp-down) time
(ALCMODE == 1)
Per
step
Per
6dB
90% of
range
0000
22.7us
182.4us
1.31ms
0001
45.4us
363.2us
2.62ms
0010
90.8us
726.4us
5.26ms
… (time doubles with every step)
1010
23.2ms
186ms
1.348s
Table 16 ALC Control Registers
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ALC CLIP PROTECTION
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
clip protection function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain
is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls
below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
Note:
If ATK = 0000, then the clip protection circuit makes no difference to the operation of the ALC. It is
designed to prevent clipping when long attack times are used.
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8980 has a noise gate function that
prevents noise pumping by comparing the signal level at the input pins against a noise gate
threshold, NGTH. The noise gate cuts in when:
Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to:
Signal level at input pin [dB] < NGTH [dB]
The PGA gain is then held constant (preventing it from ramping up as it normally would when the
signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise
gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.
Levels at the extremes of the range may cause inappropriate operation, so care should be taken with
set–up of the function. Note that the noise gate only works in conjunction with the ALC function.
REGISTER
ADDRESS
BIT
R35
ALC Noise Gate
Control
2:0
3
LABEL
DEFAULT
DESCRIPTION
NGTH
000
Noise gate threshold:
000=-39dB
001=-45dB
010=-51db
… (6dB steps)
111=-81dB
NGATEN
0
Noise gate function enable
1 = enable
0 = disable
Table 17 ALC Noise Gate Control
OUTPUT SIGNAL PATH
The WM8980 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi
DACs, analogue mixers, speaker, stereo headphone and stereo line/mono/midrail output drivers.
The digital filters and DAC are enabled by register bits DACENL And DACENR. The mixers and
output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is
possible to utilise the analogue mixing and amplification provided by the WM8980, irrespective of
whether the DACs are running or not.
The WM8980 DACs receive digital input data on the DACDAT pin. The digital filter block processes
the data to provide the following functions:
§
§
Digital volume control
Graphic equaliser
§
§
A digital peak limiter.
Sigma-Delta Modulation
High performance sigma-delta audio DAC converts the digital data into an analogue signal.
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Figure 12 DAC Digital Filter Path
The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC
analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1), speaker
(LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 have additional mixers which allow them
to output different signals to the headphone and speaker outputs.
DIGITAL PLAYBACK (DAC) PATH
Digital data is passed to the WM8980 via the flexible audio interface and is then passed through a
variety of advanced digital filters as shown in Figure 12 to the hi-fi DACs. The DACs are enabled by
the DACENL/R register bits.
REGISTER
ADDRESS
R3
Power
Management 3
BIT
LABEL
DEFAULT
DESCRIPTION
0
DACENL
0
Left channel DAC enable
0 = DAC disabled
1 = DAC enabled
1
DACENR
0
Right channel DAC enable
0 = DAC disabled
1 = DAC enabled
Table 18 DAC Enable Control
The WM8980 also has a Soft Mute function, which gradually attenuates the volume of the digital
signal to zero. When removed, the gain will ramp back up to the digital gain setting.
REGISTER
ADDRESS
R10
DAC Control
BIT
LABEL
DEFAULT
DESCRIPTION
0
DACPOLL
0
Left DAC output polarity:
0 = non-inverted
1 = inverted (180 degrees phase shift)
1
DACPOLR
0
Right DAC output polarity:
0 = non-inverted
1 = inverted (180 degrees phase shift)
2
AMUTE
0
Automute enable
0 = Amute disabled
1 = Amute enabled
3
DACOSR
0
DAC oversampling rate:
0=64x (lowest power)
1=128x (best performance)
6
SOFTMUTE
0
Softmute enable:
0=Disabled
1=Enabled
Table 19 DAC Control Register
The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital
interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a
high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and
sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and
low distortion.
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The DAC output defaults to non-inverted. Setting DACPOLL will invert the DAC output phase on the
left channel and DACPOLR inverts the phase on the right channel.
AUTOMUTE
The DAC has an automute function which applies an analogue mute when 1024 consecutive zeros
are detected. The mute is released as soon as a non-zero sample is detected. Automute can be
disabled using the AMUTE control bit.
DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain and attenuation range
is –127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by:
0.5 × (X-255) dB for 1 ≤ X ≤ 255;
REGISTER
ADDRESS
R11
Left DAC
Digital Volume
R12
Right DAC
Digital Volume
BIT
LABEL
MUTE for X = 0
DEFAULT
DESCRIPTION
7:0
DACVOLL
[7:0]
11111111
( 0dB )
Left DAC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
8
DACVU
Not
latched
DAC left and DAC right volume do
not update until a 1 is written to
DACVU (in reg 11 or 12)
7:0
DACVOLR
[7:0]
11111111
( 0dB )
Right DAC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
8
DACVU
Not
latched
DAC left and DAC right volume do
not update until a 1 is written to
DACVU (in reg 11 or 12)
Table 20 DAC Digital Volume Control
Note: An additional gain of up to +12dB can be added using the gain block embedded in the
digital peak limiter circuit (see DAC OUTPUT LIMITER section).
DAC 5-BAND EQUALISER
A 5-band graphic equaliser function which can be used to change the output frequency levels to suit
the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND
EQUALISER section for further details on this feature.
DAC 3-D ENHANCEMENT
The WM8980 has an advanced digital 3-D enhancement feature which can be used to vary the
perceived stereo separation of the left and right channels. Like the 5-band equaliser this feature can
be applied to either the record path or the plaback path but not both simultaneously. See the 3-D
STEREO ENHANCEMENT section for further details on this feature.
DAC DIGITAL OUTPUT LIMITER
The WM8980 has a digital output limiter function. The operation of this is shown in Figure 13. In
this diagram the upper graph shows the envelope of the input/output signals and the lower graph
shows the gain characteristic.
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Figure 13 DAC Digital Limiter Operation
The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 13, in
normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the
limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the
LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold
1dB below the upper threshold. When the signal falls below the lower threshold the signal is
amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached.
Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above
the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value.
VOLUME BOOST
The limiter has programmable upper gain which boosts signals below the threshold to compress the
dynamic range of the signal and increase its perceived loudness. This operates as an ALC function
with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the
LIMBOOST register bits.
The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter
is disabled.
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REGISTER
ADDRESS
R24
DAC digital
limiter control
1
BIT
3:0
LABEL
LIMATK
DEFAULT
0010
DESCRIPTION
Limiter Attack time (per 6dB gain
change) for 44.1kHz sampling. Note
that these will scale with sample rate.
0000=94us
0001=188s
0010=375us
0011=750us
0100=1.5ms
0101=3ms
0110=6ms
0111=12ms
1000=24ms
1001=48ms
1010=96ms
1011 to 1111=192ms
7:0
LIMDCY
0011
Limiter Decay time (per 6dB gain
change) for 44.1kHz sampling. Note
that these will scale with sample rate:
0000=750us
0001=1.5ms
0010=3ms
0011=6ms
0100=12ms
0101=24ms
0110=48ms
0111=96ms
1000=192ms
1001=384ms
1010=768ms
1011 to 1111=1.536s
R25
DAC digital
limiter control
2
8
LIMEN
0
Enable the DAC digital limiter:
0=disabled
1=enabled
3:0
LIMBOOST
0000
Limiter volume boost (can be used as a
stand alone volume boost when
LIMEN=0):
0000=0dB
0001=+1dB
0010=+2dB
… (1dB steps)
1011=+11dB
1100=+12dB
1101 to 1111=reserved
6:4
LIMLVL
000
Programmable signal threshold level
(determines level at which the limiter
starts to operate)
000=-1dB
001=-2dB
010=-3dB
011=-4dB
100=-5dB
101 to 111=-6dB
Table 21 DAC Digital Limiter Control
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5-BAND GRAPHIC EQUALISER
A 5-band graphic EQ is provided, which can be applied to the ADC or DAC path, together with 3D
enhancement, under control of the EQ3DMODE register bit.
REGISTER
ADDRESS
R18
EQ Control 1
BIT
8
LABEL
EQ3DMODE
DEFAULT
1
DESCRIPTION
0 = Equaliser and 3D Enhancement
applied to ADC path
1 = Equaliser and 3D Enhancement
applied to DAC path
Table 22 EQ and 3D Enhancement DAC or ADC Path Select
The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak
filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost
(+/- 12dB in 1dB steps). The peak filters have selectable bandwidth.
REGISTER
ADDRESS
R18
EQ Band 1
Control
BIT
LABEL
DEFAULT
DESCRIPTION
4:0
EQ1G
01100
(0dB)
Band 1 Gain Control. See Table 28 for
details.
6:5
EQ1C
01
Band 1 Cut-off Frequency:
00=80Hz
01=105Hz
10=135Hz
11=175Hz
Table 23 EQ Band 1 Control
REGISTER
ADDRESS
R19
EQ Band 2
Control
BIT
LABEL
DEFAULT
4:0
EQ2G
01100
(0dB)
6:5
EQ2C
01
DESCRIPTION
Band 2 Gain Control. See Table 28 for
details.
Band 2 Centre Frequency:
00=230Hz
01=300Hz
10=385Hz
8
EQ2BW
0
11=500Hz
Band 2 Bandwidth Control
0=narrow bandwidth
1=wide bandwidth
Table 24 EQ Band 2 Control
REGISTER
ADDRESS
R20
EQ Band 3
Control
BIT
LABEL
DEFAULT
4:0
EQ3G
01100
(0dB)
6:5
EQ3C
01
DESCRIPTION
Band 3 Gain Control. See Table 28 for
details.
Band 3 Centre Frequency:
00=650Hz
01=850Hz
8
EQ3BW
0
10=1.1kHz
11=1.4kHz
Band 3 Bandwidth Control
0=narrow bandwidth
1=wide bandwidth
Table 25 EQ Band 3 Control
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REGISTER
ADDRESS
R21
EQ Band 4
Control
BIT
LABEL
DEFAULT
4:0
EQ4G
01100
(0dB)
6:5
EQ4C
01
DESCRIPTION
Band 4 Gain Control. See Table 28 for
details
Band 4 Centre Frequency:
00=1.8kHz
8
EQ4BW
01=2.4kHz
10=3.2kHz
11=4.1kHz
Band 4 Bandwidth Control
0=narrow bandwidth
1=wide bandwidth
0
Table 26 EQ Band 4 Control
REGISTER
ADDRESS
R22
EQ Band 5
Gain Control
BIT
LABEL
DEFAULT
4:0
EQ5G
01100
(0dB)
6:5
EQ5C
01
DESCRIPTION
Band 5 Gain Control. See Table 28 for
details.
Band 5 Cut-off Frequency:
00=5.3kHz
01=6.9kHz
10=9kHz
11=11.7kHz
Table 27 EQ Band 5 Control
GAIN REGISTER
GAIN
00000
+12dB
00001
+11dB
00010
+10dB
…. (1dB steps)
01100
0dB
01101
-1dB
11000 to 11111
-12dB
Table 28 Gain Register Table
3D STEREO ENHANCEMENT
The WM8980 has a digital 3D enhancement option to artificially increase the separation between the
left and right channels. Selection of 3D for record or playback is controlled by register bit
EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done
when ADC and DAC are disabled. The WM8980 control interface will only allow EQ3DMODE to be
changed when ADC and DAC are disabled (ie ADCENL = 0, ADCENR = 0, DACENL = 0 and
DACENR = 0).
The DEPTH3D setting controls the degree of stereo expansion.
When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting.
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REGISTER
ADDRESS
R41 (29h)
3D
BIT
3:0
LABEL
DEPTH3D[3:0]
DEFAULT
0000
DESCRIPTION
Stereo depth
0000: 0% (minimum 3D effect)
0001: 6.67%
....
1110: 93.3%
1111: 100% (maximum 3D effect)
Table 29 3D Stereo Enhancement Function
ANALOGUE OUTPUTS
The WM8980 has three sets of stereo analogue outputs. These are:
•
•
•
LOUT1 and ROUT1 which are normally used to drive a headphone load.
LOUT2 and ROUT2 – normally used to drive an 8Ω BTL speaker.
OUT3 and OUT4 – can be configured as a stereo line out (OUT3 is left output and
OUT4 is right output). OUT4 can also be used to provide a mono mix of left and right
channels.
LOUT2, ROUT2, OUT3 and OUT4 are supplied from SPKVDD and are capable of driving up to
1.5Vrms signals as shown in Figure 14. LOUT1 and ROUT1 are supplied from AVDD and can only
drive out a 1V rms signal (AVDD/3.3).
LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB
ranges.
There are four output mixers in the output signal path, the left and right channel mixers which control
the signals to speaker, headphone (and optionally the line outputs) and also dedicated OUT3 and
OUT4 mixers.
LEFT AND RIGHT OUTPUT CHANNEL MIXERS
The left and right output channel mixers are shown in Figure 14. These mixers allow the AUX
inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This
allows a mono mix of the DAC channels to be done as well as mixing in external line-in from the
AUX or speech from the input bypass path.
The AUX and bypass inputs have individual volume control from -15dB to +6dB and the DAC volume
can be adjusted in the digital domain if required. The output of these mixers goes to both the
headphone (LOUT1 and ROUT1) and speaker (LOUT2 and ROUT2) and can optionally go to the
OUT3 and OUT4 mixers.
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Figure 14 Left/Right Output Channel Mixers
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REGISTER
ADDRESS
R49
Output mixer
control
R50
Left channel
output mixer
control
w
BIT
LABEL
DEFAULT
DESCRIPTION
5
DACR2LMIX
0
Right DAC output to left output
mixer
0 = not selected
1 = selected
6
DACL2RMIX
0
Left DAC output to right output mixer
0 = not selected
1 = selected
0
DACL2LMIX
1
Left DAC output to left output mixer
0 = not selected
1 = selected
1
BYPL2LMIX
0
Left bypass path (from the left
channel input boost output) to left
output mixer
0 = not selected
1 = selected
4:2
BYPLMIXVOL
5
AUXL2LMIX
8:6
AUXLMIXVOL
000
Left bypass volume contol to output
channel mixer:
000 = -15dB
001 = -12dB
…
101 = 0dB
110 = +3dB
111 = +6dB
0
Left Auxilliary input to left channel
output mixer:
0 = not selected
1 = selected
000
Aux left channel input to left mixer
volume control:
000 = -15dB
001 = -12dB
…
101 = 0dB
110 = +3dB
111 = +6dB
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R51
Right channel
output mixer
control
R3
Power
management
3
0
DACR2RMIX
1
Right DAC output to right output
mixer
0 = not selected
1 = selected
1
BYPR2RMIX
0
Right bypass path (from the right
channel input boost output) to right
output mixer
0 = not selected
1 = selected
4:2
BYPRMIXVOL
5
AUXR2RMIX
8:6
AUXRMIXVOL
2
LMIXEN
0
Left output channel mixer enable:
0 = disabled
1= enabled
3
RMIXEN
0
Right output channel mixer enable:
0 = disabled
1 = enabled
000
Right bypass volume control to
output channel mixer:
000 = -15dB
001 = -12dB
…
101 = 0dB
110 = +3dB
111 = +6dB
0
Right Auxiliary input to right channel
output mixer:
0 = not selected
1 = selected
000
Aux right channel input to right mixer
volume control:
000 = -15dB
001 = -12dB
…
101 = 0dB
110 = +3dB
111 = +6dB
Table 30 Left and Right Output Mixer Control
HEADPHONE OUTPUTS (LOUT1 AND ROUT1)
The headphone outputs, LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, either
through DC blocking capacitors, or DC coupled without any capacitor. Each headphone output has
an analogue volume control PGA with a gain range of -57dB to +6dB as shown in Figure 17.
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Figure 15 Headphone Outputs LOUT1 and ROUT1
REGISTER
ADDRESS
R52
LOUT1
Volume
control
R53
ROUT1
Volume
control
BIT
LABEL
DEFAULT
DESCRIPTION
7
LOUT1ZC
0
Headphone volume zero cross
enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6
LOUT1MUTE
0
Left headphone output mute:
0 = Normal operation
1 = Mute
5:0
LOUT1VOL
8
HPVU
7
111001
Left headphone output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
Not latched
LOUT1 and ROUT1 volumes do not
update until a 1 is written to HPVU
(in reg 52 or 53)
ROUT1ZC
0
Headphone volume zero cross
enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6
ROUT1MUTE
0
Right headphone output mute:
0 = Normal operation
1 = Mute
5:0
ROUT1VOL
8
HPVU
111001
Not latched
Right headphone output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
LOUT1 and ROUT1 volumes do not
update until a 1 is written to HPVU
(in reg 52 or 53)
Table 31 OUT1 Volume Control
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Headphone Output using DC Blocking Capacitors:
DC Coupled Headphone Output:
Figure 16 Recommended Headphone Output Configurations
When DC blocking capacitors are used, then their capacitance and the load resistance together
determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass
response. Smaller capacitance values will diminish the bass response. Assuming a 16Ω load and
C1, C2 = 220µF:
fc = 1 / 2π RLC1 = 1 / (2π x 16Ω x 220µF) = 45 Hz
In the DC coupled configuration, the headphone “ground” is connected to the VMID pin. The
OUT3/4 pins can be configured as a DC output driver by setting the OUT3MUTE and OUT4MUTE
register bit. The DC voltage on VMID in this configuration is equal to the DC offset on the LOUT1
and ROUT1 pins therefore no DC blocking capacitors are required. This saves space and material
cost in portable applications.
Note that OUT3 and OUT4 have an optional output boost of 1.5x. When these are configured in this
output boost mode (OUT3BOOST/OUT4BOOST=1) then the VMID value of these outputs will be
equal to 1.5xAVDD/2 and will not match the VMID of the headphone drivers. Do not use the DC
coupled output mode in this configuration.
It is recommended to connect the DC coupled outputs only to headphones, and not to the line input
of another device. Although the built-in short circuit protection will prevent any damage to the
headphone outputs, such a connection may be noisy, and may not function properly if the other
device is grounded.
SPEAKER OUTPUTS (LOUT2 AND ROUT2)
The outputs LOUT2 and ROUT2 are designed to drive an 8Ω BTL speaker but can optionally drive
two headphone loads of 16Ω/32Ω or a line output (see Headphone Output and Line Output sections,
respectively). Each output has an individual volume control PGA, an output boost/level shift bit, a
mute and an enable as shown in Figure 17. LOUT2 and ROUT2 output the left and right channel
mixer outputs respectively.
The ROUT2 signal path also has an optional invert. The amplifier used for this invert can be used to
mix in the AUXR signal with an adjustable gain range of -15dB -> +6dB. This allows a ‘beep’ signal
to be applied only to the speaker output without affecting the HP or line outputs.
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Figure 17 Speaker Outputs LOUT2 and ROUT2
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REGISTER
ADDRESS
R54
LOUT2 (SPK)
Volume
control
R55
ROUT2 (SPK)
Volume
control
BIT
LABEL
DEFAULT
DESCRIPTION
7
LOUT2ZC
0
Speaker volume zero cross enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6
LOUT2MUTE
0
Left speaker output mute:
0 = Normal operation
1 = Mute
5:0
LOUT2VOL
8
SPKVU
7
111001
Left speaker output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
Not latched
LOUT2 and ROUT2 volumes do not
update until a 1 is written to SPKVU
(in reg 54 or 55)
ROUT2ZC
0
Speaker volume zero cross enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6
ROUT2MUTE
0
Right speaker output mute:
0 = Normal operation
1 = Mute
5:0
ROUT2VOL
8
SPKVU
111001
Not latched
Right speaker output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
LOUT2 and ROUT2 volumes do not
update until a 1 is written to SPKVU
(in reg 54 or 55)
Table 32 Speaker Volume Control
The signal to be output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any
combination of the DAC output, the Bypass path (output of the input boost stage) and the AUX input.
The LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Note that
gains over 0dB may cause clipping if the signal is large. The LOUT2MUTE/ ROUT2MUTE register
bits cause the speaker outputs to be muted (the output DC level is driven out). The output pins
remain at the same DC level (DCOP), so that no click noise is produced when muting or un-muting
The speaker output stages also have a selectable gain boost of 1.5x (3.52dB). When this boost is
enabled the output DC level is also level shifted (from AVDD/2 to 1.5xAVDD/2) to prevent the signal
from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 18, is used to perform the DC
level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this
operating mode. It should also be noted that if SPKVDD is not equal to or greater than 1.5xAVDD
this boost mode may result in signals clipping. Table 34 summarises the effect of the SPKBOOST
control bits.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R49
Output control
2
SPKBOOST
0
0 = speaker gain = -1;
DC = AVDD / 2
1 = speaker gain = +1.5;
DC = 1.5 x AVDD / 2
R1
Power
management
1
8
BUFDCOPEN
0
Dedicated buffer for DC level shifting
output stages when in 1.5x gain
boost configuration.
0=Buffer disabled
1=Buffer enabled (required for 1.5x
gain boost)
Table 33 Speaker Boost Stage Control
SPKBOOST
OUTPUT
STAGE GAIN
OUTPUT DC
LEVEL
OUTPUT STAGE
CONFIGURATION
0
1x (0dB)
AVDD/2
Inverting
1
1.5x (3.52dB)
1.5xAVDD/2
Non-inverting
Table 34 Output Boost Stage Details
REGISTER
ADDRESS
R43
Beep control
BIT
LABEL
DEFAULT
5
MUTERPGA2INV
0
4
INVROUT2
0
3:1
BEEPVOL
000
0
BEEPEN
0
DESCRIPTION
Mute input to INVROUT2 mixer
Invert ROUT2 output
AUXR input to ROUT2 inverter gain
000 = -15dB
...
111 = +6dB
0 = mute AUXR beep input
1 = enable AUXR beep input
Table 35 AUXR – ROUT2 BEEP Mixer Function
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ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output
PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This
is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital
and is equal to 221 * input clock period.
REGISTER
ADDRESS
R7
Additional
Control
BIT
0
LABEL
SLOWCLKEN
DEFAULT
0
DESCRIPTION
Slow clock enable. Used for both the
jack insert detect debounce circuit and
the zero cross timeout.
0 = slow clock disabled
1 = slow clock enabled
Table 36 Timeout Clock Enable Control
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OUT3/OUT4 MIXERS AND OUTPUT STAGES
The OUT3/OUT4 pins can provide an additional stereo line output, a mono output, or a pseudo
ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for
OUT4 as shown in Figure 19.
The OUT3 and OUT4 output stages are powered from SPKVDD and SPKGND. The individually
controllable outputs also incorporate an optional 1.5x boost and level shifting stage.
Figure 19 OUT3 and OUT4 Mixers
OUT3 can provide a buffered midrail headphone pseudo-ground, or a left line output.
OUT4 can provide a buffered midrail headphone pseudo-ground, a right line output, or a mono mix
output.
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REGISTER
ADDRESS
R56
OUT3 mixer
control
R57
OUT4 mixer
control
BIT
LABEL
DEFAULT
DESCRIPTION
6
OUT3MUTE
0
0 = Output stage outputs OUT3 mixer
1 = Output stage muted – drives out
VMID. Can be used as VMID buffer in
this mode.
3
OUT4_2OUT3
0
OUT4 mixer output to OUT3
0 = disabled
1= enabled
2
BYPL2OUT3
0
Left ADC input to OUT3
0 = disabled
1= enabled
1
LMIX2OUT3
0
Left DAC mixer to OUT3
0 = disabled
1= enabled
0
LDAC2OUT3
1
Left DAC output to OUT3
0 = disabled
1= enabled
6
OUT4MUTE
0
0 = Output stage outputs OUT4 mixer
1 = Output stage muted – drives out
VMID. Can be used as VMID buffer in
this mode.
5
HALFSIG
0
0=OUT4 normal output
1=OUT4 attenuated by 6dB
4
LMIX2OUT4
0
Left DAC mixer to OUT4
0 = disabled
1= enabled
3
LDAC2OUT4
0
Left DAC to OUT4
0 = disabled
1= enabled
2
BYPR2OUT4
0
Right ADC input to OUT4
0 = disabled
1= enabled
1
RMIX2OUT4
0
Right DAC mixer to OUT4
0 = disabled
1= enabled
0
RDAC2OUT4
1
Right DAC output to OUT4
0 = disabled
1= enabled
Table 37 OUT3/OUT4 Mixer Registers
The OUT3 and OUT4 output stages each have a selectable gain boost of 1.5x (3.52dB). When this
boost is enabled the output DC level is also level shifted (from AVDD/2 to 1.5xAVDD/2) to prevent
the signal from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 20, is used to perform
the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this
operating mode. It should also be noted that if SPKVDD is not equal to or greater than 1.5xAVDD
this boost mode may result in signals clipping. Table 34 summarises the effect of the OUT3BOOST
and OUT4BOOST control bits.
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Figure 21 Outputs OUT3 and OUT4
REGISTER
ADDRESS
R49
Output control
R1
Power
management
1
BIT
LABEL
DEFAULT
DESCRIPTION
3
OUT3BOOST
0
0 = OUT3 output gain = -1;
DC = AVDD / 2
1 = OUT3 output gain = +1.5
DC = 1.5 x AVDD / 2
4
OUT4BOOST
0
0 = OUT4 output gain = -1;
DC = AVDD / 2
1 = OUT4 output gain = +1.5
DC = 1.5 x AVDD / 2
8
BUFDCOPEN
0
Dedicated buffer for DC level shifting
output stages when in 1.5x gain
boost configuration.
0=Buffer disabled
1=Buffer enabled (required for 1.5x
gain boost)
Table 38 OUT3 and OUT4 Boost Stages Control
OUT3BOOST/
OUT4BOOST
OUTPUT
STAGE GAIN
OUTPUT DC
LEVEL
OUTPUT STAGE
CONFIGURATION
0
1x
AVDD/2
Inverting
1
1.5x
1.5xAVDD/2
Non-inverting
Table 39 OUT3/OUT4 Output Boost Stage Details
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ENABLING THE OUTPUTS
Each analogue output of the WM8980 can be separately enabled or disabled. The analogue mixer
associated with each output has a separate enable. All outputs are disabled by default. To save
power, unused parts of the WM8980 should remain disabled.
Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled
(BUFIOEN=0) or when BUFDCOP is disabled (BUFDCOPEN=0) when configured in output boost
mode, as this may cause pop noise (see “Power Management” and “Applications Information”
sections).
REGISTER
ADDRESS
R1
Power
Management
1
R2
Power
Management
2
R3
Power
Management
3
BIT
LABEL
DEFAULT
DESCRIPTION
2
BUFIOEN
0
Unused input/output tie off buffer enable
6
OUT3MIXEN
0
OUT3 mixer enable
7
OUT4MIXEN
0
OUT4 mixer enable
8
BUFDCOPEN
0
Output stage 1.5xAVDD/2 driver enable
8
ROUT1EN
0
ROUT1 output enable
7
LOUT1EN
0
LOUT1 output enable
6
SLEEP
0
0 = normal device operation
1 = residual current reduced in device
standby mode
2
LMIXEN
0
Left mixer enable
3
RMIXEN
0
Right mixer enable
4
VBUFEN
0
Video buffer enable
5
ROUT2EN
0
ROUT2 output enable
6
LOUT2EN
0
LOUT2 output enable
7
OUT3EN
0
OUT3 enable
8
OUT4EN
0
OUT4 enable
Note: All “Enable” bits are 1 = ON, 0 = OFF
Table 40 Output Stages Power Management Control
THERMAL SHUTDOWN
The speaker outputs can drive very large currents. To protect the WM8980 from overheating a
thermal shutdown circuit is included. If the device temperature reaches approximately 1250C and the
thermal shutdown circuit is enabled (TSDEN=1) then the speaker amplifiers will be disabled if
TSDEN is set. The thermal shutdown may also be configured to generate an interrupt. See the GPIO
and Interrupt Controller section for details.
REGISTER
ADDRESS
R49
Output
control
BIT
1
LABEL
TSDEN
DEFAULT
1
DESCRIPTION
Thermal Shutdown Enable
0 : thermal shutdown disabled
1 : thermal shutdown enabled
Table 41 Thermal Shutdown
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to a voltage source (either
AVDD/2 or 1.5xAVDD/2 as appropriate) through a resistor. This helps to prevent pop noise when the
output is re-enabled. The resistance between the voltage buffer and the output pins can be
controlled using the VROI control bit. The default impedance is low, so that any capacitors on the
outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI
can then be set to 1, increasing the resistance to about 30kΩ.
REGISTER
ADDRESS
R49
BIT
0
LABEL
VROI
DEFAULT
0
DESCRIPTION
VREF (AVDD/2 or 1.5xAVDD/2) to
analogue output resistance
0: approx 1kΩ
1: approx 30 kΩ
Table 42 Disabled Outputs to VREF Resistance
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A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 22. This
buffer can be enabled using the BUFIOEN register bit.
If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set then the relevant outputs will be tied
to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled.
Figure 22 summarises the tie-off options for the speaker and mono output pins.
Figure 22 Unused Input/Output Pin Tie-off Buffers
L/ROUT2EN/
OUT3/4EN
OUT3BOOST/
OUT4BOOST/
SPKBOOST
VROI
OUTPUT CONFIGURATION
0
0
0
1kΩ tie-off to AVDD/2
0
0
1
30kΩ tie-off to AVDD/2
0
1
0
1kΩ tie-off to 1.5xAVDD/2
0
1
1
30kΩ tie-off to 1.5xAVDD/2
1
0
X
Output enabled (DC level=AVDD/2)
1
1
X
Output enabled (DC level=1.5xAVDD/2)
Table 43 Unused Output Pin Tie-off Options
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VIDEO BUFFER
DESCRIPTION
The WM8980 incorporates a current mode output video buffer capable of operating from a 2.5V
rd
supply, with an input 3 order Low Pass Filter (LPF) and clamp. The gain through this buffer can be
programmed as 0dB or 6dB via the control interface. The current mode output means that the signal
swing seen at the output of the buffer will be the same as that at the connection to the receiving
equipment (e.g. a TV). Note that the input to the receiver should be AC coupled and terminated to
75Ω, as is standard, for best performance.
Figure 23 Video Buffer
The input clamp should be enabled when using AC coupling at the input to the video buffer, using
the VBCLAMPEN register bit.
Care should be taken with PCB layout, designing for at least 1GHz frequencies to avoid degrading
performance. Vias and sharp corners should be avoided and parasitic capacitance minimised on
signal paths, which should be kept as short and straight as possible. The VBVDD supply should be
decoupled as close to the pin as possible. See the “External Components” section for more
information.
LOW PASS FILTER
A low pass filter is integrated at the video buffer input, which is intended to remove images in the
rd
video DAC output waveform at multiples of the DAC clock frequency. A 3 order Butterworth filter is
used, with the following characteristics:
VIDEO BUFFER REGISTERS
Video buffer enable / disable and gain are controlled via the following registers:
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3
Power management
3
4
VBUFEN
0
Video buffer enable
0 = enabled
1 = disabled
R40
Video Buffer
8
VBGAIN
0
Video buffer gain
0 = 0dB
1 = +6dB
7
VBCLAMPEN
0
Video buffer clamp enable
0 = disabled
1 = enabled
Table 44 Video Buffer Registers
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DIGITAL AUDIO INTERFACES
The audio interface has four pins:
•
ADCDAT: ADC data output
•
•
•
DACDAT: DAC data input
LRC: Data Left/Right alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK, and LRC can be outputs when the WM8980 operates as a master, or inputs
when it is a slave (see Master and Slave Mode Operation, below).
Five different audio data formats are supported:
•
•
•
Left justified
Right justified
I 2S
•
•
DSP mode A
DSP mode B
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8980 audio interface may be configured as either master or slave. As a master interface
device the WM8980 generates BCLK and LRC and thus controls sequencing of the data transfer on
ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In
slave mode (MS=0), the WM8980 responds with data to clocks it receives over the digital audio
interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.
Figure 24 Left Justified Audio Interface (assuming n-bit word length)
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In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition.
All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and
sample rate, there may be unused BCLK cycles after each LRC transition.
Figure 25 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The
other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency
and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of
the next.
Figure 26 I2S Audio Interface (assuming n-bit word length)
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st
In DSP/PCM mode, the left channel MSB is available on either the 1 (mode B) or 2nd (mode A)
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
Figure 27 DSP/PCM Mode Audio Interface (mode A, LCRP=0)
Figure 28 DSP/PCM Mode Audio Interface (mode B, LCRP=1)
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REGISTER
ADDRESS
R4
Audio
Interface
Control
BIT
LABEL
DEFAULT
DESCRIPTION
0
MONO
0
Selects between stereo and mono
device operation:
0=Stereo device operation
1=Mono device operation. Data appears
in ‘left’ phase of LRC
1
ADCLRSWAP
0
Controls whether ADC data appears in
‘right’ or ‘left’ phases of LRC clock:
0=ADC data appear in ‘left’ phase of
LRC
1=ADC data appears in ‘right’ phase of
LRC
2
DACLRSWAP
0
Controls whether DAC data appears in
‘right’ or ‘left’ phases of LRC clock:
0=DAC data appear in ‘left’ phase of
LRC
1=DAC data appears in ‘right’ phase of
LRC
4:3
FMT
10
Audio interface Data Format Select:
00=Right Justified
01=Left Justified
10=I2S format
11= DSP/PCM mode
6:5
WL
10
Word length
00=16 bits
01=20 bits
10=24 bits
11=32 bits (see note)
7
LRCP
LRC clock polarity
0=normal
1=inverted
8
BCP
BCLK polarity
0=normal
1=inverted
Table 45 Audio Interface Control
Note: Right Justified Mode will only operate with a maximum of 24 bits.
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below. Each audio interface can be controlled individually.
Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK,
and LRC are outputs. The frequency of BCLK in master mode are controlled with BCLKDIV. These
are divided down versions of master clock. This may result in short BCLK pulses at the end of a
LRC if there is a non-integer ratio of BCLKs to LRC clocks.
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REGISTER
ADDRESS
R6
Clock
Generation
Control
BIT
LABEL
DEFAULT
DESCRIPTION
0
MS
0
Sets the chip to be master over LRC
and BCLK
0=BCLK and LRC clock are inputs
1=BCLK and LRC clock are outputs
generated by the WM8980 (MASTER)
4:2
BCLKDIV
000
Configures the BCLK output frequency,
for use when the chip is master over
BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
7:5
MCLKDIV
010
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
8
CLKSEL
1
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
Table 46 Clock Control
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8980 supports A-law and µ-law and companding and linear mode on both transmit (ADC)
and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by
writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
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REGISTER
ADDRESS
R5
Companding
Control
BIT
LABEL
DEFAULT
DESCRIPTION
0
LOOPBACK
0
Digital loopback function
0=No loopback
1=Loopback enabled, ADC data output
is ded directly into DAC data input.
2:1
ADC_COMP
0
ADC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
4:3
DAC_COMP
0
DAC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
5
WL8
0
0=off
1=device operates in 8-bit mode
Table 47 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
µ-law (where µ=255 for the U.S. and Japan):
F(x) = ln( 1 + µ|x|) / ln( 1 + µ)
-1
x
1
A-law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
} for x
F(x) = ( 1 + lnA|x|) / (1 + lnA)
} for 1/A
1/A
x
1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for µ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s
of data.
Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The
input data range is separated into 8 levels, allowing low amplitude signals better precision than that
of high amplitude signals. This is to exploit the operation of the human auditory system, where
louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to
use 8 BCLK’s per LRC frame. When using DSP mode B, this allows 8-bit data words to be output
consecutively every 8 BCLK’s and can be used with 8-bit data words using the A-law and u-law
companding functions.
BIT8
BIT[7:4]
BIT[3:0]
SIGN
EXPONENT
MANTISSA
Table 48 8-bit Companded Word Composition
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u-law Companding
1
120
0.9
Companded Output
0.7
80
0.6
0.5
60
0.4
40
0.3
Normalised Output
0.8
100
0.2
20
0.1
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalised Input
Figure 29 u-Law Companding
A-law Companding
1
120
0.9
Companded Output
0.7
80
0.6
0.5
60
0.4
40
0.3
Normalised Output
0.8
100
0.2
20
0.1
0
0
0
0.2
0.4
0.6
0.8
1
Normalised Input
Figure 30 A-Law Companding
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AUDIO SAMPLE RATES
The WM8980 sample rates for the ADCs and the DACs are set using the SR register bits. The
cutoffs for the digital filters and the ALC attack/decay times stated are determined using these
values and assume a 256fs master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the
closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack,
decay and hold times will scale appropriately.
REGISTER
ADDRESS
R7
Additional
Control
BIT
LABEL
3:1
SR
DEFAULT
000
DESCRIPTION
Approximate sample rate (configures the
coefficients for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
Table 49 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8980 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8980 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1 and/or GPI04) a clock for another part of the system that is
derived from an existing audio master clock.
Figure 31 shows the PLL and internal clocking arrangment on the WM8980.
The PLL can be enabled or disabled by the PLLEN register bit.
REGISTER
ADDRESS
R1
Power
management 1
BIT
5
LABEL
PLLEN
DEFAULT
0
DESCRIPTION
PLL enable
0=PLL off
1=PLL on
Table 50 PLLEN Control Bit
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Figure 31 PLL and Clock Select Circuit
The PLL frequency ratio R = f2/f1 (see Figure 31) can be set using the register bits PLLK and PLLN:
PLLN = int R
PLLK = int (224 (R-PLLN))
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a
selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
PLLN = int R = 8
24
k = int ( 2
x (8.192 – 8)) = 3221225 = 3126E9h
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R36
PLL N value
4
PLLPRESCALE
0
Divide MCLK by 2 before input to
PLL
3:0
PLLN
1000
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
R37
PLL K value
1
5:0
PLLK [23:18]
0Ch
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
R38
PLL K Value
2
8:0
PLLK [17:9]
093h
R39
PLL K Value
3
8:0
PLLK [8:0]
0E9h
Table 51 PLL Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in Table 52.
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MCLK
(MHz)
(F1)
DESIRED
OUTPUT
(MHz)
F2
(MHz)
PRESCALE
DIVIDE
POSTSCALE
DIVIDE
R
N
(Hex)
K
(Hex)
12
11.29
90.3168
1
2
12
12.288
98.304
1
2
7.5264
7
86C227
8.192
8
13
11.29
90.3168
1
3126E9
2
6.947446
6
F28BD5
13
12.288
98.304
1
2
7.561846
7
8FD526
14.4
11.29
90.3168
1
2
6.272
6
45A1CB
14.4
12.288
98.304
1
2
6.826667
6
D3A06D
19.2
11.29
90.3168
2
2
9.408
9
6872B0
19.2
12.288
98.304
2
2
10.24
A
3D70A4
19.68
11.29
90.3168
2
2
9.178537
9
2DB493
19.68
12.288
98.304
2
2
9.990243
9
FD80A0
19.8
11.29
90.3168
2
2
9.122909
9
1F76F8
19.8
12.288
98.304
2
2
9.929697
9
EE009F
24
11.29
90.3168
2
2
7.5264
7
86C227
24
12.288
98.304
2
2
8.192
8
3126E9
26
11.29
90.3168
2
2
6.947446
6
F28BD5
26
12.288
98.304
2
2
7.561846
7
8FD526
27
11.29
90.3168
2
2
6.690133
6
BOAC94
27
12.288
98.304
2
2
7.281778
7
482297
12
11.29
90.3168
1
2
7.5264
7
86C227
12
12.288
98.304
1
2
8.192
8
3126E9
Table 52 PLL Frequency Examples
GENERAL PURPOSE INPUT/OUTPUT
The WM8980 has three dual purpose input/output pins and one dedicated GPIO.
•
CSB/GPIO1: CSB / GPIO pin
•
L2/GPIO2: Left channel line input / headphone detection input
•
R2/GPIO3: Right channel line input / headphone detection input
•
GPIO4: Dedicated GPIO
The GPIO2 and GPIO3 functions are provided for use as jack detection inputs.
The GPIO1 and GPIO4 functions are provided for use as jack detection inputs or general purpose
outputs.
The default configuration for the CSB/GPIO1 and GPIO4 pins are to be inputs.
When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection,
depending on how the MODE pin is set.
If setup as an input the GPIO4 pin can also be used for jack detection.
Table 49 illustrates the functionality of the GPIO1 and GPIO4 pins when used as general purpose
outputs.
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REGISTER
ADDRESS
R8
GPIO
Control
R9
GPIO
Control
BIT
LABEL
DEFAULT
DESCRIPTION
2:0
GPIO1SEL
000
CSB/GPIO1 pin function select:
000= input (CSB/jack detection:
depending on MODE setting)
001= reserved
010=Temp ok
011=Amute active
100=PLL clk o/p
101=PLL lock
110=logic 1
111=logic 0
3
GPIO1POL
0
GPIO1 Polarity invert
0=Non inverted
1=Inverted
5:4
OPCLKDIV
00
PLL Output clock division ratio
00=divide by 1
01=divide by 2
10=divide by 3
11=divide by 4
2:0
GPIO4SEL
000
GPIO4 pin function select:
000= input jack detection
001= reserved
010=Temp ok
011=Amute active
100=PLL clk o/p
101=PLL lock
110=logic 1
111=logic 0
3
GPIO4POL
0
GPIO4 Polarity invert
0=Non inverted
1=Inverted
Table 53 CSB/GPIO Control
Note: If MODE is set to 3 wire mode, CSB/GPIO1 shall be used as CSB input irrespective of the
GPIO1SEL[2:] bits.
For further details of the Jack detect operation see the OUTPUT SWITCHING section.
OUTPUT SWITCHING (JACK DETECT)
When the device is configured with a 2-wire interface the CSB/GPIO1 pin can be used as a switch
control input to automatically disable one set of outputs and enable another. The L2/GPIO2,
R2/GPIO3 and GPIO4 pins can also be used for this purpose. For example, when a headphone is
plugged into a jack socket then it may be desirable to disable the speaker (e.g. when one of the
GPIO pins is connected to a mechanical switch in the headphone socket to detect plug-in).
The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output
enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a
slow clock with period 221 x MCLK.
Note that the GPIOPOL bits are not relevant for jack detection, it is the signal detected at the pin
which is used.
The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2,
OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and
OUT4_EN_0 are the output enable signal which are used if the selected jack detection pin is at logic
0 (after de-bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output
enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce).
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Similar to the output enables, VMID, which can be driven out of OUT3 can be configured to be on/off
depending on the jack detection input polarity using the VMID_EN_0 and VMID_EN_1 bits.
The jack detection enables work as follows:
All OUT_EN signals have an AND function performed with their normal enable signals (in Table 40).
When an output is normally enabled at per Table 40, the selected jack detection enable (controlled
by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is
already OFF (0), the jack detection signal will have no effect due on the AND function.
During jack detection if the user desires an output to be un-changed whether the jack is in or not,
both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000.
The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the
VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should
set to 0 for all JD_EN0 or JD_EN1 settings.
If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs
to be controlled as normal via the normal output enables found in Table 40. Similarly the VMID_EN
signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit.
REGISTER
ADDRESS
R9
GPIO Control
R13
GPW Control
BIT
LABEL
DEFAULT
DESCRIPTION
5:4
JD_SEL
00
Pin selected as jack detection input
00 = GPIO1
01 = GPIO2
10 = GPIO3
11 = GPIO4
6
JD_EN
0
Jack Detection Enable
0=disabled
1=enabled
8:7
JD_VMID
00
[7] VMID_EN_0
[8] VMID_EN_1
3:0
JD_EN0
0
Output enabled when selected jack
detection input is logic 0.
[0]= OUT1_EN_0
[1]= OUT2_EN_0
[2]= OUT3_EN_0
[3]= OUT4_EN_0
7:4
JD_EN1
0
Output enabled when selected jack
detection input is logic 1
[4]= OUT1_EN_1
[5]= OUT2_EN_1
[6]= OUT3_EN_1
[7]= OUT4_EN_1
Table 54 Jack Detect Register Control Bits
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CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin
determines the 2 or 3 wire mode as shown in Table 55.
The WM8980 is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each
control register.
MODE
INTERFACE FORMAT
Low
2 wire
High
3 wire
Table 55 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB/GPIO1 pin latches in a complete control word consisting of the last 16 bits.
Figure 32 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8980 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit
address of each register in the WM8980).
The WM8980 operates as a slave 2-wire device only. The controller indicates the start of data
transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device
address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in
the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address
received matches the address of the WM8980, then the WM8980 responds by pulling SDIN low on
the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in
write only mode, the WM8980 returns to the idle condition and wait for a new start condition and
valid address.
During a write, once the WM8980 has acknowledged a correct address, the controller sends the first
byte of control data (B15 to B8, i.e. the WM8980 register address plus the first bit of register data).
The WM8980 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8980 acknowledges again by pulling SDIN low.
Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a
complete sequence the WM8980 returns to the idle state and waits for another start condition. If a
start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN
changes while SCLK is high), the device jumps to the idle condition.
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DEVICE ADDRESS
(7 BITS)
SDIN
RD / WR
BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 1
(BITS 7 TO 0)
ACK
(LOW)
SCLK
START
register address and
1st register data bit
remaining 8 bits of
register data
STOP
Figure 33 2-Wire Serial Control Interface
In 2-wire mode the WM8980 has a fixed device address, 0011010.
RESETTING THE CHIP
The WM8980 can be reset by performing a write of any value to the software reset register (address
0 hex). This will cause all register values to be reset to their default values. In addition to this there
is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the
device is powered up.
POWER SUPPLIES
The WM8980 can use up to five separate power supplies:
AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and
mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on
overall power consumption (except for power consumed in the headphone). A large AVDD slightly
improves audio quality.
SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output
drivers. SPKVDD can range from 2.5V to 5V. SPKVDD can be tied to AVDD, but it requires separate
layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder
headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than
AVDD, the output signal may be clipped.
DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces.
DCVDD can range from 1.62V to 3.6V, and has no effect on audio quality. The return path for
DCVDD is DGND, which is shared with DBVDD.
DBVDD can range from 1.8V to 3.6V. DBVDD return path is through DGND.
VBVDD and VBGND: Supplies for video buffer circuit. VBVDD can range from 2.5V to 3.6V.
It is possible to use the same supply voltage for all four supplies. However, digital and analogue
supplies should be routed and decoupled separately on the PCB to keep digital switching noise out
of the analogue signal paths.
RECOMMENDED POWER UP/DOWN SEQENCE
In order to minimise output ‘pop’ and ‘click’ noise it is recommended that the device is powered up in
a controlled sequence.
In addition to this it is recommended that the zero cross functions are used when changing the
volume in the PGAs.
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POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode.
Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x
oversampling results in a slight decrease in noise performance compared to 128x but lowers the
power consumption of the device.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R10
DAC control
3
DACOSR128
0
DAC oversample rate select
0 = 64x (lowest power)
1 = 128x (best SNR)
R14
ADC control
3
ADCOSR128
0
ADC oversample rate select
0 = 64x (lowest power)
1 = 128x (best SNR)
Table 56 ADC and DAC Oversampling Rate Selection
VMID
The analogue will not work unless VMID is enabled (VMIDSEL 00). The impedance of the VMID
resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time
of the VMID circuit.
REGISTER
ADDRESS
R1
Power
management 1
BIT
1:0
LABEL
DEFAULT
VMIDSEL
00
DESCRIPTION
Reference string impedance to VMID pin
(detemines startup time):
00=off (open circuit)
01=75kΩ
10=300kΩ
11=5kΩ (for fastest startup)
Table 57 VMID Impedance Control
BIASEN
The analogue amplifiers will not operate unless BIASEN is enabled.
REGISTER
ADDRESS
R1
Power
management 1
BIT
3
LABEL
BIASEN
DEFAULT
0
DESCRIPTION
Analogue amplifier bias control
Table 58 Analogue Bias Control
ESTIMATED SUPPLY CURRENTS
When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from
DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an
additional 700 microamps will be drawn from DCVDD. It is anticipated that the video buffer will draw
about 1mA with no load attached, in normal operating up to 30 mA will be drawn.
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Table 53 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit.
REGISTER BIT
AVDD CURRENT (MILLIAMPS)
BUFDCOPEN
0.1
OUT4MIXEN
0.2
OUT3MIXEN
0.2
PLLEN
1.4 (with clocks applied)
MICBEN
0.5
BIASEN
0.3
BUFIOEN
0.1
VMIDSEL
10K=>0.3, less than 0.1 for 100k/500k
ROUT1EN
0.4
LOUT1EN
0.4
BOOSTENR
0.2
BOOSTENL
0.2
INPPGAENR
0.2
INPPGAENL
0.2
ADCENR
x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9
ADCENL
x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9
OUT4EN
0.2
OUT3EN
0.2
LOUT2EN
1mA from SPKVDD + 0.2mA from AVDD in 5V mode
ROUT2EN
1mA from SPKVDD + 0.2mA from AVDD in 5V mode
RMIXEN
0.2
LMIXEN
0.2
DACENR
x64 (DACOSR=0)=>1.8, x128(DACOSR=1)=>1.9
DACENL
x64 (DACOSR=0)=>1.8, x128(DACOSR=1)=>1.9
Table 59 AVDD Supply Current
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REGISTER MAP
ADDR
B[15:9]
REGISTER
NAME
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEC HEX
DEF’T
VAL
(HEX)
0
00
Software Reset
1
01
Power manage’t 1
BUFDCOP
EN
OUT4MIX
EN
2
02
Power manage’t 2
ROUT1EN
LOUT1EN
3
03
Power manage’t 3
OUT4EN
OUT3EN
4
04
Audio Interface
BCP
LRCP
5
05
Companding ctrl
0
0
6
06
Clock Gen ctrl
CLKSEL
7
07
Additional ctrl
0
0
0
8
08
GPIO Stuff
0
0
0
OPCLKDIV
GPIO1POL
GPIO1SEL[2:0]
9
09
Jack detect control
JD_VMID1
JD_VMID0
JD_EN
JD_SEL
GPIO4POL
GPIO4SEL[2:0]
10
0A
DAC Control
0
0
SOFT
MUTE
11
0B
Left DAC digital Vol
DACVU
DACVOLL
12
0C
Right DAC dig’l Vol
DACVU
DACVOLR
Software reset
PLLEN
OUT3MIX
EN
SLEEP
MICBEN
BIASEN
BUFIOEN
VMIDSEL
OOSTENRBOOSTENL INPGAENR NPPGAENL ADCENR
LOUT2EN ROUT2EN VBUFEN
WL8
LMIXEN
DACENR
000
DLRSWAP ALRSWAP
MONO
050
ADC_COMP
LOOPBACK
000
MS
140
LOWCLKEN
000
BCLKDIV
0
0
0
000
DACENL
FMT
MCLKDIV
0
ADCENL
DAC_COMP
WL
0
RMIXEN
000
SR
0
DACOSR
128
AMUTE
000
000
DACPOLR DACPOLL
000
0FF
0FF
13 0D
ack Detect Control
14
0E
ADC Control
15
0F
Left ADC Digital Vol
ADCVU
ADCVOLL
0FF
16
10
Right ADC Digital
Vol
ADCVU
ADCVOLR
0FF
18
12
EQ1 – low shelf
EQ3DMODE
0
EQ1C
EQ1G
12C
19
13
EQ2 – peak 1
EQ2BW
0
EQ2C
EQ2G
02C
20
14
EQ3 – peak 2
EQ3BW
0
EQ3C
EQ3G
02C
21
15
EQ4 – peak 3
EQ4BW
0
EQ4C
EQ4G
02C
22
16
EQ5 – high shelf
0
0
EQ5C
EQ5G
02C
24
18
DAC Limiter 1
LIMEN
25
19
DAC Limiter 2
0
0
27
1B
Notch Filter 1
NFU
NFEN
NFA0[13:7]
000
28
1C
Notch Filter 2
NFU
0
NFA0[6:0]
000
29
1D
Notch Filter 3
NFU
0
NFA1[13:7]
000
30
1E
Notch Filter 4
NFU
0
NFA1[6:0]
32
20
ALC control 1
33
21
ALC control 2
ALCZC
34
22
ALC control 3
ALCMODE
35
23
Noise Gate
0
0
0
0
0
36
24
PLL N
0
0
0
0
PLL_PRE
SCALE
37
25
PLL K 1
0
0
0
38
26
PLL K 2
PLLK[17:9]
093
39
27
PLL K 3
PLLK[8:0]
0E9
40
28
Video Buffer
0
0
0
41
29
3D control
0
0
0
0
0
43
2B
Beep control
0
0
0
MUTER
PGA2INV
INVROUT2
44
2C
Input ctrl
MICBVSEL
0
R2_2
INPPGA
RIN2
INPPGA
RIP2
INPPGA
45
2D
Left INP PGA gain
ctrl
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JD_EN1
HPFEN
HPFAPP
HPFCUT
INPGA
UPDATE
ADCOSR
128
0
LIMDCY
LIMLVL
ALCSEL
0
ADCRPOL ADCLPOL
032
LIMBOOST
000
000
038
ALCMIN
ALCHLD
ALCDCY
ALCLVL
00B
ALCATK
032
NGEN
000
NGTH
008
PLLN[3:0]
00C
PLLK[23:18]
0
0
0
VBPULLDWN VBGAIN VBCLAMP
EN
L2_2
INPPGA
INPPGAVOLL
LIN2
INPPGA
000
000
DEPTH3D
BEEPVOL
0
100
LIMATK
ALCMAX
NPPGAZCL INPPGA
MUTEL
000
JD_EN0
BEEPEN
000
LIP2
INPPGA
003
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46
2E
Right INP PGA
gain ctrl
47
2F
Left ADC Boost ctrl PGABOOSTL
0
L2_2BOOSTVOL
0
AUXL2BOOSTVOL
100
48
30
Right ADC Boost
ctrl
PGABOOSTR
0
R2_2BOOSTVOL
0
AUXR2BOOSTVOL
100
49
31
Output ctrl
0
0
50
32
Left mixer ctrl
AUXLMIXVOL
AUXL2LMIX
BYPLMIXVOL
BYPL2LMIX DACL2LMIX
001
51
33
Right mixer ctrl
AUXRMIXVOL
UXR2RMIX
BYPRMIXVOL
BYPR2RMIX DACR2RMIX
001
52
34
LOUT1 (HP)
volume ctrl
UPDATE
LOUT1ZC
LOUT1
MUTE
LOUT1VOL
039
53
35
ROUT1 (HP)
volume ctrl
UPDATE
ROUT1ZC
ROUT1
MUTE
ROUT1VOL
039
54
36
LOUT2 (SPK)
volume ctrl
UPDATE
LOUT2ZC
LOUT2
MUTE
LOUT2VOL
039
55
37
ROUT2 (SPK)
volume ctrl
UPDATE
ROUT2ZC
ROUT2
MUTE
ROUT2VOL
039
56
38
OUT3 mixer ctrl
0
0
OUT3
MUTE
0
0
OUT4_
2OUT3
BYPL2
OUT3
LMIX2
OUT3
LDAC2
OUT3
001
57
39
OUT4 (MONO)
mixer ctrl
0
0
OUT4
MUTE
HALFSIG
LMIX2
OUT4
LDAC2
OUT4
BYPR2
OUT4
RMIX2
OUT4
RDAC2
OUT4
001
INPGA
UPDATE
NPPGAZCR INPPGA
MUTER
010
INPPGAVOLR
DACL2
RMIX
DACR2
LMIX
OUT4
BOOST
OUT3
BOOST
SPKR
BOOST
TSDEN
VROI
002
Table 60 WM8980 Register Map
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DIGITAL FILTER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
+/- 0.025dB
0
TYP
MAX
UNIT
ADC Filter
Passband
-6dB
0.454fs
0.5fs
Passband Ripple
+/- 0.025
Stopband
Stopband Attenuation
dB
0.546fs
f > 0.546fs
-60
Group Delay
dB
21/fs
ADC High Pass Filter
High Pass Filter Corner
Frequency
-3dB
3.7
-0.5dB
10.4
-0.1dB
21.6
Hz
DAC Filter
Passband
+/- 0.035dB
0
-6dB
0.454fs
0.5fs
Passband Ripple
+/-0.035
Stopband
Stopband Attenuation
Group Delay
dB
0.546fs
f > 0.546fs
-80
dB
29/fs
Table 61 Digital Filter Characteristics
TERMINOLOGY
1.
Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2.
Pass-band Ripple – any variation of the frequency response in the pass-band region
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DAC FILTER RESPONSES
0.2
0
0.15
0.1
Response (dB)
Response (dB)
-20
-40
-60
-80
0.05
0
-0.05
-0.1
-100
-0.15
-120
-0.2
0
0.5
1
1.5
2
2.5
3
0
0.1
Frequency (Fs)
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 34 DAC Digital Filter Frequency Response
Figure 35 DAC Digital Filter Ripple
ADC FILTER RESPONSES
0.2
0
0.15
0.1
Response (dB)
Response (dB)
-20
-40
-60
-80
0.05
0
-0.05
-0.1
-100
-0.15
-0.2
-120
0
0.5
1
1.5
2
Frequency (Fs)
Figure 36 ADC Digital Filter Frequency Response
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2.5
3
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 37 ADC Digital Filter Ripple
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HIGHPASS FILTER
The WM8980 has a selectable digital highpass filter in the ADC filter path. This filter has two
modes, audio and applications. In audio mode the filter is a 1st order IIR with a cut-off of around
3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cut-off
frequency.
5
0
-5
Response (dB)
-10
-15
-20
-25
-30
-35
-40
0
5
10
15
20
25
30
35
40
45
Frequency (Hz)
Figure 38 ADC Highpass Filter Response, HPFAPP=0
10
10
0
0
-10
-10
Response (dB)
Response (dB)
-20
-20
-30
-30
-40
-50
-40
-60
-50
-70
-80
-60
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
Frequency (Hz)
Frequency (Hz)
Figure 39 ADC Highpass Filter Responses (48kHz),
HPFAPP=1, all cut-off settings shown.
Figure 40 ADC Highpass Filter Responses (24kHz),
HPFAPP=1, all cut-off settings shown.
10
0
-10
Response (dB)
-20
-30
-40
-50
-60
-70
-80
-90
0
200
400
600
800
1000
1200
Frequency (Hz)
Figure 41 ADC Highpass Filter Responses (12kHz),
HPFAPP=1, all cut-off settings shown.
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5-BAND EQUALISER
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
The WM8980 has a 5-band equaliser which can be applied to either the ADC path or the DAC path.
The plots from Figure 42 to Figure 55 show the frequency responses of each filter with a sampling
frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of ±12dB, and
secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each
filter.
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
-15
-1
10
5
Figure 42 EQ Band 1 Low Frequency Shelf Filter Cut-offs
15
15
10
10
5
5
0
-5
-10
-10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 44 EQ Band 2 – Peak Filter Centre Frequencies,
EQ2BW=0
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
0
-5
-15
-1
10
10
Figure 43 EQ Band 1 Gains for Lowest Cut-off Frequency
Magnitude (dB)
Magnitude (dB)
0
-15
-1
10
Figure 45
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
EQ Band 2 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ2BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
Figure 46 EQ Band 2 – EQ2BW=0, EQ2BW=1
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15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
WM8980
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
-15
-1
10
Figure 47 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BFigure 48
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
EQ Band 3 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ3BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
Figure 49 EQ Band 3 – EQ3BW=0, EQ3BW=1
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WM8980
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
Product Preview
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
-15
-1
10
5
Figure 50 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BFigure 51
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
EQ Band 4 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ4BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
Figure 52 EQ Band 4 – EQ3BW=0, EQ3BW=1
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 53 EQ Band 5 High Frequency Shelf Filter Cut-offs
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-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 54 EQ Band 5 Gains for Lowest Cut-off Frequency
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Figure 55 shows the result of having the gain set on more than one channel simultaneously. The
blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show
the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the
peak filters.
20
15
Magnitude (dB)
10
5
0
-5
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 55 Cumulative Frequency Boost/Cut
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WM8980
APPLICATION INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 56 Recommended External Component Diagram
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PACKAGE DIAGRAM
FL: 40 PIN QFN PLASTIC PACKAGE 6 X 6 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DETAIL 1
D2
31
DM037.A
D
40
1
30
INDEX AREA
(D/2 X E/2)
4
A
E
E2
21
10
aaa C
2X
11
20
e
b
BOTTOM VIEW
1
bbb M C A B
aaa C
2X
TOP VIEW
ccc C
A3
AA
A
0.08 C
7
DD
CC
BB
A1
SIDE VIEW
C
5
DETAIL 2
SEATING PLANE
L
L1
W
T
A3
b
Exposed lead
Symbols
A
A1
A3
b
D
D2
E
E2
e
G
H
L
T
W
MIN
0.80
0
0.18
4.00
4.00
0.30
DETAIL 1
G
H
Half etch tie bar
DETAIL 2
Dimensions (mm)
NOM
MAX
0.90
1.00
0.02
0.05
0.20 REF
0.25
6.00 BSC
4.15
6.00 BSC
4.15
0.50 BSC
0.213
0.1
0.40
0.1
Dimensions (mm)
Symbols
NOTE
0.30
1
4.25
2
4.25
2
AA
BB
CC
DD
L1
MIN
0.235
0.235
0.181
0.181
0.03
NOM
MAX
NOTE
7
7
7
7
0.15
0.50
0.2
Tolerances of Form and Position
aaa
bbb
ccc
REF:
0.15
0.10
0.10
JEDEC, MO-220, VARIATION VJJD-2.
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC, MO-220, VARIATION VJJD-2.
3. ALL DIMENSIONS ARE IN MILLIMETRES.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002.
5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT.
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WM8980
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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