w WM8985 Multimedia CODEC with Class D Headphone and Line Out DESCRIPTION FEATURES The WM8985 is a low power, high quality, feature-rich stereo CODEC designed for portable multimedia applications that require low power consumption and high quality audio. Stereo CODEC: • DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz) • ADC SNR 92.5dB, THD -83dB (‘A’ weighted @ 48kHz) • Headphone driver with ‘capless’ option - 40mW/channel output power into 16Ω / 3.3V AVDD2 - Class D headphone driver - Class AB headphone / line Driver - PSRR 70dB at 217Hz • Stereo, mono or differential line output The device integrates preamps for stereo differential mics, and includes class D and class AB drivers for headphone and differential or stereo line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced DSP features include a 5-band equaliser, an ALC/limiter for the microphone or line input through the ADC and a digital playback limiter. Additional digital filtering options are available in the ADC path, to cater for application filtering such as ‘wind noise reduction’ and a programmable notch filter. Highly flexible mixers enable many new application features, with the option to record and playback any combination of voice, line inputs and digital audio such as FM Radio or MP3. The WM8985 digital audio interface can operate in master or slave mode, while an integrated PLL provides flexible clocking schemes. The WM8985 operates at analogue supply voltages from 2.5V to 3.3V, although the digital core can operate at voltages down to 1.71V to save power. Additional power management control enables individual sections of the chip to be powered down under software control. Mic Preamps: • Stereo differential or mono microphone interfaces • Programmable preamp gain • Pseudo differential inputs with common mode rejection • Programmable ALC / Noise Gate in ADC path • Low-noise bias supplied for electret microphones Other Features: • Enhanced 3-D function for improved stereo separation • Digital playback limiter • 5-band Equaliser (record or playback) • Programmable ADC High Pass Filter (wind noise reduction) • Programmable ADC Notch Filter • Aux inputs for stereo analog input signals or ‘beep’ • PLL supporting various clocks between 8MHz-50MHz • Sample rates supported (kHz): 8, 11.025, 16, 12, 16, 22.05, 24, 32, 44.1, 48 • Low power, low voltage • 2.5V to 3.6V analogue supplies • 1.71V to 3.6V digital supplies • 5x5mm 32-lead QFN package APPLICATIONS • • WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Portable audio player / FM radio Multimedia Mobile Handsets Production Data, July 2009, Rev 4.6 Copyright ©2009 Wolfson Microelectronics plc WM8985 Production Data BLOCK DIAGRAM w PD, Rev 4.6, July 2009 2 WM8985 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 2 PIN CONFIGURATION ........................................................................................... 5 ORDERING INFORMATION .................................................................................. 5 PIN DESCRIPTION ................................................................................................ 6 ABSOLUTE MAXIMUM RATINGS ......................................................................... 7 RECOMMENDED OPERATING CONDITIONS ..................................................... 7 ELECTRICAL CHARACTERISTICS ...................................................................... 8 TERMINOLOGY .......................................................................................................... 14 POWER CONSUMPTION .................................................................................... 15 AUDIO PATHS OVERVIEW ................................................................................. 16 SIGNAL TIMING REQUIREMENTS ..................................................................... 17 SYSTEM CLOCK TIMING ........................................................................................... 17 AUDIO INTERFACE TIMING – MASTER MODE ........................................................ 17 AUDIO INTERFACE TIMING – SLAVE MODE ............................................................ 18 CONTROL INTERFACE TIMING – 3-WIRE MODE .................................................... 19 CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 20 INTERNAL POWER ON RESET CIRCUIT .......................................................... 21 RECOMMENDED POWER UP/DOWN SEQUENCE .................................................. 23 DEVICE DESCRIPTION ....................................................................................... 27 INTRODUCTION ......................................................................................................... 27 INPUT SIGNAL PATH ................................................................................................. 28 ANALOGUE TO DIGITAL CONVERTER (ADC) .......................................................... 38 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 43 LIMITER MODE ........................................................................................................... 46 OUTPUT SIGNAL PATH ............................................................................................. 55 3D STEREO ENHANCEMENT .................................................................................... 62 ANALOGUE OUTPUTS............................................................................................... 63 DIGITAL AUDIO INTERFACES ................................................................................... 76 AUDIO SAMPLE RATES ............................................................................................. 81 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 81 COMPANDING ............................................................................................................ 83 GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 86 OUTPUT SWITCHING (JACK DETECT)..................................................................... 87 CONTROL INTERFACE .............................................................................................. 88 RESETTING THE CHIP .............................................................................................. 89 POWER SUPPLIES .................................................................................................... 89 POWER MANAGEMENT ............................................................................................ 90 POP MINIMISATION ................................................................................................... 91 REGISTER MAP................................................................................................... 92 REGISTER BITS BY ADDRESS ................................................................................. 94 DIGITAL FILTER CHARACTERISTICS ............................................................. 112 TERMINOLOGY ........................................................................................................ 112 DAC FILTER RESPONSES....................................................................................... 113 ADC FILTER RESPONSES....................................................................................... 113 HIGHPASS FILTER ................................................................................................... 114 5-BAND EQUALISER ................................................................................................ 115 w PD, Rev 4.6, July 2009 3 WM8985 Production Data APPLICATIONS INFORMATION ....................................................................... 119 RECOMMENDED EXTERNAL COMPONENTS ........................................................ 119 PACKAGE DIAGRAM ........................................................................................ 120 IMPORTANT NOTICE ........................................................................................ 121 ADDRESS: ................................................................................................................ 121 w PD, Rev 4.6, July 2009 4 WM8985 Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8985GEFL -40°C to +85°C 32-lead QFN (5 x 5 mm) (Pb-free) MSL1 260oC WM8985GEFL/R -40°C to +85°C 32-lead QFN (5 x 5 mm) (Pb-free, tape and reel) MSL1 260oC Note: Reel quantity = 3,500 w PD, Rev 4.6, July 2009 5 WM8985 Production Data PIN DESCRIPTION PIN NAME TYPE 1 LIP Analogue Input DESCRIPTION 2 LIN Analogue Input Left MIC pre-amp negative input 3 L2/GPIO2 Analogue Input Left channel line input/secondary mic pre-amp positive input/GPIO2 pin 4 RIP Analogue Input Right MIC pre-amp positive input 5 RIN Analogue Input Right MIC pre-amp negative input 6 R2/GPIO3 Analogue Input Right channel line input/secondary mic pre-amp positive input/GPIO3 pin 7 LRC Digital Input / Output DAC and ADC sample rate clock 8 BCLK Digital Input / Output Digital audio bit clock Left MIC pre-amp positive input 9 ADCDAT Digital Output 10 DACDAT Digital Input ADC digital audio data output DAC digital audio data input 11 MCLK Digital Input Master clock input 12 DGND Supply Digital ground 13 DCVDD Supply Digital core logic supply 14 DBVDD Supply 15 CSB/GPIO1 Digital Input / Output Digital buffer (I/O) supply 16 SCLK Digital Input 3-Wire control interface clock input / 2-wire control interface clock input 17 SDIN Digital Input / Output 3-Wire control interface data input / 2-Wire control interface data input 18 MODE Digital Input 19 AUXL Analogue Input Left auxiliary input 20 AUXR Analogue Input Right auxiliary input 21 OUT4 Analogue Output 22 OUT3 Analogue Output Left line output 23 ROUT2 Analogue Output Class D or class AB headphone output right 24 AGND2 Supply 25 LOUT2 Analogue Output 26 AVDD2 Supply 27 VMID Reference 28 AGND1 Supply 29 ROUT1 Analogue Output Class AB headphone or line output right 30 LOUT1 Analogue Output Class AB headphone or line output left 31 AVDD1 Supply 32 MICBIAS Analogue Output 3-Wire control interface chip Select / GPIO1 pin Control interface selection Right line output / mono mix output Analogue ground (ground reference for ROUT2/LOUT2 and OUT3/OUT4) Class D or class AB headphone output left Analogue supply (feeds output amplifiers ROUT2/LOUT2 and OUT3/OUT4) Decoupling for ADC and DAC reference voltage Analogue ground (ground reference for all input amplifiers, PLL, ADC and DAC, internal bias circuits, output amplifiers LOUT1, ROUT1) Analogue supply (feeds all input amplifiers, PLL, ADC and DAC, internal bias circuits, output amplifiers LOUT1, LOUT2)) Microphone bias Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. Refer to the application note WAN_0118 on “Guidelines on How to Use QFN Packages and Create Associated PCB Footprints”. w PD, Rev 4.6, July 2009 6 WM8985 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX -0.3V +4.5V Voltage range digital inputs DGND -0.3V DBVDD +0.3V Voltage range analogue inputs AGND1 -0.3V AVDD1 +0.3V Operating Temperature Range -40°C +85°C DBVDD, DCVDD, AVDD1, AVDD2 supply voltages Storage temperature prior to soldering 30°C max / 85% RH max Storage temperature after soldering -65°C +150°C Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. 2. All digital and analogue supplies are internally independent (i.e. not connected). 3. Analogue supply voltages AVDD1 and AVDD2 should be greater than or equal to the DCVDD digital supply voltage. 4. DBVDD must be greater than or equal to DCVDD. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Digital supply range (Core) DCVDD 1.711,2 3.6 V Digital supply range (Buffer) DBVDD 1.712 3.6 V AVDD1, AVDD2 2.51 Analogue supply range Ground TEST CONDITIONS DGND, AGND1, AGND2 MIN TYP MAX 3.6 0 UNIT V V Notes: 1. Analogue supply voltages should not be less than digital supply voltages. 2. DBVDD must be greater than or equal to DCVDD. w PD, Rev 4.6, July 2009 7 WM8985 Production Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Microphone Input PGA Inputs (LIP, LIN, RIP, RIN, L2, R2) INPPGAVOLL, INPPGAVOLR, PGABOOSTL and PGABOOSTR = 0dB Full-scale Input Signal Level – Single-ended input via LIN/RIN 1 AVDD/3.3 Vrms Full-scale Input Signal Level – Pseudo-differential input 1,2 AVDD*0.7/ 3.3 Vrms INPPGAVOLL/R = +35.25dB No input signal 0 to 20kHz 150 μV LIN, RIN input resistance INPPGAVOLL and INPPGAVOLR = +35.25dB 1.6 kΩ LIN, RIN input resistance INPPGAVOLL and INPPGAVOLR = 0dB 46 kΩ LIN, RIN input resistance INPPGAVOLL and INPPGAVOLR = -12dB 71 kΩ LIP, RIP input resistance Input PGA equivalent input noise All gain settings 90 kΩ L2, R2 input resistance L2_2INPPGA and R2_2INPPGA = 1 L2_2BOOSTVOL and R2_2BOOSTVOL = 000 90 kΩ L2, R2 input resistance L2_2INPPGA and R2_2INPPGA = 0 L2_2BOOSTVOL and R2_2BOOSTVOL = +6dB 11 kΩ L2, R2 input resistance L2_2INPPGA and R2_2INPPGA = 0 L2_2BOOSTVOL and R2_2BOOSTVOL = 0dB 22 kΩ L2, R2 input resistance L2_2INPPGA and R2_2INPPGA = 0 L2_2BOOSTVOL and R2_2BOOSTVOL = -12dB 60 kΩ Input Capacitance All analogue input pins 10 pF Maximum Input PGA Programmable Gain Gain adjusted by INPPGAVOLL and INPPGAVOLL +35.25 dB Minimum Input PGA Programmable Gain Gain adjusted by INPPGAVOLL and INPPGAVOLL -12 dB Guaranteed monotonic 0.75 dB INPPGAMUTEL and INPPGAMUTER = 1 100 dB Input Gain Boost PGABOOSTL and PGABOOSTR = 0 0 dB Input Gain Boost PGABOOSTL and PGABOOSTR = 1 +20 dB Programmable Gain Step Size Input PGA Mute Attenuation w PD, Rev 4.6, July 2009 8 WM8985 Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Auxiliary Analogue Inputs (AUXL, AUXR) Full-scale Input Signal Level 2 Input Resistance Input Capacitance AVDD/3.3 Vrms Left Input boost and mixer enabled, at +6dB 11 kΩ Left Input boost and mixer enabled, at 0dB gain 22 kΩ Left Input boost and mixer enabled, at -12dB gain 60 kΩ Right Input boost, mixer enabled, at +6dB gain 11 kΩ Right Input boost, mixer enabled, at 0dB gain 22 kΩ Right Input boost, mixer enabled, at -12dB gain 60 kΩ All analogue Inputs 10 pF Maximum Gain from AUXL and AUXR input to left and right input PGA mixers Gain adjusted by AUXL2BOOSTVOL and AUXR2BOOSTVOL +6 dB Minimum Gain from AUXL and AUXR input to left and right input PGA mixers Gain adjusted by AUXL2BOOSTVOL and AUXR2BOOSTVOL -12 dB AUXLBOOSTVOL and AUXRBOOSTVOL step size Guaranteed monotonic 3 dB Maximum Gain from L2/R2 input to left and right input PGA mixers Gain adjusted by L2_2BOOSTVOL and R2_2BOOSTVOL +6 dB Minimum Gain from L2/R2 input to left and right input PGA mixers Gain adjusted by L2_2BOOSTVOL and R2_2BOOSTVOL -12 dB L2, R2 Line Input Programmable Gain L2/R2_2BOOSTVOL step size Guaranteed monotonic L2/R2_2BOOSTVOL mute attenuation 3 dB 100 dB OUT4 to left or right input boost record path Maximum Gain into left and right input PGA mixers Gain adjusted by OUT4_2ADCVOL +12 dB Minimum Gain into left and right input PGA mixers Gain adjusted by OUT4_2ADCVOL -6 dB OUT4_2ADCVOL gain step size Guaranteed monotonic 3 dB 100 dB OUT4_2ADCVOL mute attenuation Analogue to Digital Converter (ADC) - Input from LIN/P and RIN/P in differential configuration to input PGA INPPGAVOLL, INPPGAVOLR, PGABOOSTL, PGABOOSTR, ADCLVOL and ADCRVOL = 0dB Signal to Noise Ratio 3 w SNR A-weighted AVDD1=AVDD2=3.3V 92.5 dB A-weighted AVDD1=AVDD2=2.5V 91.5 dB 22Hz to 20kHz AVDD1=AVDD2=3.3V 90 dB 22Hz to 20kHz AVDD1=AVDD2=2.5V 90 dB PD, Rev 4.6, July 2009 9 WM8985 Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 SYMBOL TEST CONDITIONS TYP MAX UNIT THD -7dBV Input AVDD1=AVDD2=3.3V -75 -70 dB -7dBV Input AVDD1=AVDD2=2.5V -75 -7dBV Input AVDD1=AVDD2=3.3V -72 -7dBV Input AVDD1=AVDD2=2.5V -72 dB 1kHz full scale input signal 100 dB THD+N Channel Separation 6 MIN dB -68 dB Analogue to Digital Converter (ADC) - Input from L2, R2 into left and right PGA mixer. INPPGAVOLL, INPPGAVOLR, L2_2BOOSTVOL, R2_2BOOSTVOL, ADCLVOL and ADCRVOL = 0dB Signal to Noise Ratio 3 SNR Total Harmonic Distortion 4 THD Total Harmonic Distortion + Noise 5 THD+N Channel Separation 6 A-weighted AVDD1=AVDD2=3.3V 85 92.5 dB A-weighted AVDD1=AVDD2=2.5V 92.5 dB 22Hz to 20kHz AVDD1=AVDD2=3.3V 90 dB 22Hz to 20kHz AVDD1=AVDD2=2.5V 90 dB -1dBV Input AVDD1=AVDD2=3.3V -83 -1dBV Input AVDD1=AVDD2=2.5V -66 -1dBV Input AVDD1=AVDD2=3.3V -81 -1dBV Input AVDD1=AVDD2=2.5V -65 dB 1kHz input signal 100 dB AVDD1/3.3 Vrms 98 dB A-weighted AVDD1=AVDD2=2.5V 96 dB 22Hz to 20kHz AVDD1=AVDD2=3.3V 95.5 dB 22Hz to 20kHz AVDD1=AVDD2=2.5V 93.5 dB 0dBFS input AVDD1=AVDD2=3.3V -84 0dBFS input AVDD1=AVDD2=2.5V -84 0dBFS input AVDD1=AVDD2=3.3V -82 0dBFS input AVDD1=AVDD2=2.5V -82 dBFS 1kHz signal 100 dB -78 dB dB -70 dB DAC to left and right mixers into 10kΩ / 50pF load on LOUT1 and ROUT1 LOUT1VOL, ROUT1VOL, DACLVOL and DACRVOL = 0dB Full-scale output 1 LOUT1VOL and ROUTVOL = 0dB Signal to Noise Ratio 3 SNR Total Harmonic Distortion 4 Total Harmonic Distortion + Noise Channel Separation 6 w THD 5 THD+N A-weighted AVDD1=AVDD2=3.3V 92 -80 dBFS dBFS -78 dBFS PD, Rev 4.6, July 2009 10 WM8985 Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to L/R mixer into 10kΩ / 50pF load on L/ROUT2, class AB mode LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL = 0dB Full-scale output 1 Signal to Noise Ratio 3 SNR Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 THD THD+N Channel Separation 6 LOUT2VOL and ROUT2VOL = 0dB AVDD1/3.3 Vrms A-weighted AVDD1=AVDD2=3.3V 100 dB A-weighted AVDD1=AVDD2=2.5V 96 dB 22Hz to 20kHz AVDD1=AVDD2=3.3V 95.5 dB 22Hz to 20kHz AVDD1=AVDD2=2.5V 93.5 dB 0dBFS input AVDD1=AVDD2=3.3V -84 dBFS 0dBFS input AVDD1=AVDD2=2.5V -82 dBFS 0dBFS input AVDD1=AVDD2=3.3V -82 dBFS 0dBFS input AVDD1=AVDD2=2.5V -80 dBFS 1kHz input signal 100 dB DAC to OUT3 and OUT4 mixers into OUT3/OUT4 outputs into (10kΩ / 50pF load. DACVOLL and DACVOLR = 0dB) Full-scale output voltage Signal to Noise Ratio 3 Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 AVDD2/3.3 Vrms SNR A-weighted AVDD1=AVDD2=3.3V 98 dB THD full-scale signal AVDD1=AVDD2=3.3V -84 dBFS THD+N full-scale signal AVDD1=AVDD2=3.3V -82 dBFS 1kHz signal 100 dB Channel Separation 6 DAC to left and right mixer into headphone 16Ω load on LOUT1 and ROUT1 LOUT1VOL, ROUT1VOL, DACLVOL and DACRVOL = 0dB Full-scale output Signal to Noise Ratio 3 Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 Channel Separation 6 w AVDD1/3.3 Vrms A-weighted AVDD1=AVDD2=3.3V 100 dB 22Hz to 20kHz AVDD1=AVDD2=3.3V 95.5 dB THD Po = 20mW, RL=16Ω -79 dB THD+N Po = 20mW, RL=16Ω -75 dB 1kHz signal 100 dB SNR PD, Rev 4.6, July 2009 11 WM8985 Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to left and right mixer into headphone 16Ω load on LOUT2 and ROUT2, Class AB mode LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL = 0dB Full-scale output Signal to Noise Ratio 3 Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 Channel Separation AVDD1/3.3 Vrms 97 dB 22Hz to 20kHz AVDD1=AVDD2=3.3V 95.5 dB THD Po = 20mW, RL=16Ω -80 -75 dB THD+N Po = 20mW, RL=16Ω -77 -70 dB 1kHz signal 100 SNR A-weighted AVDD1=AVDD2=3.3V 6 90 dB DAC to left and right mixer into headphone 16Ω load on LOUT2 and ROUT2, Class D mode, Lfilter = 33uH Cfilter = 220nf LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL = 0Db Full-scale output AVDD1/3.3 Vrms 97 dB Signal to Noise Ratio 3 SNR A-weighted AVDD1=AVDD2=3.3V Total Harmonic Distortion 4 THD Po = 20mW, RL=16Ω -79 1kHz signal Channel Separation 6 90 -75 dB 100 dB PWM Rise Time 1.5 ns PWM Fall Time 1.5 ns DCLKDIV = 1000 1.4 MHz RL = 16Ω, tPW = 20ns, PO = 20mW 72 % 100mVpp ripple @217Hz injected on AVDD2 70 dB No analogue output signal on either channel 0.5 mA PWM Switching Frequency Efficiency Power Supply Rejection Idle Current PSRR Bypass paths to left and right output mixers. BYPL2LMIX = 1 and BYPR2RMIX = 1 Maximum PGA gain into mixer Gain adjusted by BYPLMIXVOL and BYPRMIXVOL +6 dB Minimum PGA gain into mixer Gain adjusted by BYPLMIXVOL and BYPRMIXVOL -15 dB Guaranteed monotonic 3 dB BYPL2LMIX = 0 BYPR2RMIX = 0 100 dB Maximum Programmable Gain Gain adjusted by L/ROUT1VOL and L/ROUT2VOL +6 dB Minimum Programmable Gain Gain adjusted by L/ROUT1VOL and L/ROUT2VOL -57 dB Programmable Gain step size Guaranteed monotonic 1 dB Mute attenuation 1kHz, full scale signal L/ROUT1MUTE = 1 L/ROUT2MUTE = 1 85 dB BYPLMIXVOL and BYPRMIXVOL gain step into mixer Mute attenuation Analogue outputs (LOUT1, ROUT1, LOUT2, ROUT2) w PD, Rev 4.6, July 2009 12 WM8985 Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT LIN and RIN input PGA to input boost stage into 10kΩ / 50pF load on OUT3/OUT4 outputs INPPGAVOLL, INPPGAVOLR, PGABOOSTL and PGABOOSTR = 0dB Full-scale output voltage, 0dB gain Signal to Noise Ratio 3 Total Harmonic Distortion SNR 4 Total Harmonic Distortion + Noise 5 THD THD+N AVDD2/3.3 Vrms 98 dB A-weighted AVDD1=AVDD2=2.5V 96 dB 22Hz to 22kHz AVDD1=AVDD2=3.3V 95.5 dB 22Hz to 22kHz AVDD1=AVDD2=2.5V 93.5 dB full-scale signal AVDD1=AVDD2=3.3V -84 dBFS full-scale signal AVDD1=AVDD2=2.5V -82 dBFS full-scale signal AVDD1=AVDD2=3.3V -82 dBFS full-scale signal AVDD1=AVDD2=2.5V -80 dBFS 100 dB AVDD1/3.3 Vrms 100 dB A-weighted AVDD1=AVDD2=2.5V 96 dB 22Hz to 22kHz AVDD1=AVDD2=3.3V 95.5 dB 22Hz to 22kHz AVDD1=AVDD2=2.5V 93.5 dB full-scale signal AVDD1=AVDD2=3.3V -87 full-scale signal AVDD1=AVDD2=2.5V -69 full-scale signal AVDD1=AVDD2=3.3V -85 full-scale signal AVDD1=AVDD2=2.5V -68 dBFS 1kHz full scale signal 100 dB A-weighted AVDD1=AVDD2=3.3V 90 Channel Separation 6 LIN and RIN into input PGA Bypass to LOUT1 and ROUT1 into 16Ω / 50pF loads BYPLMIXVOL, BYPRMIXVOL, LOUT1VOL and ROUT1VOL = 0dB Full-scale output voltage, 0dB gain Signal to Noise Ratio 3 Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 Channel separation 6 SNR THD THD+N A-weighted AVDD1=AVDD2=3.3V 90 -75 dBFS dBFS -73 dBFS Microphone Bias Bias Voltage MBVSEL=0 0.9*AVDD1 V MBVSEL=1 0.65*AVDD1 V Bias Current Source for VMICBIAS within +/-3% Output Noise Voltage 1kHz to 20kHz w 3 15 mA nV/√Hz PD, Rev 4.6, July 2009 13 WM8985 Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Input / Output Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH Output LOW Level VOL Input Capacitance Input leakage 0.7×DBV DD V 0.3×DBVDD IOL=1mA 0.9×DBV DD V IOH-1mA All digital pins V 0.1xDBVDD V 10 pF 50 pA TERMINOLOGY 1. 2. 3. 4. 5. 6. Full-scale input and output levels scale in relation to AVDD1 or AVDD2 depending upon the input or output used. For example, when AVDD1 = 3.3V, 0dBFS = 1Vrms (0dBV). When AVDD < 3.3V the absolute level of 0dBFS will decrease with a linear relationship to AVDD. Input level to RIP and LIP in differential configurations is limited to a maximum of -3dB or performance will be reduced. Signal-to-noise ratio (dBFS) – SNR is the difference in level between a reference full scale output signal and the device output with no signal applied. This ratio is also called idle channel noise. (No Auto-zero or Automute function is employed in achieving these results). Total Harmonic Distortion (dB) – THD is the difference in level between a reference output signal and the first seven harmonics of the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the next seven harmonics is calculated. Total Harmonic Distortion plus Noise (dB) – THD+N is the difference in level between a reference output signal and the sum of the harmonics, wide-band noise and interference on the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the total harmonics, wide-band noise and interference is calculated. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. w PD, Rev 4.6, July 2009 14 WM8985 Production Data POWER CONSUMPTION Typical power consumption for various scenarios is shown below. DBVDD(V) DBVDD(mA) AVDD1(V) AVDD1(mA) AVDD2(V) AVDD2(mA) Total (mW) 1.8 0.0002 1.8 0.0002 1.8 0.0002 3.3 0.006 3.6 0.008 1.8 3.3 3.3 3.3 3.6 0 0 0 0 0 2.5 3 3.3 3.3 3.6 0.01 0.011 0.012 0.011 0.012 2.5 3 3.3 3.3 3.6 0 0 0 0 0 0.03 0.03 0.04 0.06 0.07 Standby mode (Lowest Power) 1.8 1.8 1.8 3.3 3.6 0.002 0.002 0.002 0.006 0.008 1.8 3.3 3.3 3.3 3.6 0 0 0 0 0 2.5 3 3.3 3.3 3.6 0.117 0.138 0.149 0.149 0.157 2.5 3 3.3 3.3 3.6 0 0 0 0 0 0.30 0.42 0.50 0.51 0.59 DAC Playback 32Ω load L/ROUT2 - Class AB Mode fs=44.1kHz 1.8 1.8 3.3 3.6 3.336 3.336 7.182 8.098 1.8 0.003 3.3 0.0021 3.3 0.0021 3.6 0.025 2.5 3 3.3 3.6 2.238 2.728 3.025 3.325 2.5 3 3.3 3.6 0.28 0.35 0.39 0.44 12.31 15.24 34.98 42.80 ADC Stereo Line Record fs=44.1kHz 1.8 1.8 3.3 3.6 3.57 3.57 7.603 8.529 1.8 3.3 3.3 3.6 2.5 2.7 3 3.3 4.76 4.967 5.272 5.578 2.5 3 3.3 3.6 0 0 0 0 18.35 19.88 40.99 49.21 Description Off (Default Settings) DCVDD(V) DCVDD(mA) All measurements are made with quiescent signal. 0.013 0.013 0.026 0.027 Table 1 Power Consumption Contact Wolfson for more information on device power consumption. w PD, Rev 4.6, July 2009 15 WM8985 Production Data AUDIO PATHS OVERVIEW Figure 1 Audio Paths Overview w PD, Rev 4.6, July 2009 16 WM8985 Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING tMCLKL MCLK tMCLKH tMCLKY Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA = +25oC, Slave Mode PARAMETER SYMBOL CONDITIONS MIN TMCLKY MCLK=SYSCLK (=256fs) 81.38 MCLK input to PLL Note 1 20 TYP MAX UNIT System Clock Timing Information MCLK cycle time MCLK duty cycle TMCLKDS 60:40 ns ns 40:60 Note: 1. PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz. AUDIO INTERFACE TIMING – MASTER MODE Figure 3 Digital Audio Data Timing – Master Mode (see Control Interface) w PD, Rev 4.6, July 2009 17 WM8985 Production Data Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, MCLK=256fs, 24-bit data, unless otherwise stated. TA=+25oC, PARAMETER MIN SYMBOL Master TYP Mode, fs=48kHz, MAX UNIT ns Audio Data Input Timing Information LRC propagation delay from BCLK falling edge tDL 10 ADCDAT propagation delay from BCLK falling edge tDDA 15 DACDAT setup time to BCLK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns ns AUDIO INTERFACE TIMING – SLAVE MODE Figure 4 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRC set-up time to BCLK rising edge tLRSU 10 ns LRC hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns DACDAT set-up time to BCLK rising edge tDs 10 ADCDAT propagation delay from BCLK falling edge tDD ns 15 ns Note: BCLK period should always be greater than or equal to MCLK period. w PD, Rev 4.6, July 2009 18 WM8985 Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. Figure 5 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions o DCVDD = 1.8V, DBVDD = AVDD1 = AVDD2 = 3.3V, DGND = AGND1 = AGND2 = 0V, TA=+25 C, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 80 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDIN to SCLK set-up time tDSU 40 ns SCLK to SDIN hold time tDHO 40 ns CSB pulse width low tCSL 40 ns CSB pulse width high tCSH 40 ns CSB rising to SCLK rising tCSS 40 ns tps 0 Pulse width of spikes that will be suppressed w 5 ns PD, Rev 4.6, July 2009 19 WM8985 Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. t3 t3 t5 SDIN t4 t6 t2 t8 SCLK t1 t9 t7 Figure 6 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, MCLK = 256fs, 24-bit data, unless otherwise stated. TA=+25oC, PARAMETER SYMBOL MIN SCLK Low Pulse-Width t1 1.3 us SCLK High Pulse-Width t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 SDIN, SCLK Rise Time t6 300 SDIN, SCLK Fall Time t7 300 Setup Time (Stop Condition) t8 Slave TYP Mode, fs=48kHz, MAX UNIT 526 kHz Program Register Input Information SCLK Frequency 0 Data Hold Time t9 Pulse width of spikes that will be suppressed tps w ns 600 0 ns ns ns 900 ns 5 ns PD, Rev 4.6, July 2009 20 WM8985 Production Data INTERNAL POWER ON RESET CIRCUIT Figure 7 Internal Power on Reset Circuit Schematic The WM8985 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1 and monitors DCVDD. It asserts PORB low if AVDD1 or DCVDD is below a minimum threshold. Figure 8 Typical Power up Sequence where AVDD1 is Powered before DCVDD Figure 8 shows a typical power-up sequence where AVDD1 comes up first. When AVDD1 goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD1 is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD1 falls first, PORB is asserted low whenever AVDD1 drops below the minimum threshold Vpora_off. w PD, Rev 4.6, July 2009 21 WM8985 Production Data Figure 9 Typical Power up Sequence where DCVDD is Powered before AVDD1 Figure 9 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD1 goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD1 rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the minimum threshold Vpord_off. SYMBOL MIN TYP MAX UNIT Vpora 0.4 0.6 0.8 V Vpora_on 0.9 1.2 1.6 V Vpora_off 0.4 0.6 0.8 V Vpord_on 0.5 0.7 0.9 V Vpord_off 0.4 0.6 0.8 V Table 2 Typical POR Operation (Typical Simulated Values) Notes: w 1. If AVDD1 and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. 2. The chip will enter reset at power down when AVDD1 or DCVDD falls below Vpora_off or Vpord_off. This may be important if the supply is turned on and off frequently by a power management system. 3. The minimum tpor period is maintained even if DCVDD and AVDD1 have zero rise time. This specification is guaranteed by design rather than test. PD, Rev 4.6, July 2009 22 WM8985 Production Data RECOMMENDED POWER UP/DOWN SEQUENCE In order to minimise output pop and click noise, it is recommended that the WM8985 device is powered up and down under control using the following sequences: Power Up: 1. Turn on external power supplies. Wait for supply voltage to settle. 2. Set low analogue bias mode, BIASCUT = 1 3. Enable thermal shutdown TSDEN = TSOPCTRL = 1 4. Enable Internal bias BIASEN = 1. 5. Mute all outputs and set PGAs to minimum gain, R52 to R57 = 0x140h. 6. Enable VMID independent current bias, POBCTRL = 1. 7. Enable required outputs, DACs and mixers. 8. Enable VMID with required charge time e.g. VMIDSEL=01. 9. Wait 500ms 1 10. Setup digital interface, input amplifiers, PLL, ADCs and DACs for desired operation. 11. Disable VMID independent current bias, POBCTRL = 0. 12. Unmute L/ROUT1 and set desired volume, e.g. for 0dB R52 and R53 = 0x139h. 13. Unmute L/ROUT2 and set desired volume, e.g. for 0dB R54 and R55 = 0x139h. Power Down 2: 1. Disable Thermal shutdown, TSDEN = TSOPCTRL = 0 2. Disable VMIDSEL=00 and BIASEN=0 3. Wait for VMID to discharge 3 4. Power off registers R1, R2, R3 = 0x000h 5. Remove external power supplies Notes: w 1. Charging time constant is determined by impedance selected by VMIDSEL and the value of decoupling capacitor connected to VMID pin. 2. It is possible to interrupt the power down sequence and power up to VMID before the allocated VMID discharge time. This is done by following the power-up sequence omitting steps 4 to 8. 3. Discharge time constant is determined by the values of analogue output capacitors. PD, Rev 4.6, July 2009 23 WM8985 Production Data Figure 10 ADC Power Up and Down Sequence (not to scale) SYMBOL MIN TYPICAL MAX UNIT tmidrail_on 300 tmidrail_off >6 ms s tadcint 2/fs n/fs ADC Group Delay 29/fs n/fs Table 3 Typical POR Operation (Typical Simulated Values) w PD, Rev 4.6, July 2009 24 WM8985 Production Data Notes: 1. The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD1 power supply rise time. 2. The analogue input pin discharge time, tmidrail_off, is determined by the analogue input coupling capacitor discharge time. The time, tmidrail_off, is measured using a 1μF capacitor on the analogue input but will vary dependent upon the value of input coupling capacitor. 3. While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system noise but no significant digital output will be present. 4. The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for normal ADC operation. 5. ADCDAT data output delay from power up - with power supplies starting from 0V - is determined primarily by the VMID charge time. ADC initialisation and power management bits may be set immediately after POR is released; VMID charge time will be significantly longer and will dictate when the device is stabilised for analogue input. 6. ADCDAT data output delay at power up from device standby (power supplies already applied) is determined by ADC initialisation time, 2/fs. Figure 11 DAC Power Up and Down Sequence (not to scale) w PD, Rev 4.6, July 2009 25 WM8985 Production Data SYMBOL MIN TYPICAL MAX UNIT tline_midrail_on 300 tline_midrail_off >6 ms s thp_midrail_on 300 ms thp__midrail_off >6 s tdacint 2/fs n/fs DAC Group Delay 29/fs n/fs Table 4 Typical POR Operation (Typical Simulated Values) Notes: w 1. The lineout charge time, tline_midrail_on, is determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD1 power supply rise time. The values above were measured using a 4.7μF capacitor. 2. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute function has been applied to the signal beforehand. 3. The lineout discharge time, tline_midrail_off, is determined by the VMID pin discharge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance. The values above were measured using a 4.7μF capacitor. 4. The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD1 power supply rise time. The values above were measured using a 4.7μF VMID decoupling capacitor. 5. The headphone discharge time, thp_midrail_off, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance. The values above were measured using a 4.7μF VMID decoupling capacitor. 6. The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for normal DAC operation. PD, Rev 4.6, July 2009 26 WM8985 Production Data DEVICE DESCRIPTION INTRODUCTION The WM8985 is a low power audio CODEC combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. FEATURES The chip offers great flexibility in use, and so can support many different modes of operation as follows: MICROPHONE INPUTS Two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be pseudo-differentially connected, with user defined gain. The provision of the common mode input pin for each stereo input allows for rejection of common mode noise on the microphone inputs (level depends on gain setting chosen). A microphone bias is output from the chip which can be used to bias both microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected. PGA AND ALC OPERATION A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant. AUXILIARY ANALOG LINE INPUTS (AUXL, AUXR) The inputs, AUXL and AUXR, can be used as a stereo line input or as an input for warning tones (or ‘beeps’) etc. These inputs can be summed into the record paths, along with the microphone preamp outputs, so allowing for mixing of audio with ‘backing music’ etc as required. Additional stereo analog signals might be connected to the Line inputs of WM8985 (e.g. melody chip or FM radio), and the stereo signal listened to via headphones, or recorded, simultaneously if required. ADC The stereo ADC uses a 24-bit high-order over sampling architecture to deliver optimum performance with low power consumption. HI-FI DAC The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type applications, including MP3 players and portable disc players of all types. OUTPUT MIXERS Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to allow for all possible signal combinations. w PD, Rev 4.6, July 2009 27 WM8985 Production Data OUT3 and OUT4 can be configured to provide an additional stereo or mono differential lineout from the output of the DACs, the mixers or the input microphone boost stages. They can also provide a midrail reference for pseudo differential inputs to external amplifiers. AUDIO INTERFACES The WM8985 has a standard audio interface, to support the transmission of stereo data to and from the chip. This interface is a 3 wire standard audio interface which supports a number of audio data formats including: 2 • IS • DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words are transmitted) • MSB-First, left justified • MSB-First, right justified The interface can operate in master or slave modes. CONTROL INTERFACES To allow full software control over all features, the WM8985 offers a choice of 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Selection of the mode is via the MODE pin. In 2 wire mode, the address of the device is fixed as 0011010. CLOCKING SCHEMES WM8985 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC and ADC. A flexible clock divider allows the 256fs DAC clock to be generated from a range of input clock frequencies, for example, 256fs, 384fs, 512fs and 768fs. A PLL is included which may be used to generate these clocks in the event that they are not available from the system controller. This PLL can accept a range of common input clock frequencies between 8MHz and 50MHz to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the GPIO1 pin and used elsewhere in the system; available in 2-wire control mode only. POWER CONTROL The design of the WM8985 has given much attention to power consumption without compromising performance. The WM8985 operates at low analog and digital supply voltages, and includes the ability to power off any unused parts of the circuitry under software control. It also includes standby and power off modes. INPUT SIGNAL PATH The WM8985 has a number of flexible analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to accommodate single-ended, pseudo-differential or dual differential microphones. There are two auxiliary input pins which can be fed into to the input boost/mix stage as well as driving into the output path. A bypass path exists from the output of the boost/mix stage into the output left/right mixers. MICROPHONE INPUTS The WM8985 can accommodate a variety of microphone configurations including single ended and pseudo-differential inputs. The inputs to the left differential input PGA are LIN, LIP and L2. The inputs to the right differential input PGA are RIN, RIP and R2. In single-ended microphone input configuration the microphone signal should be input to LIN or RIN and the non-inverting input of the input PGA clamped to VMID. w PD, Rev 4.6, July 2009 28 WM8985 Production Data Figure 12 Microphone Input PGA Circuit The input PGAs are enabled by the INPPGAENL and INPPGAENR register bits. REGISTER ADDRESS R2 (02h) Power Management 2 BIT LABEL DEFAULT DESCRIPTION 2 INPPGAENL 0 Left channel input PGA enable 0 = disabled 1 = enabled 3 INPPGAENR 0 Right channel input PGA enable 0 = disabled 1 = enabled Table 5 Input PGA Enable Register Settings w PD, Rev 4.6, July 2009 29 WM8985 Production Data REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R44 (2Ch) Input Control 0 LIP2INPPGA 1 Connect LIP pin to left channel input PGA amplifier positive terminal. 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) 1 LIN2INPPGA 1 Connect LIN pin to left channel input PGA negative terminal. 0 = LIN not connected to input PGA 1 = LIN connected to input PGA amplifier negative terminal. 2 L2_2INPPGA 0 Connect L2 pin to left channel input PGA positive terminal. 0 = L2 not connected to input PGA 1 = L2 connected to input PGA amplifier positive terminal (constant input impedance). 4 RIP2INPPGA 1 Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) 5 RIN2INPPGA 1 Connect RIN pin to right channel input PGA negative terminal. 0 = RIN not connected to input PGA 1 = RIN connected to right channel input PGA amplifier negative terminal. 6 R2_2INPPGA 0 Connect R2 pin to right channel input PGA positive terminal. 0 = R2 not connected to input PGA 1 = R2 connected to input PGA amplifier positive terminal (constant input impedance). Table 6 Input PGA Control INPUT PGA VOLUME CONTROLS The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the LIN/RIN input to the PGA output and from the L2/R2 amplifier to the PGA output are always common and controlled by the register bits INPPGAVOLL[5:0] and INPPGABVOLR[5:0]. These register bits also affect the LIP pin when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1, the RIP pin when RIP2INPPGA=1 and the L2 pin when L2_2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled automatically and the INPPGAVOLL and INPPGAVOLR bits should not be used. w PD, Rev 4.6, July 2009 30 WM8985 Production Data REGISTER ADDRESS BIT R45 (20h) Left channel input PGA volume control 5:0 INPPGAVOLL 010000 (0dB) Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB 6 INPPGAMUTEL 0 Mute control for left channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input BOOST stage). 7 INPPGAZCL 0 Left channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. 8 INPPGAVU Not latched INPPGA left and INPPGA right volume do not update until a 1 is written to INPPGAVU (in reg 45 or 46) (See "Volume Updates" below) 5:0 INPPGAVOLR 010000 (0dB) Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB 6 INPPGAMUTER 0 Mute control for right channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input BOOST stage). 7 INPPGAZCR 0 Right channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. 8 INPPGAVU Not latched INPPGA left and INPPGA right volume do not update until a 1 is written to INPPGAVU (in reg 45 or 46) (See "Volume Updates" below) 8:7 ALCSEL 00 ALC function select: 00 = ALC off 01 = ALC right only 10 = ALC left only 11 = ALC both on R46 (2Eh) Right channel input PGA volume control R32 (20h) ALC control 1 LABEL DEFAULT DESCRIPTION Table 7 Input PGA Volume Control w PD, Rev 4.6, July 2009 31 WM8985 Production Data VOLUME UPDATES Volume settings will not be applied to the PGAs until a '1' is written to one of the INPPGAVU bits. This is to allow left and right channels to be updated at the same time, as shown in Figure 13. Figure 13 Simultaneous Left and Right Volume Updates If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in Figure 14. Figure 14 Click Noise during Volume Update In order to prevent this click noise, a zero cross function is provided. When enabled, this will cause the PGA volume to update only when a zero crossing occurs, minimising click noise as shown in Figure 15. w PD, Rev 4.6, July 2009 32 WM8985 Production Data Figure 15 Volume Update using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8985 will automatically update the volume. The volume updates will occur between one and two timeout periods, depending on when the INPPGAVU bit is set as shown in Figure 16. Figure 16 Volume Update after Timeout w PD, Rev 4.6, July 2009 33 WM8985 Production Data AUXILLIARY INPUTS There are two auxiliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs or as a ‘beep’ input signal to be mixed with the outputs. The AUXL/R inputs can be used as a line input to the input BOOST stage which has adjustable gain of -12dB to +6dB in 3dB steps, with an additional "off" state (i.e. not connected to ADC input). See the INPUT BOOST section for further details. The AUXL/R inputs can also be mixed into the output channel mixers, with a gain of -15dB to +6dB plus off. INPUT BOOST Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the L2/R2 input pin (can be used as a line input, bypassing the input PGA). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 17. Figure 17 Input Boost Stage w PD, Rev 4.6, July 2009 34 WM8985 Production Data The input PGA paths can have a +20dB boost (PGABOOSTL/R=1), a 0dB pass through (PGABOOSTL/R=0) or be completely isolated from the input boost circuit (INPPGAMUTEL/R=1). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R47 (2Fh) Left Input BOOST control 8 PGABOOSTL 1 Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. R48 (30h) Right Input BOOST control 8 PGABOOSTR 1 Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Table 8 Input BOOST Stage Control The Auxiliary amplifier path to the BOOST stages is controlled by the AUXL2BOOSTVOL[2:0] and AUXR2BOOSTVOL[2:0] register bits. When AUXL2BOOSTVOL/AUXR2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. The L2/R2 path to the BOOST stage is controlled by the LIP2BOOSTVOL[2:0] and the RIP2BOOSTVOL[2:0] register bits. When L2_2BOOSTVOL[6:4] and R2_2BOOSTVOL[6:4]=000 the L2/R2 input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. w PD, Rev 4.6, July 2009 35 WM8985 Production Data REGISTER ADDRESS R42 (2Ah) OUT4 to ADC R47 (2Fh) Left channel Input BOOST control R48 (30h) Right channel Input BOOST control w BIT LABEL DEFAULT DESCRIPTION 8:6 OUT4_2ADCVOL 000 Controls the OUT4 to ADC input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain 5 OUT4_2LNR 0 OUT4 to L or R ADC input 0 = Right ADC input 1 = Left ADC input 2:0 AUXL2BOOSTVOL 000 Controls the auxiliary amplifier to the left channel input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain 6:4 L2_2BOOSTVOL 000 Controls the L2 pin to the left channel input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain 2:0 AUXR2BOOSTVOL 000 Controls the auxiliary amplifier to the right channel input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain PD, Rev 4.6, July 2009 36 WM8985 Production Data REGISTER ADDRESS BIT LABEL 6:4 DEFAULT R2_2BOOSTVOL 000 DESCRIPTION Controls the R2 pin to the right channel input boost stage: 000 = Path disabled (disconnected) 001 = -12dB 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain Table 9 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 (02h) Power management 2 BIT LABEL DEFAULT DESCRIPTION 4 BOOSTENL 0 Left channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON 5 BOOSTENR 0 Right channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Table 10 Input BOOST Enable Control MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD1 and when MBVSEL=1, MICBIAS=0.65*AVDD1. The output can be enabled or disabled using the MICBEN control bit. REGISTER ADDRESS BIT R1 (01h) Power management 1 4 LABEL MICBEN DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Table 11 Microphone Bias Enable Control REGISTER ADDRESS R44 (2Ch) Input control BIT 8 LABEL MBVSEL DEFAULT 0 DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD1 1 = 0.65 * AVDD1 Table 12 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 18. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA. w PD, Rev 4.6, July 2009 37 WM8985 Production Data Figure 18 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8985 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD1. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion. ADC DIGITAL FILTERS The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path for each ADC channel is illustrated in Figure 19. Figure 19 ADC Digital Filter Path The ADCs are enabled by the ADCENL/R register bit. REGISTER ADDRESS R2 (02h) Power management 2 BIT LABEL DEFAULT DESCRIPTION 0 ADCENL 0 Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled 1 ADCENR 0 Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled Table 13 ADC Enable Control w PD, Rev 4.6, July 2009 38 WM8985 Production Data The polarity of the output signal can also be changed under software control using the ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR128 register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS BIT R14 (0Eh) ADC Control LABEL DEFAULT DESCRIPTION 0 ADCLPOL 0 ADC left channel polarity adjust: 0 = normal 1 = inverted 1 ADCRPOL 0 ADC right channel polarity adjust: 0 = normal 1 = inverted 3 ADCOSR128 0 ADC oversample rate select: 0 = 64x (lower power) 1 = 128x (best performance) Table 14 ADC Control SELECTABLE HIGH PASS FILTER A selectable high pass filter is provided and enabled as default. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 16. REGISTER ADDRESS R14 (0Eh) ADC Control BIT 6:4 LABEL HPFCUT DEFAULT 000 DESCRIPTION Application mode cut-off frequency See Table 16 for details. PLL Output Clock Division Ratio 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4 Note: HPCUT and OPCLKDIV cannot be set independently 7 HPFAPP 0 Select audio mode or application mode 0 = Audio mode (1st order, fc = ~3.7Hz) 1 = Application mode (2nd order, fc = HPFCUT) 8 HPFEN 1 High Pass Filter Enable 0 = disabled 1 = enabled Table 15 ADC Enable Control w PD, Rev 4.6, July 2009 39 WM8985 Production Data HPFCUT [2:0] SR=101/100 SR=011/010 SR=001/000 fs (kHz) 8 11.025 12 16 22.05 24 000 82 113 001 102 141 010 131 011 163 100 32 44.1 48 122 82 113 122 82 113 122 153 102 141 153 102 141 153 180 196 131 180 196 131 180 196 225 245 163 225 245 163 225 245 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 Table 16 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the SR register bits are set correctly for the actual sample rate as shown in Table 16. Sampling rate (SR) is enabled by register bits R7[1:3]. Register 14(0Eh) bits [5:4] (HPFCUT) are used to control the high pass filter cut-off in applications mode and also the PLL output clock division ratio (OPCLKDIV). w PD, Rev 4.6, July 2009 40 WM8985 Production Data PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. These coefficients should be converted to 2’s complement numbers to determine the register values. A0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup. REGISTER ADDRESS R27 (1Bh) Notch Filter 1 BIT LABEL DEFAULT DESCRIPTION NFA0[13:7] 0 Notch Filter a0 coefficient, bits [13:7] 7 NFEN 0 Notch filter enable: 0 = Disabled 1 = Enabled 8 NFU 0 Notch filter update. The notch filter 6:0 values used internally only update when one of the NFU bits is set high. R28 (1Ch) Notch Filter 2 NFA0[6:0] 0 Notch Filter a0 coefficient, bits [6:0] 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R29 (1Dh) Notch Filter 3 6:0 NFA1[13:7] 0 Notch Filter a1 coefficient, bits [13:7] 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R30 (1Eh) Notch Filter 4 0-6 NFA1[6:0] 0 Notch Filter a1 coefficient, bits [6:0] 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. 6:0 Table 17 Notch Filter Function The coefficients are calculated as follows: a0 = 1 − tan( w b / 2) 1 + tan( w b / 2) a1 = −(1 + a0 ) cos( w 0 ) Where: w 0 = 2πfc / fs w b = 2πfb / fs fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The coefficients are calculated as follows: NFA0 = -a0 x 213 NFA1 = -a1 x 212 These values are then converted to 2’s complement notation to determine the register values. w PD, Rev 4.6, July 2009 41 WM8985 Production Data NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth. Fc = 1000 Hz fb = 100 Hz fs = 48000 Hz w 0 = 2πfc / fs = 2π x (1000 / 48000) = 0.1308996939 rads w b = 2πfb / fs = 2π x (100 / 48000) = 0.01308996939 rads a0 = 1 − tan( w b / 2) 1 − tan(0.0130899693 9 / 2) = = 0.9869949627 1 + tan( w b / 2) 1 + tan( 0.0130899693 9 / 2) a1 = −(1 + a0 ) cos( w 0 ) = −(1 + 0.9869949627 ) cos(0.1308996939 ) = -1.969995945 NFA0 = -a0 x 213 = -8085 (rounded to nearest whole number) NFA1 = -a1 x 212 = 8069 (rounded to nearest whole number) These values are then converted to 2’s complement: NFA0 = 14’h206B = 14’b10000001101011 NFA1 = 14’h1F85 = 14’b 01111110000101 DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: 0.5 × (G-255) dB for 1 ≤ G ≤ 255; REGISTER ADDRESS R15 (0Fh) Left channel ADC Digital Volume R16 (10h) Right channel ADC Digital Volume BIT LABEL MUTE for G = 0 DEFAULT DESCRIPTION 7:0 ADCLVOL [7:0] 11111111 ( 0dB ) Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB … 0.5dB steps up to 1111 1111 = 0dB 8 ADCVU Not latched ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16) 7:0 ADCRVOL [7:0] 11111111 ( 0dB ) Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB 8 ADCVU Not latched ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16) Table 18 ADC Digital Volume Control w PD, Rev 4.6, July 2009 42 WM8985 Production Data INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8985 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal. A digital peak detector monitors the input signal amplitude and compares it to a register defined threshold level (ALCLVL). If the signal is below the threshold, the ALC will increase the gain of the PGA at a rate set by ALCDCY. If the signal is above the threshold, the ALC will reduce the gain of the PGA at a rate set by ALCATK. The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode. The ALC/limiter function is enabled by settings the register bits R32[8:7] ALCSEL. REGISTER ADDRESS BIT R32 (20h) ALC Control 1 2:0 ALCMIN [2:0] 000 (-12dB) Set minimum gain of PGA 000 = -12dB 001 = -6dB 010 = 0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB 5:3 ALCMAX [2:0] 111 (+35.25dB) Set Maximum Gain of PGA 111 = +35.25dB 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB 8:7 ALCSEL 00 ALC function select 00 = ALC disabled 01 = Right channel ALC enabled 10 = Left channel ALC enabled 11 = Both channels ALC enabled 3:0 ALCLVL [3:0] 1011 (-6dB) ALC target – sets signal level at ADC input 1111 = -1.5dBFS 1110 = -1.5dBFS 1101 = -3dBFS 1100 = -4.5dBFS 1011 = -6dBFS 1010 = -7.5dBFS 1001 = -9dBFS 1000 = -10.5dBFS 0111 = -12dBFS 0110 = -13.5dBFS 0101 = -15dBFS 0100 = -16.5dBFS 0011 = -18dBFS 0010 = -19.5dBFS 0001 = -21dBFS 0000 = -22.5dBFS 7:4 ALCHLD 0000 ALC hold time before gain is R33 (21h) ALC Control 2 w LABEL DEFAULT DESCRIPTION PD, Rev 4.6, July 2009 43 WM8985 Production Data REGISTER ADDRESS R34 (22h) ALC Control 3 BIT LABEL DEFAULT DESCRIPTION [3:0] (0ms) increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s 1000 = 0.34s 1001 = 0.68s 1010 or higher = 1.36s 8 ALCMODE 0 Determines the ALC mode of operation: 0 = ALC mode (Normal Operation) 1 = Limiter mode. 7:4 ALCDCY [3:0] 0011 (13ms/6dB) Decay (gain ramp-up) time (ALCMODE ==0) Per step Per 6dB 90% of range 0000 410us 3.3ms 24ms 0001 820us 6.6ms 48ms 0010 1.64ms 13.1ms 192ms … (time doubles with every step) 1010 or higher 0011 (2.9ms/6dB) 420ms 3.36s 24.576s Decay (gain ramp-up) time (ALCMODE ==1) Per step Per 6dB 90% of range 0000 90.8us 726.4us 5.26ms 0001 181.6us 1.453ms 10.53 ms 0010 363.2us 2.905ms 21.06 ms … (time doubles with every step) 1010 3:0 ALCATK [3:0] 0010 (832us/6dB) 93ms 744ms 5.39s ALC attack (gain ramp-down) time (ALCMODE == 0) Per step Per 6dB 90% of range 0000 104us 832us 6ms 0001 208us 1.66ms 12ms 0010 416us 3.32ms 24.1ms … (time doubles with every step) 1010 or higher 0010 (182us/6dB) w 106ms 852ms 6.18s ALC attack (gain ramp-down) time (ALCMODE == 1) Per step Per 6dB 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms PD, Rev 4.6, July 2009 44 WM8985 Production Data REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION … (time doubles with every step) 1010 23.2ms 186ms 1.348s Table 20 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. NORMAL MODE In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this. Figure 21 ALC Normal Mode Operation w PD, Rev 4.6, July 2009 45 WM8985 Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode. If the ALC is started in limiter mode, this is the gain setting of the PGA at startup. If the ALC is switched into limiter mode after running in ALC mode, the starting gain will be the gain at switchover. The diagram below shows an example of limiter mode. Figure 20 ALC Limiter Mode Operation ATTACK AND DECAY TIMES The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when the gain is increasing. In limiter mode, the time constants are faster than in ALC mode. The time constants are shown below in terms of a single gain step, a change of 6dB and a change of 90% of the PGAs gain range. Note that, these times will vary slightly depending on the sample rate used (specified by the SR register). w PD, Rev 4.6, July 2009 46 WM8985 Production Data NORMAL MODE ALCMODE = 0 (Normal Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tATK 104μs 208μs 416μs 832μs 1.66ms 3.33ms 6.66ms 13.3ms 26.6ms 53.2ms 106ms Attack Time (s) tATK6dB tATK90% 832μs 6ms 1.66ms 12ms 3.33ms 24ms 6.66ms 48ms 13.3ms 96ms 26.6ms 192ms 53.2ms 384ms 106ms 767ms 213.2ms 1.53s 426ms 3.07s 852ms 6.13s ALCMODE = 0 (Normal Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tDCY 410μs 820μs 1.64ms 3.28ms 6.56ms 13.1ms 26.2ms 52.5ms 105ms 210ms 420ms Decay Time (s) tDCY6dB tDCY90% 3.28ms 23.6ms 6.56ms 47.2ms 13.1ms 94.5ms 26.2ms 189ms 52.5ms 378ms 105ms 756ms 210ms 1.51s 420ms 3.02s 840ms 6.05s 1.68s 12.1s 3.36s 24.2s Table 19 ALC Normal Mode (Attack and Decay times) w PD, Rev 4.6, July 2009 47 WM8985 Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tATKLIM 22.7μs 45.4μS 90.8μS 182μS 363μS 726μS 1.45ms 2.9ms 5.81ms 11.6ms 23.2ms Attack Time (s) tATKLIM6dB tATKLIM90% 182μs 1.31ms 363μs 2.62ms 726μs 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tDCYLIM 90.8μs 182μS 363μS 726μS 1.45ms 2.91ms 5.81ms 11.6ms 23.2ms 46.5ms 93ms Attack Time (s) tDCYLIM6dB tDCYLIM90% 726μs 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s 372ms 2.68s 744ms 5.36s Table 20 ALC Limiter Mode (Attack and Decay times) w PD, Rev 4.6, July 2009 48 WM8985 Production Data MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled. REGISTER ADDRESS R32 ALC Control 1 BIT LABEL DEFAULT DESCRIPTION 5:3 ALCMAX 111 Set Maximum Gain of PGA 2:0 ALCMIN 000 Set minimum gain of PGA Table 23 ALC Max/Min Gain In normal mode, ALCMAX sets the maximum boost which can be applied to the signal. In limiter mode, ALCMAX will normally have no effect (assuming the starting gain value is less than the maximum gain specified by ALCMAX) because the maximum gain is set at the starting gain level. ALCMIN sets the minimum gain value which can be applied to the signal. Figure 23 ALC Min/Max Gain ALCMAX 111 110 101 100 011 010 001 000 Maximum Gain (dB) 35.25 29.25 23.25 17.25 11.25 5.25 -0.75 -6.75 Table 24 ALC Max Gain Values w PD, Rev 4.6, July 2009 49 WM8985 Production Data ALCMIN 000 001 010 011 100 101 110 111 Minimum Gain (dB) -12 -6 0 6 12 18 24 30 Table 25 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range. It is recommended that the ALC starting gain is set between the ALCMAX and ALCMIN limits. ALC HOLD TIME (NORMAL MODE ONLY) In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins it’s decay phase (gain increasing). The hold time is set by the ALCHLD register. REGISTER ADDRESS BIT R33 ALC Control 2 7:4 LABEL ALCHLD DEFAULT 0000 DESCRIPTION ALC hold time before gain is increased. Table 26 ALC Hold Time If the hold time is exceeded this indicates that the signal has reached a new average level and the ALC will increase the gain to adjust for that new average level. If the signal goes above the threshold during the hold period, the hold phase is abandoned and the ALC returns to normal operation. w PD, Rev 4.6, July 2009 50 Production Data WM8985 Figure 24 ALCLVL w PD, Rev 4.6, July 2009 51 WM8985 Production Data Figure 25 ALC Hold Time ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tHOLD (s) 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s Table 27 ALC Hold Time Values w PD, Rev 4.6, July 2009 52 WM8985 Production Data PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used. NOISE GATE (NORMAL MODE ONLY) When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8985 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set–up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode. REGISTER ADDRESS BIT R35 (23h) ALC Noise Gate Control 2:0 3 LABEL DEFAULT DESCRIPTION NGTH 000 Noise gate threshold: 000 = -39dB 001 = -45dB 010 = -51db 011 = -57dB 100 = -63dB 101 = -70dB 110 = -76dB 111 = -81dB NGATEN 0 Noise gate function enable 1 = enable 0 = disable Table 28 ALC Noise Gate Control The diagrams below show the response of the system to the same signal with and without noise gate. w PD, Rev 4.6, July 2009 53 WM8985 Production Data Figure 21 ALC Operation Above Noise Gate Threshold w PD, Rev 4.6, July 2009 54 WM8985 Production Data Figure 22 Noise Gate Operation OUTPUT SIGNAL PATH The WM8985 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are enabled by register bits DACENL and DACENR. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8985, irrespective of whether the DACs are running or not. The WM8985 DACs receive digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control Graphic equaliser A digital peak limiter Sigma-Delta Modulation High performance sigma-delta audio DAC converts the digital data into an analogue signal. w PD, Rev 4.6, July 2009 55 WM8985 Production Data Figure 23 DAC Digital Filter Path The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1, LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 have additional mixers which allow them to output different signals to the line outputs or back into the record path. DIGITAL PLAYBACK (DAC) PATH Digital data is passed to the WM8985 via the flexible audio interface and is then passed through a variety of advanced digital filters as shown in Figure 23 to the hi-fi DACs. The DACs are enabled by the DACENL/R register bits. REGISTER ADDRESS R3 (03h) Power Management 3 BIT LABEL DEFAULT DESCRIPTION 0 DACENL 0 Left channel DAC enable 0 = DAC disabled 1 = DAC enabled 1 DACENR 0 Right channel DAC enable 0 = DAC disabled 1 = DAC enabled Table 21 DAC Enable Control The WM8985 also has a Soft Mute function, which when enabled, gradually attenuates the volume of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, it must first be disabled by setting the SOFTMUTE bit to zero. REGISTER ADDRESS R10 (0Ah) DAC Control BIT LABEL DEFAULT DESCRIPTION 0 DACPOL 0 Left DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) 1 DACRPOL 0 Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) 2 AMUTE 0 Automute enable 0 = Amute disabled 1 = Amute enabled 3 DACOSR128 0 DAC oversampling rate: 0 = 64x (lowest power) 1 = 128x (best performance) 6 SOFTMUTE 0 Softmute enable: 0 = Enabled 1 = Disabled Table 22 DAC Control Register w PD, Rev 4.6, July 2009 56 WM8985 Production Data The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. The DAC output phase defaults to non-inverted. Setting DACLPOL will invert the DAC output phase on the left channel and DACRPOL inverts the phase on the right channel. AUTO-MUTE The DAC has an auto-mute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is released as soon as a non-zero sample is detected. Auto-mute can be disabled using the AMUTE control bit. DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL The signal volume from each Hi-Fi DAC can be controlled digitally. The gain range is –127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 × (X-255) dB for 1 ≤ X ≤ 255; REGISTER ADDRESS R11 (0Bh) Left DAC Digital Volume R12 (0Ch) Right DAC Digital Volume BIT LABEL MUTE for X = 0 DEFAULT DESCRIPTION 7:0 DACLVOL [7:0] 11111111 ( 0dB ) Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB 8 DACVU Not latched DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) 7:0 DACRVOL [7:0] 11111111 ( 0dB ) Right DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB 8 DACVU Not latched DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Table 23 DAC Digital Volume Control Note: An additional gain of up to 12dB can be added using the gain block embedded in the digital peak limiter circuit (see DAC OUTPUT LIMITER section). 5-BAND EQUALISER A 5-band graphic equaliser function which can be used to change the output frequency levels to suit the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND EQUALISER section for further details on this feature. 3-D ENHANCEMENT The WM8985 has an advanced digital 3-D enhancement feature which can be used to vary the perceived stereo separation of the left and right channels. Like the 5-band equaliser this feature can be applied to either the ADC record path or the DAC playback path but not both simultaneously. Refer to the 3-D STEREO ENHANCEMENT section for further details on this feature. DAC DIGITAL OUTPUT LIMITER The WM8985 has a digital output limiter function. The operation of this is shown in Figure 24. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic. w PD, Rev 4.6, July 2009 57 WM8985 Production Data Figure 24 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 24, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value. VOLUME BOOST The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled. w PD, Rev 4.6, July 2009 58 WM8985 Production Data REGISTER ADDRESS R24 (18h) DAC digital limiter control 1 BIT 3:0 LABEL LIMATK DEFAULT 0010 DESCRIPTION Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these are proportionally related to sample rate. 0000 = 94us 0001 = 188s 0010 = 375us 0011 = 750us 0100 = 1.5ms 0101 = 3ms 0110 = 6ms 0111 = 12ms 1000 = 24ms 1001 = 48ms 1010 = 96ms 1011 to 1111 = 192ms R25 (19h) DAC digital limiter control 2 7:4 LIMDCY 0011 Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these are proportionally related to sample rate: 0000 = 750us 0001 = 1.5ms 0010 = 3ms 0011 = 6ms 0100 = 12ms 0101 = 24ms 0110 = 48ms 0111 = 96ms 1000 = 192ms 1001 = 384ms 1010 = 768ms 1011 to 1111 = 1.536s 8 LIMEN 0 Enable the DAC digital limiter: 0=disabled 1=enabled 3:0 LIMBOOST 0000 Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000 = 0dB 0001 = +1dB 0010 = +2dB 0011 = +3dB 0100 = +4dB 0101 = +5dB 0110 = +6dB 0111 = +7dB 1000 = +8dB 1001 = +9dB 1010 = +10dB 1011 = +11dB 1100 = +12dB 1101 to 1111 = reserved w PD, Rev 4.6, July 2009 59 WM8985 Production Data REGISTER ADDRESS BIT 6:4 LABEL LIMLVL DEFAULT 000 DESCRIPTION Programmable signal threshold level (determines level at which the limiter starts to operate) 000 = -1dB 001 = -2dB 010 = -3dB 011 = -4dB 100 = -5dB 101 to 111 = -6dB Table 24 DAC Digital Limiter Control 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. REGISTER ADDRESS R18 (12h) EQ Control 1 BIT 8 LABEL EQ3DMODE DEFAULT 1 DESCRIPTION 0 = Equaliser and 3D Enhancement applied to ADC path 1 = Equaliser and 3D Enhancement applied to DAC path Table 25 EQ and 3D Enhancement DAC or ADC Path Select Note: The ADCs and DACs must be disabled before changing the EQ3DMODE bit. The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB in 1dB steps). The peak filters have selectable bandwidth. To enable the use of the 5-band equaliser the device must be in 128fs mode by setting M128ENB to 1 in register R7 bit 8. Refer to the Low Power section under Power Management below for more details. REGISTER ADDRESS R18 (12h) EQ Band 1 Control BIT LABEL DEFAULT 4:0 EQ1G 01100 (0dB) 6:5 EQ1C 01 DESCRIPTION Band 1 Gain Control. See Table 31 for details. Band 1 Cut-off Frequency: 00 = 80Hz 01 = 105Hz 10 = 135Hz 11 = 175Hz Table 26 EQ Band 1 Control w PD, Rev 4.6, July 2009 60 WM8985 Production Data REGISTER ADDRESS R19 (13h) EQ Band 2 Control BIT LABEL DEFAULT DESCRIPTION 4:0 EQ2G 01100 (0dB) Band 2 Gain Control. See Table 31 for details. 6:5 EQ2C 01 Band 2 Centre Frequency: 8 EQ2BW 0 00 = 230Hz 01 = 300Hz 10 = 385Hz 11 = 500Hz Band 2 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth Table 27 EQ Band 2 Control REGISTER ADDRESS R20 (14h) EQ Band 3 Control BIT LABEL DEFAULT DESCRIPTION 4:0 EQ3G 01100 (0dB) Band 3 Gain Control. See Table 31 for details. 6:5 EQ3C 01 Band 3 Centre Frequency: 8 EQ3BW 0 00 = 650Hz 01 = 850Hz 10 = 1.1kHz 11 = 1.4kHz Band 3 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth Table 28 EQ Band 3 Control REGISTER ADDRESS R21 (15h) EQ Band 4 Control BIT LABEL DEFAULT 4:0 EQ4G 01100 (0dB) 6:5 EQ4C 01 8 EQ4BW 0 DESCRIPTION Band 4 Gain Control. See Table 31 for details Band 4 Centre Frequency: 00 = 1.8kHz 01 = 2.4kHz 10 = 3.2kHz 11 = 4.1kHz Band 4 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth Table 29 EQ Band 4 Control w PD, Rev 4.6, July 2009 61 WM8985 Production Data REGISTER ADDRESS R22 (16h) EQ Band 5 Gain Control BIT LABEL DEFAULT DESCRIPTION 4:0 EQ5G 01100 (0dB) Band 5 Gain Control. See Table 31 for details. 6:5 EQ5C 01 Band 5 Cut-off Frequency: 00 = 5.3kHz 01 = 6.9kHz 10 = 9kHz 11 = 11.7kHz Table 30 EQ Band 5 Control GAIN REGISTER GAIN 00000 +12dB 00001 +11dB 00010 +10dB …. (1dB steps) 01100 0dB 01101 -1dB 11000 -12dB 11001 to 11111 Reserved Table 31 Gain Register Table See also Figure 47 to Figure 64 for equaliser and high pass filter responses. 3D STEREO ENHANCEMENT The WM8985 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done when both ADCs and both DACs are disabled. To enable the 3D Stereo Enhancement in the ADC path the device must be in 128fs mode by setting M128ENB to 1 in register R7 bit 8. Refer to the Low Power section under Power Management below for more details. The DEPTH3D setting controls the degree of stereo expansion. w PD, Rev 4.6, July 2009 62 WM8985 Production Data REGISTER ADDRESS R41 (29h) 3D Control BIT 3:0 LABEL DEPTH3D DEFAULT 0000 DESCRIPTION Stereo depth 0000 = Disabled 0001 = 6.67% 0010 = 13.3% 0011 = 20% 0100 = 26.7% 0101 = 33.3% 0110 = 40% 0111 = 46.6% 1000 = 53.3% 1001 = 60% 1010 = 66.7% 1011 = 73.3% 1100 = 80% 1101 = 86.7% 1110 = 93.3% 1111 = 100% (maximum 3D effect) Table 32 3D Stereo Enhancement Function Note: When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting. ANALOGUE OUTPUTS The WM8985 has three sets of stereo analogue outputs. These are: • • • LOUT1 and ROUT1 which are normally used to drive a headphone load. LOUT2 and ROUT2 – which can be used as class D or class AB headphone drivers. OUT3 and OUT4 – can be configured as a stereo line out (OUT3 is left output and OUT4 is right output) or a differential output. OUT4 can also be used to provide a mono mix of left and right channels. The outputs LOUT2 and ROUT2 are powered from AVDD2 and are capable of driving a 1V rms signal (AVDD1/3.3). LOUT1, ROUT1, OUT3 and OUT4 are powered from AVDD1 LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB gain ranges. There are four output mixers in the output signal path, the left and right channel mixers which control the signals to headphone (and optionally the line outputs) and also dedicated OUT3 and OUT4 mixers. w PD, Rev 4.6, July 2009 63 WM8985 Production Data LEFT AND RIGHT OUTPUT CHANNEL MIXERS The left and right output channel mixers are shown in Figure 25. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This allows a mono mix of the DAC channels to be performed as well as mixing in external line-in from the AUX or speech from the input bypass path. The AUX and bypass inputs have individual volume control from -15dB to +6dB and the DAC volume can be adjusted in the digital domain if required. The output of these mixers is connected to both the headphone (LOUT1 and ROUT1) and class D headphone (LOUT2 and ROUT2) and can optionally be connected to the OUT3 and OUT4 mixers. Figure 25 Left/Right Output Channel Mixers w PD, Rev 4.6, July 2009 64 WM8985 Production Data REGISTER ADDRESS LABEL DEFAULT DESCRIPTION R43 (2Bh) Output mixer control 8 BYPL2RMIX 0 Left bypass path (from the Left channel input PGA stage) to right output mixer 0 = not selected 1 = selected R43 (2Bh) Output mixer control 7 BYPR2LMIX 0 Right bypass path (from the right channel input PGA stage) to Left output mixer 0 = not selected 1 = selected R49 (31h) Output mixer control 5 DACR2LMIX 0 Right DAC output to left output mixer 0 = not selected 1 = selected 6 DACL2RMIX 0 0 DACL2LMIX 1 Left DAC output to right output mixer 0 = not selected 1 = selected Left DAC output to left output mixer 0 = not selected 1 = selected 1 BYPL2LMIX 0 4:2 BYPLMIXVOL 5 AUXL2LMIX 8:6 AUXLMIXVOL R50 (32h) Left channel output mixer control w BIT 000 Left bypass path (from the left channel input PGA stage) to left output mixer 0 = not selected 1 = selected Left bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 0 Left Auxiliary input to left channel output mixer: 0 = not selected 1 = selected 000 Aux left channel input to left mixer volume control: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB PD, Rev 4.6, July 2009 65 WM8985 Production Data R51 (33h) Right channel output mixer control R3 (03h) Power management 3 0 DACR2RMIX 1 Right DAC output to right output mixer 0 = not selected 1 = selected 1 BYPR2RMIX 0 Right bypass path (from the right channel input PGA stage) to right output mixer 0 = not selected 1 = selected 4:2 BYPRMIXVOL 5 AUXR2RMIX 8:6 AUXRMIXVOL 2 LMIXEN 0 Left output channel mixer enable: 0 = disabled 1= enabled 3 RMIXEN 0 Right output channel mixer enable: 0 = disabled 1 = enabled 000 Right bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 0 Right Auxiliary input to right channel output mixer: 0 = not selected 1 = selected 000 Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Table 33 Left and Right Output Mixer Control HEADPHONE OUTPUTS (LOUT1 AND ROUT1) The headphone outputs LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors, or DC-coupled to a buffered midrail reference (LOUT2 or ROUT2), saving a capacitor (capless mode). When using capless mode AVDD1 and AVDD2 should use the same supply to maximise supply rejection. OUT3 and OUT4 should not be used as a buffered midrail reference in capless mode. w PD, Rev 4.6, July 2009 66 WM8985 Production Data Headphone Output using DC Blocking Capacitors DC Coupled Headphone Output Figure 26 Recommended Headphone Output Configurations When DC blocking capacitors are used, their capacitance and the load resistance together determine the lower cut-off frequency of the output signal, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16Ω load and C1, C2 = 220μF: fc = 1 / 2π RLC1 = 1 / (2π x 16Ω x 220μF) = 45 Hz In the DC coupled configuration, the headphone pseudo-ground is connected to the buffered midrail reference pin (LOUT2 or ROUT2). The L/ROUT2 pins can be configured as a DC output driver by setting the LOUT2MUTE and ROUT2MUTE register bits. The DC voltage on VMID in this configuration is equal to the DC offset on the LOUT1 and ROUT1 pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. It is not recommended to use DC-coupling to line inputs of another device. Although the built-in short circuit protection on the headphone outputs would be tolerant of shorts to ground, such a connection could be noisy, and may not function properly if the other device is grounded. DC-coupled configurations should only be used with headphones. w PD, Rev 4.6, July 2009 67 WM8985 Production Data REGISTER ADDRESS R52 (34h) LOUT1 Volume control R53 ROUT1 Volume control BIT LABEL DEFAULT 111001 (0dB) DESCRIPTION 5:0 LOUT1VOL 6 LOUT1MUTE 0 Left headphone output mute: 0 = Normal operation 1 = Mute 7 LOUT1ZC 0 Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately 8 HPVU Not latched LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU (in reg 52 or 53) 5:0 ROUT1VOL 6 ROUT1MUTE 0 Right headphone output mute: 0 = Normal operation 1 = Mute 7 ROUT1ZC 0 Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately 8 HPVU Not latched LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU (in reg 52 or 53) 111001 (0dB) Left headphone output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Right headphone output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Table 34 OUT1 Volume Control w PD, Rev 4.6, July 2009 68 WM8985 Production Data CLASS D / CLASS AB HEADPHONE OUTPUTS (LOUT2 AND ROUT2) The outputs LOUT2 and ROUT2 are designed to drive two headphone loads of 16Ω or 32Ω or line outputs (See Headphone Output and Line Output sections, respectively). Each output has an individual volume control PGA, a mute and an enable control bit as shown in Figure 27. LOUT2 and ROUT2 output the left and right channel mixer outputs respectively. REGISTER ADDRESS BIT LABEL R7 (07h) 7:4 DCLKDIV R23 (17h) 8 CLASSDEN DEFAULT DESCRIPTION 1000 Controls clock division from SYSCLK to generate suitable class D clock. Recommended class D clock frequency = 1.4MHz. 0000 = divide by 1 0010 = divide by 2 0011 = divide by 3 0100 = divide by 4 0101 = divide by 5.5 0110 = divide by 6 1000 = divide by 8 1001 = divide by 12 1010 = divide by 16 0 Enable signal for class D mode on LOUT2 and ROUT2 0 = Class AB mode 1 = Class D mode Table 35 Class D Control Registers When driving headphones using class D outputs it is necessary to use appropriate filtering, placed close to the device, to minimise EMI emissions from the headphone cable (Refer to "Applications Information" for more information). This filtering does not prevent class AB mode operation. Figure 27 LOUT2 and ROUT2 Class D Headphone Configuration w PD, Rev 4.6, July 2009 69 WM8985 Production Data Figure 28 LOUT2 and ROUT2 Class AB Headphone Configuration The output configurations shown in figures 29 and 30 are both suitable for class AB operation. The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the bypass path (output of the input boost stage) and the AUX input. The LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Gains over 0dB may cause clipping if the input signal is too high. The LOUT2MUTE/ ROUT2MUTE register bits cause these outputs to be muted (the output DC level is driven out). The output pins remain at the same DC level, so that no click noise is produced when muting or un-muting. w PD, Rev 4.6, July 2009 70 WM8985 Production Data REGISTER ADDRESS R54 (36h) LOUT2 Volume control R55 (37h) ROUT2 Volume control BIT LABEL DEFAULT 111001 DESCRIPTION 5:0 LOUT2VOL Left output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB 6 LOUT2MUTE 0 Left output mute: 0 = Normal operation 1 = Mute 7 LOUT2ZC 0 LOUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately 8 OUT2VU Not latched LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55) 5:0 ROUT2VOL 6 111001 Right output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB ROUT2MUTE 0 Right output mute: 0 = Normal operation 1 = Mute 7 ROUT2ZC 0 ROUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately 8 OUT2VU Not latched LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55) Table 36 OUT2 Volume Control ZERO CROSS TIMEOUT A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * SYSCLK period. REGISTER ADDRESS R7 (07h) Additional Control BIT 0 LABEL SLOWCLKEN DEFAULT 0 DESCRIPTION Slow clock enable 0 = slow clock disabled 1 = slow clock enabled Table 37 Timeout Clock Enable Control Note: SLOWCLKEN is also used for the jack insert detect debounce circuit w PD, Rev 4.6, July 2009 71 WM8985 Production Data OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins provide an additional stereo line output, a mono output, or a differential output. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 29. The OUT3 and OUT4 output stages are powered from AVDD1 and AGND1. Figure 29 OUT3 and OUT4 Mixers OUT3 can provide a left line output, or a mono mix line output. OUT4 can provide a right line output, or a mono mix line output. A 6dB attenuation function is provided for OUT4, to prevent clipping during mixing of left and right signals. This function is enabled by the OUT4ATTN register bit. w PD, Rev 4.6, July 2009 72 WM8985 Production Data REGISTER ADDRESS R56 (38h) OUT3 mixer control R57 (39h) OUT4 mixer control BIT LABEL DEFAULT DESCRIPTION 6 OUT3MUTE 0 0 = Output stage outputs OUT3 mixer 1 = Output stage muted 3 OUT4_2OUT3 0 OUT4 mixer output to OUT3 0 = disabled 1 = enabled 2 BYPL2OUT3 0 Left ADC input to OUT3 0 = disabled 1 = enabled 1 LMIX2OUT3 0 Left DAC mixer to OUT3 0 = disabled 1 = enabled 0 LDAC2OUT3 1 Left DAC output to OUT3 0 = disabled 1 = enabled 7 OUT3_2OUT4 0 OUT3 mixer output to OUT4 0 = disabled 1 = enabled 6 OUT4MUTE 0 0 = Output stage outputs OUT4 mixer 1 = Output stage muted 5 OUT4ATTN 0 0 = OUT4 normal output 1 = OUT4 attenuated by 6dB 4 LMIX2OUT4 0 Left DAC mixer to OUT4 0 = disabled 1 = enabled 3 LDAC2OUT4 0 Left DAC to OUT4 0 = disabled 1 = enabled 2 BYPR2OUT4 0 Right ADC input to OUT4 0 = disabled 1 = enabled 1 RMIX2OUT4 0 Right DAC mixer to OUT4 0 = disabled 1 = enabled 0 RDAC2OUT4 1 Right DAC output to OUT4 0 = disabled 1 = enabled Table 38 OUT3/OUT4 Mixer Registers w PD, Rev 4.6, July 2009 73 WM8985 Production Data ENABLING THE OUTPUTS Each analogue output of the WM8985 can be independently enabled or disabled. The analogue mixer associated with each output has a separate enable bit. All outputs are disabled by default. To save power, unused parts of the WM8985 should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see “Power Management” and “Applications Information” sections). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 (01h) Power Management 1 2 BUFIOEN 0 Unused input/output bias buffer enable 6 OUT3MIXEN 0 OUT3 mixer enable 7 OUT4MIXEN 0 OUT4 mixer enable R2 (02h) Power Management 2 8 ROUT1EN 0 ROUT1 output enable 7 LOUT1EN 0 LOUT1 output enable 6 SLEEP 0 0 = Normal device operation 1 = Supply current reduced in device standby mode when clock supplied (see note) R3 (03h) Power Management 3 2 LMIXEN 0 Left mixer enable 3 RMIXEN 0 Right mixer enable 5 LOUT2EN 0 LOUT2 output enable 6 ROUT2EN 0 ROUT2 output enable 7 OUT3EN 0 OUT3 enable 8 OUT4EN 0 OUT4 enable Note: All “Enable” bits are 1 = ON, 0 = OFF Table 39 Output Stages Power Management Control Note: The SLEEP bit R2[6] should only be used when the device is already Standby mode. The SLEEP bit prevents the MCLK from propagating round the device when the external MCLK signal cannot be removed. THERMAL SHUTDOWN To protect the WM8985 from becoming too hot, a thermal sensor has been built in. If the device junction temperature reaches approximately 125°C and the TSDEN and TSOPCTRL bit are set, then all outputs will be disabled to avoid further increase of the chip temperature. Additionally, when the device is too hot and TSDEN is set, then the WM8985 de-asserts GPIO bit 11, a virtual GPIO that can be set up to generate an interrupt to the CPU (see “GPIO and Interrupt Control” section). REGISTER ADDRESS R49 (31h) Output Control BIT LABEL DEFAULT DESCRIPTION 1 TSDEN 0 Thermal Sensor Enable 0 = disabled 1 = enabled 2 TSOPCTRL 0 Thermal Shutdown Output enable 0 = Disabled 1 = Enabled, i.e. all outputs will be disabled if TI set and the device junction temperature is more than 125ºC. Table 40 Thermal Shutdown UNUSED ANALOGUE INPUTS/OUTPUTS Whenever an analogue input/output is disabled, it remains connected to a voltage source (AVDD1/2) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30kΩ. w PD, Rev 4.6, July 2009 74 WM8985 Production Data REGISTER ADDRESS BIT R49 (31h) 0 LABEL DEFAULT VROI 0 DESCRIPTION VREF (AVDD1/2) to analogue output resistance 0 = approx 1kΩ 1 = approx 30 kΩ Table 41 Disabled Outputs to VREF Resistance A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 30. This buffer can be enabled using the BUFIOEN register bit. Figure 30 summarises the bias options for the output pins. Analogue inputs 1k 1k 1k 1k LOUT1 30k VROI R49[0] 1k ROUT1 30k AVDD/2 + VROI R49[0] AVDD/2 BUFIOEN R1[2] 1k OUT4 Used to tie off all unused inputs and outputs 30k VROI R49[0] 1k OUT3 30k VROI R49[0] 1k LOUT2 30k VROI R49[0] 1k ROUT2 30k VROI R49[0] Figure 30 Unused Input/Output Pin Tie-off Buffers L/ROUT2EN/ OUT3/4EN VROI OUTPUT CONFIGURATION 0 0 1kΩ to AVDD1/2 0 1 30kΩ to AVDD1/2 1 X Output enabled (DC level=AVDD1/2) Table 42 Unused Output Pin Bias Options w PD, Rev 4.6, July 2009 75 WM8985 Production Data DIGITAL AUDIO INTERFACES The audio interface has four pins: • • ADCDAT: ADC data output DACDAT: DAC data input • • LRC: Data Left/Right alignment clock BCLK: Bit clock, for synchronisation The clock signals BCLK, and LRC can be outputs when the WM8985 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: • Left justified • • • Right justified I 2S DSP mode A • DSP mode B All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. MASTER AND SLAVE MODE OPERATION The WM8985 audio interface may be configured as either master or slave. As a master interface device the WM8985 generates BCLK and LRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8985 responds with data to clocks it receives over the digital audio interfaces. AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition. Figure 31 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRC transition. w PD, Rev 4.6, July 2009 76 WM8985 Production Data Figure 32 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 33 I2S Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the LRC pulse shown in Figure 34 and Figure 35. In device slave mode, Figure 36 and Figure 37, it is possible to use any length of LRC pulse less than 1/fs, providing the falling edge of the LRC pulse occurs greater than one BCLK period before the rising edge of the next LRC pulse. Figure 34 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) w PD, Rev 4.6, July 2009 77 WM8985 Production Data Figure 35 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 36 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) Figure 37 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w PD, Rev 4.6, July 2009 78 WM8985 Production Data REGISTER ADDRESS R4 (04h) Audio Interface Control BIT LABEL DEFAULT DESCRIPTION 0 MONO 0 Selects between stereo and mono device operation: 0 = Stereo device operation 1 = Mono device operation. Data appears in ‘left’ phase of LRC only. 1 ALRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of LRC clock: 0 = ADC left data appear in ‘left’ phase of LRC and right data in ‘right’ phase 1 = ADC left data appear in ‘right’ phase of LRC and right data in ‘left’ phase 2 DLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of LRC clock: 0 = DAC left data appear in ‘left’ phase of LRC and right data in ‘right’ phase 1 = DAC left data appear in ‘right’ phase of LRC and right data in ‘left’ phase 4:3 FMT 10 Audio interface Data Format Select: 00 = Right Justified 01 = Left Justified 10 = I2S format 11 = DSP/PCM mode 6:5 WL 10 Word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits (see note) 7 LRP 0 LRC clock polarity 0 = normal 1 =inverted DSP Mode – mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) st 1 = MSB is available on 1 BCLK rising edge after LRC rising edge (mode B) R5 8 BCP 0 BCLK polarity 0 = normal 1 = inverted 0 LOOPBACK 0 Digital loopback function 0 = No loopback 1 = Loopback enabled, ADC data output is fed directly into DAC data input. Table 43 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode. AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and LRC are outputs. The frequency of BCLK in master mode can be controlled with BCLKDIV. The frequencies of BCLK and LRC are also controlled by MCLKDIV. The LRC sample rate is set to the required values by MCLKDIV and the BCLK rate will be set accordingly to provide sufficient BCLKs for that chosen sample rate. These clocks are divided down versions of master clock. w PD, Rev 4.6, July 2009 79 WM8985 Production Data REGISTER ADDRESS R6 (06h) Clock Generation Control BIT LABEL DEFAULT DESCRIPTION 0 MS 0 Sets the chip to be master over LRC and BCLK 0 = BCLK and LRC clock are inputs 1 = BCLK and LRC clock are outputs generated by the WM8985 (MASTER) 4:2 BCLKDIV 000 Configures the BCLK output frequency, for use when the chip is master over BCLK. 000 = divide by 1 (BCLK=SYSCLK) 001 = divide by 2 (BCLK=SYSCLK/2) 010 = divide by 4 (BCLK=SYSCLK/4) 011 = divide by 8 (BCLK=SYSCLK/8) 100 = divide by 16 (BCLK=SYSCLK/16) 101 = divide by 32 (BCLK=SYSCLK/32) 110 = reserved 111 = reserved 7:5 MCLKDIV 010 Sets the scaling for SYSCLK clock output (under control of CLKSEL) 000 = divide by 1 (LRC=SYSCLK/128) 001 = divide by 1.5 (LRC=SYSCLK/192) 010 = divide by 2 (LRC=SYSCLK/256) 011 = divide by 3 (LRC=SYSCLK/384) 100 = divide by 4 (LRC=SYSCLK/512) 101 = divide by 6 (LRC=SYSCLK/768) 110 = divide by 8 (LRC=SYSCLK/1024) 111 = divide by 12 (LRC=SYSCLK/1536) 8 CLKSEL 1 Controls the source of the clock for all internal operation: 0 = MCLK 1 = PLL output Table 44 Clock Control The CLKSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from MCLK (CLKSEL=0). When the internal clock is switched from one source to another using the CLKSEL bit, the clock originally selected must generate at least one falling edge after CLKSEL has changed for the switching of clocks to be successful. EXAMPLE: If the PLL is the current source of the internal clock (CLKSEL=1) and it is required to switch to the MCLK, change CLKSEL to select MCLK (CLKSEL=0) and then disable PLL (PLLEN=0). w PD, Rev 4.6, July 2009 80 WM8985 Production Data AUDIO SAMPLE RATES The WM8985 ADC high pass filter, ALC and DAC limiter characteristics are sample rate dependent. SR should be set to the correct sample rate or the closest value if the actual sample rate is not available. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen. The filter characteristics and the ALC attack decay and hold times will scale appropriately. REGISTER ADDRESS R7 (07h) Additional Control BIT LABEL 3:1 SR DEFAULT 000 DESCRIPTION Approximate sample rate (configures the coefficients for the internal digital filters): 000 = 48kHz 001 = 32kHz 010 = 24kHz 011 = 16kHz 100 = 12kHz 101 = 8kHz 110-111 = reserved Table 45 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP (PLL) The WM8985 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8985 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from an existing audio master clock. Figure 38 shows the PLL and internal clocking on the WM8985. The PLL can be enabled or disabled by the PLLEN register bit. REGISTER ADDRESS R1 (01h) Power management 1 BIT 5 LABEL PLLEN DEFAULT 0 DESCRIPTION PLL enable 0 = PLL off 1 = PLL on Table 46 PLLEN Control Bit w PD, Rev 4.6, July 2009 81 WM8985 Production Data Figure 38 PLL and Clock Select Circuit The PLL frequency ratio R = f2/f1 (see Figure 38) can be set using the register bits PLLK and PLLN: PLLN = int R PLLK = int (224 (R-PLLN)) EXAMPLE: MCLK=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement. Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 PLLN = int R = 8 k = int ( 224 x (8.192 – 8)) = 3221225 = 3126E9h REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R36 (24h) PLL N value 4 PLLPRESCALE 0 0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input to PLL 3:0 PLLN 1000 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. R37 (25h) PLL K value 1 5:0 PLLK [23:18] 0Ch Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). R38 (26h) PLL K Value 2 8:0 PLLK [17:9] 093h R39 (27h) PLL K Value 3 8:0 PLLK [8:0] 0E9h Table 47 PLL Frequency Ratio Control The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in 48. w PD, Rev 4.6, July 2009 82 WM8985 DESIRED OUTPUT (SYSCLK) (MHz) f2 (MHz) PLLPRESCALE MCLKDIV Production Data MCLK (MHz) (f1) R N K 12 11.29 90.3168 1 2 7.5264 7h 86C226h 12 12.288 98.304 1 2 8.192 8h 3126E8h 13 11.29 90.3168 1 2 6.947446 6h 13 12.288 98.304 1 2 7.561846 7h 14.4 11.29 90.3168 1 2 6.272 14.4 12.288 98.304 1 2 19.2 11.29 90.3168 2 2 19.2 12.288 98.304 2 19.68 11.29 90.3168 19.68 12.288 98.304 19.8 11.29 90.3168 19.8 12.288 98.304 24 11.29 90.3168 24 12.288 98.304 26 11.29 26 12.288 27 27 N REGISTER R36[3:0] K REGISTERS R37 R38 R39 XX7h 021h 161h 026h XX8h 00Ch 093h 0E8h F28BD4h XX6h 03Ch 145h 1D4h 8FD525h XX7h 023h 1Eah 125h 6h 45A1Cah XX6h 011h 0D0h 1Cah 6.826667 6h D3A06Eh XX6h 034h 1D0h 06Eh 9.408 9h 6872Afh XX9h 01Ah 039h 0Afh 2 10.24 Ah 3D70A3h XXAh 00Fh 0B8h 0A3h 2 2 9.178537 9h 2DB492h XX9h 00Bh 0Dah 092h 2 2 9.990243 9h FD809Fh XX9h 03Fh 0C0h 09Fh 2 2 9.122909 9h 1F76F7h XX9h 007h 1BBh 0F7h 2 2 9.929697 9h EE009Eh XX9h 03Bh 100h 09Eh 2 2 7.5264 7h 86C226h XX7h 021h 161h 026h 2 2 8.192 8h 3126E8h XX8h 00Ch 093h 0E8h 90.3168 2 2 6.947446 6h F28BD4h XX6h 03Ch 145h 1D4h 98.304 2 2 7.561846 7h 8FD525h XX7h 023h 1Eah 125h 11.29 90.3168 2 2 6.690133 6h B0AC93h XX6h 02Ch 056h 093h 12.288 98.304 2 2 7.281778 7h 482296h XX7h 012h 011h 096h Table 48 PLL Frequency Examples LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input. COMPANDING The WM8985 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. REGISTER ADDRESS R5 (05h) Companding Control BIT LABEL DEFAULT DESCRIPTION 2:1 ADC_COMP 0 ADC companding 00 = off 01 = reserved 10 = μ-law 11 = A-law 4:3 DAC_COMP 0 DAC companding 00 = off 01 = reserved 10 = μ-law 11 = A-law 5 WL8 0 0 = off 1 = device operates in 8-bit mode. Table 49 Companding Control w PD, Rev 4.6, July 2009 83 WM8985 Production Data Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: μ-law (where μ=255 for the U.S. and Japan): F(x) = ln( 1 + μ|x|) / ln( 1 + μ) -1 ≤ x ≤ 1 A law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) } for x ≤ 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA) } for 1/A ≤ x ≤ 1 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for μ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s of data. Companding converts 13 bits (μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to use 8 BCLK’s per LRC frame. When using DSP mode B, this allows 8-bit data words to be output consecutively every 8 BCLK’s and can be used with 8-bit data words using the A-law and u-law companding functions. BIT7 BIT[6:4] BIT[3:0] SIGN EXPONENT MANTISSA Table 50 8-bit Companded Word Composition u-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input Figure 39 μ-Law Companding w PD, Rev 4.6, July 2009 84 WM8985 Production Data A-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.2 0.4 0.6 0.8 1 Normalised Input Figure 40 A-Law Companding w PD, Rev 4.6, July 2009 85 WM8985 Production Data GENERAL PURPOSE INPUT/OUTPUT The WM8985 has three dual purpose input/output pins. • CSB/GPIO1: CSB / GPIO1 pin • L2/GPIO2: Left channel line input / headphone detection input • R2/GPIO3: Right channel line input / headphone detection input The GPIO2 and GPIO3 functions are provided for use as jack detection inputs. The GPIO1 function is provided for use as jack detection input or general purpose output. The default configuration for the CSB/GPIO1 is to be an input. When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection, depending on how the MODE pin is set. Table 45 illustrates the functionality of the GPIO1 pin when used as a general purpose output. REGISTER ADDRESS R8 (08h) GPIO Control R14(0Eh) BIT LABEL DEFAULT DESCRIPTION 2:0 GPIO1SEL 000 CSB/GPIO1 pin function select: 000 = input (CSB / Jack detection: depending on MODE setting) 001 = reserved 010 = Temp ok 011 = Amute active 100 = PLL clk output 101 = PLL lock 110 = logic 0 111 = logic 1 3 GPIO1POL 0 GPIO1 Polarity invert 0 = Non inverted 1 = Inverted 6 GPIO1GPD 0 GPIO1 Internal pull-down enable: 0 = Internal pull-down disabled 1 = Internal pull-down enabled 7 GPIO1GPU 0 GPIO1 Internal pull-up enable: 0 = Internal pull-up disabled 1 = Internal pull-up enabled 8 GPIO1GP 0 GPIO1 Open drain enable 0 = Open drain disabled 1 = Open drain enabled 5:4 OPCLKDIV 00 PLL Output clock division ratio 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4 Table 45 CSB/GPIO Control Note: If MODE is set to 3 wire mode, CSB/GPIO1 is used as CSB input irrespective of the GPIO1SEL[2:0] bits. Register R14(0Eh) bits [5:4] (OPCLKDIV) are used to control the PLL output clock division ratio and also the highpass filter cut-off in applications mode (HPFCUT). OPCLKDIV and HPFCUT cannot be set independently. w PD, Rev 4.6, July 2009 86 WM8985 Production Data For further details of the jack detect operation see the OUTPUT SWITCHING section. OUTPUT SWITCHING (JACK DETECT) When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch control input to automatically disable one set of outputs and enable another; the most common use for this functionality is as jack detect circuitry. The L2/GPIO2 and R2/GPIO3 pins can also be used for this purpose. The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a slow clock with period 221 x MCLK and is enabled by the SLOWCLKEN bit. Notes: 1. The SLOWCLKEN bit must be enabled for the jack detect circuitry to operate. 2. The GPIOPOL bit is not relevant for jack detection, it is the signal detected at the pin which is used Switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0 are the output enable signals which are used if the selected jack detection pin is at logic 0 (after debounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce). The jack detection enables operate as follows: All OUT_EN signals have an AND function performed with their normal enable signals (in Table 39). When an output is normally enabled as per Table 39, the selected jack detection enable (controlled by selected jack detection pin polarity) is set 0; it will turn the output off. If the normal enable signal is already OFF (0), the jack detection signal will have no effect due to the AND function. During jack detection if the user desires an output to be un-changed whether the jack is in or not, both the JD_EN settings, i.e. JD_EN0 and JD_EN1, should be set to 0000. If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs to be controlled as normal via the normal output enables found in Table 39. w PD, Rev 4.6, July 2009 87 WM8985 Production Data BIT LABEL DEFAULT DESCRIPTION REGISTER ADDRESS R9 (09h) GPIO control R13 (00h) 5:4 JD_SEL 00 Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = Reserved 6 JD_EN 0 Jack Detection Enable 0 = disabled 1 = enabled 3:0 JD_EN0 0000 Output enables when selected jack detection input is logic 0. [0]= OUT1_EN_0 [1]= OUT2_EN_0 [2]= OUT3_EN_0 [3]= OUT4_EN_0 7:4 JD_EN1 0000 Output enables when selected jack detection input is logic 1 [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1 Table 46 Jack Detect Register Control Bits CONTROL INTERFACE SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS The control interface can operate as either a 3-wire or 2-wire control interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 47. The WM8985 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are register address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 data bits in each control register. MODE INTERFACE FORMAT Low 2 wire High 3 wire Table 47 Control Interface Mode Selection 3-WIRE SERIAL CONTROL MODE In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits. Figure 39 3-Wire Serial Control Interface w PD, Rev 4.6, July 2009 88 WM8985 Production Data 2-WIRE SERIAL CONTROL MODE The WM8985 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8985). The WM8985 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8985, the WM8985 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in write only mode, the WM8985 returns to the idle condition and waits for a new start condition and valid address. During a write, once the WM8985 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8985 register address plus the first bit of register data). The WM8985 then acknowledges the first data byte by driving SDIN low for one clock cycle. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8985 acknowledges again by pulling SDIN low. Transfer is complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8985 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the control interface returns to the idle condition. DEVICE ADDRESS (7 BITS) SDIN RD / WR BIT ACK (LOW) CONTROL BYTE 1 (BITS 15 TO 8) ACK (LOW) CONTROL BYTE 1 (BITS 7 TO 0) ACK (LOW) SCLK START register address and 1st register data bit STOP remaining 8 bits of register data Figure 40 2-Wire Serial Control Interface In 2-wire mode the WM8985 has a fixed device address, 0011010. RESETTING THE CHIP The WM8985 can be reset by performing a write of any value to the software reset register (address 0h). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are initially set to default when the device is powered up. POWER SUPPLIES The WM8985 requires four separate power supplies: AVDD1 and AGND1: Analogue supply, powers all internal analogue functions and output drivers LOUT1, ROUT1, OUT3 and OUT4. AVDD1 must be between 2.5V and 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphones). Higher AVDD1 will improve audio quality. AVDD2 and AGND2: Output driver supplies, power LOUT2 and ROUT2. AVDD2 must be between 2.5V and 3.6V. AVDD2 can be tied to AVDD1, but it requires separate layout and decoupling capacitors to curb harmonic distortion. DCVDD: Digital core supply, powers all digital functions except the audio and control interface pads. DCVDD must be between 1.71V and 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD must be between 1.71V and 3.6V. DBVDD return path is through DGND. It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths. w PD, Rev 4.6, July 2009 89 WM8985 Production Data POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR128 and DACOSR128 the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R10 (0Ah) DAC control 3 DACOSR128 0 DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) R14 (0Eh) ADC control 3 ADCOSR128 0 ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Table 48 ADC and DAC Oversampling Rate Selection LOW POWER MODE If only DAC or ADC functionality is required, the WM8985 can be put into a low power mode. In this mode, the DSP core runs at half of the normal rate, reducing digital power consumption of the core by half. For DAC low power only, 3D enhancement with 2-Band equaliser functionality is permitted, where only Band 1 (low shelf) and Band 5 (high shelf) can be used. For ADC low power, the equaliser and 3D cannot be used. REGISTER ADDRESS R7 (07h) Additional Ctrl BIT 8 LABEL DEFAULT M128ENB 0 DESCRIPTION 0 = low power mode enabled 1 = low power mode disabled Table 49 DSP Core Low Power Mode Control There are 3 modes of low power operation, as detailed below. The device will not enter low power unless in one of these register configurations, regardless of M128ENB. For pop-free operation of the device it is recommended to change the M128ENB low power functionality only when both the DACs and ADCs are disabled, i.e. when DACENL=0, DACENR=0, ADCENL=0 and ADCENR=0. FUNCTION REGISTER BITS SETTING DESCRIPTION ADC low power M128ENB ADCENL ADCENR DACENL DACENR EQ3DMODE 0 1 1 0 0 1 (DAC path) Either or both of ADCENL and ADCENR must be set (mono or stereo mode) DAC low power M128ENB ADCENL ADCENR DACENL DACENR 0 0 0 1 1 Either or both of DACENL and DACENR must be set (mono or stereo mode) EQ3DMODE = 0: EQ in ADC path EQ3DMODE = 1: EQ in DAC path Table 50 DSP Core Low Power Modes for ADC Only and DAC Only Modes w PD, Rev 4.6, July 2009 90 WM8985 Production Data VMID The analogue circuitry will not operate unless VMID is enabled. The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit. REGISTER ADDRESS R1 (01h) Power management 1 BIT 1:0 LABEL DEFAULT VMIDSEL 00 DESCRIPTION Reference string impedance to VMID pin 00 = off (250kΩ VMID to AGND1) 01=75kΩ 10=300kΩ 11=5kΩ Table 51 VMID Impedance Control BIASEN The analogue amplifiers will not operate unless BIASEN is enabled. REGISTER ADDRESS R1 (01h) Power management 1 BIT 3 LABEL BIASEN DEFAULT 0 DESCRIPTION Analogue amplifier bias control 0 = disabled 1 = enabled Table 52 Analogue Bias Control POP MINIMISATION POBCTRL WM8985 has two bias generators. A noisy bias derived from AVDD and a low noise bias derived from VMID. POBCTRL is use to switch between the two bias generators. During power up, the AVDD derived bias is available as soon as AVDD is applied; the VMID derived bias is available once the VMID node has charged up. REGISTER ADDRESS R42 OUT4 to ADC BIT 2 LABEL POB CTRL DEFAULT 0 DESCRIPTION VMID independent current bias control 0 = Disable VMID independent current bias 1 = Enable VMID independent current bias Note: POBCTRL should be asserted during power up to minimize pops and then deasserted at the end of the power up sequence to give best performance. Refer to Recommended Power Up/Down w PD, Rev 4.6, July 2009 91 WM8985 Production Data REGISTER MAP ADDR B[15:9] REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1 B0 DEC HEX DEF’T VAL (HEX) 0 00 Software Reset 1 01 Power manage’t 1 0 OUT4MIX EN OUT3MIX EN PLLEN MICBEN BIASEN BUFIOEN 2 02 Power manage’t 2 ROUT1EN LOUT1EN SLEEP BOOST ENR BOOST ENL INPGA ENR INPPGA ENL ADCENR ADCENL 000 3 03 Power manage’t 3 OUT4EN OUT3EN ROUT2EN LOUT2EN LMIXEN DACENR 4 04 Audio Interface BCP LRP WL 5 05 Companding ctrl 6 06 Clock Gen ctrl CLKSEL 7 07 Additional ctrl M128ENB 8 08 GPIO Stuff GPIO1GP 9 09 Jack detect control 0 0 JD_EN 10 0A DAC Control 0 0 SOFT MUTE 11 0B Left DAC digital Vol DACVU DACLVOL[7:0] 12 0C Right DAC dig’l Vol DACVU DACRVOL[7:0] 13 0D Jack Detect Control 0 14 0E ADC Control Software reset 0 DACENL 000 DLRSWAP ALRSWAP MONO 050 DAC_COMP[1:0] ADC_COMP[1:0] LOOP BACK 000 MS 140 SLOWCLK EN 080 RMIXEN MCLKDIV[2:0] BCLKDIV[2:0] 0 DCLKDIV[3:0] GPIO1GPU GPIO1GPD SR[2:0] 0 0 JD_SEL 0 0 GPIO1POL HPFAPP HPFCUT[2:0] 0 OPCLKDIV[1:0] 000 GPIO1SEL[2:0] 0 0 DACOSR 128 AMUTE 0 0 DACRPOL DACLPOL 000 000 0FF 0FF JD_EN0[3:0] 000 0 100 JD_EN1[3:0] HPFEN 000 FMT 0 WL8 VMIDSEL[1:0] ADCOSR 128 ADCRPOL ADCLPOL 15 0F Left ADC Digital Vol ADCVU ADCLVOL[7:0] 0FF 16 10 Right ADC Digital Vol ADCVU ADCRVOL[7:0] 0FF 18 12 EQ1 – low shelf EQ3DMODE 0 EQ1C[1:0] EQ1G[4:0] 12C 19 13 EQ2 – peak 1 EQ2BW 0 EQ2C[1:0] EQ2G[4:0] 02C 20 14 EQ3 – peak 2 EQ3BW 0 EQ3C[1:0] EQ3G[4:0] 02C 21 15 EQ4 – peak 3 EQ4BW 0 EQ4C[1:0] EQ4G[4:0] 02C 22 16 EQ5 – high shelf 0 0 EQ5C[1:0] EQ5G[4:0] 23 17 Class D Control CLASSDEN 0 24 18 DAC Limiter 1 LIMEN 25 19 DAC Limiter 2 0 0 27 1B Notch Filter 1 NFU NFEN NFA0[13:7] 000 28 1C Notch Filter 2 NFU 0 NFA0[6:0] 000 29 1D Notch Filter 3 NFU 0 NFA1[13:7] 000 30 1E Notch Filter 4 NFU 0 NFA1[6:0] 32 20 ALC control 1 ALCSEL[1:0] 0 33 21 ALC control 2 0 ALCHLD[3:0] 34 22 ALC control 3 ALCMODE 35 23 Noise Gate 0 0 0 0 0 36 24 PLL N 0 0 0 0 PLLPRE SCALE 37 25 PLL K 1 0 0 0 38 26 PLL K 2 PLLK[17:9] 093 39 27 PLL K 3 PLLK[8:0] 0E9 41 29 3D control 42 2A OUT4 to ADC 43 2B Beep control w 0 0 0 02C 10 0 032 LIMBOOST[3:0] 000 000 ALCMAX[2:0] 038 ALCMIN[2:0] ALCDCY[3:0] ALCLVL[3:0] 00B ALCATK[3:0] 032 NGEN 000 NGTH[2:0] 008 PLLN[3:0] 00C PLLK[23:18] 000 DEPTH3D[3:0] OUT4_2ADCVOL[2:0] BYPL2 RMIX BYPR2 LMIX 0 008 LIMATK[3:0] LIMDCY[3:0] LIMLVL[2:0] 0 OUT4_2 LNR 0 0 POBCTRL 0 0 000 0 0 0 0 0 0 000 PD, Rev 4.6, July 2009 92 WM8985 Production Data ADDR B[15:9] REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1 B0 RIN2 INPPGA RIP2 INPPGA 0 L2_2 INPPGA LIN2 INPPGA LIP2 INPPGA DEC HEX DEF’T VAL (HEX) 003 44 2C Input ctrl MBVSEL 0 R2_2 INPPGA 45 2D Left INP PGA gain ctrl INPGAVU INPPGA ZCL INPPGA MUTEL INPPGAVOLL[5:0] 010 46 2E Right INP PGA gain ctrl INPGAVU INPPGA ZCR INPPGA MUTER INPPGAVOLR[5:0] 010 47 2F Left ADC Boost ctrl PGA BOOSTL 0 L2_2BOOSTVOL[2:0] 0 AUXL2BOOSTVOL[2:0] 100 48 30 Right ADC Boost ctrl PGA BOOSTR 0 R2_2BOOSTVOL[2:0] 0 AUXR2BOOSTVOL[2:0] 100 49 31 Output ctrl 0 0 50 32 Left mixer ctrl AUXLMIXVOL[2:0] AUXL2 LMIX 51 33 Right mixer ctrl AUXRMIXVOL[2:0] AUXR2 RMIX 52 34 LOUT1 (HP) volume ctrl OUT1VU LOUT1ZC LOUT1 MUTE LOUT1VOL[5:0] 039 53 35 ROUT1 (HP) volume ctrl OUT1VU ROUT1ZC ROUT1 MUTE ROUT1VOL[5:0] 039 54 36 LOUT2 (SPK) volume ctrl OUT2VU LOUT2ZC LOUT2 MUTE LOUT2VOL[5:0] 039 55 37 ROUT2 (SPK) volume ctrl OUT2VU ROUT2ZC ROUT2 MUTE ROUT2VOL[5:0] 039 56 38 OUT3 mixer ctrl 0 0 OUT3 MUTE 0 0 OUT4_ 2OUT3 BYPL2 OUT3 LMIX2 OUT3 LDAC2 OUT3 001 57 39 OUT4 (MONO) mixer ctrl 0 OUT 3_2OUT4 OUT4 MUTE OUT4 ATTN LMIX2 OUT4 LDAC2 OUT4 BYPR2 OUT4 RMIX2 OUT4 RDAC2 OUT4 001 61 3D Bias Control BIASCUT 0 0 0 0 000 DACL2 RMIX DACR2 LMIX TSDEN VROI 002 BYPLMIXVOL[2:0] BYPL2 LMIX DACL2 LMIX 001 BYPRMIXVOL[2:0] BYPR2 RMIX DACR2 RMIX 001 0 0 00 TSOP CTRL 00 Table 53 WM8985 Register Map w PD, Rev 4.6, July 2009 93 WM8985 Production Data REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as “Reserved” should not be changed from the default. REGISTER ADDRESS BIT 0 (00h) [8:0] 1 (01h) 8 2 (02h) LABEL DEFAULT DESCRIPTION REFER TO RESET N/A 0 Reserved. Initialise to 0 7 OUT4MIXEN 0 OUT4 mixer enable 0=disabled 1=enabled Power Management 6 OUT3MIXEN 0 OUT3 mixer enable 0=disabled 1=enabled Power Management 5 PLLEN 0 PLL enable 0=PLL off 1=PLL on Master Clock and Phase Locked Loop (PLL) 4 MICBEN 0 Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Input Signal Path 3 BIASEN 0 Analogue amplifier bias control 0=disabled 1=enabled Power Management 2 BUFIOEN 0 Unused input/output tie off buffer enable 0=disabled 1=enabled Power Management 1:0 VMIDSEL[1:0] 00 Reference string impedance to VMID pin 00 = off (250kΩ VMID to AGND1) 01=75kΩ 10=300kΩ 11=5kΩ Power Management 8 ROUT1EN 0 ROUT1 output enable 0=disabled 1=enabled Power Management 7 LOUT1EN 0 LOUT1 output enable 0=disabled 1=enabled Power Management 6 SLEEP 0 0 = normal device operation 1 = residual current reduced in device standby mode Power Management 5 BOOSTENR 0 Right channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Power Management 4 BOOSTENL 0 Left channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Power Management 3 INPPGAENR 0 Right channel input PGA enable 0 = disabled 1 = enabled Power Management 2 INPPGAENL 0 Left channel input PGA enable 0 = disabled 1 = enabled Power Management w Software reset Resetting the Chip PD, Rev 4.6, July 2009 94 WM8985 Production Data REGISTER ADDRESS 3 (03h) BIT LABEL DESCRIPTION REFER TO 1 ADCENR 0 Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled Analogue to Digital Converter (ADC) 0 ADCENL 0 Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled Analogue to Digital Converter (ADC) 8 OUT4EN 0 OUT4 enable 0 = disabled 1 = enabled Power Management 7 OUT3EN 0 OUT3 enable 0 = disabled 1 = enabled Power Management 6 ROUT2EN 0 ROUT2 enable 0 = disabled 1 = enabled Power Management 5 LOUT2EN 0 LOUT2 enable 0 = disabled 1 = enabled Power Management 0 Reserved. Initialise to 0 3 RMIXEN 0 Right output channel mixer enable: 0 = disabled 1 = enabled Analogue Outputs 2 LMIXEN 0 Left output channel mixer enable: 0 = disabled 1 = enabled Analogue Outputs 1 DACENR 0 Right channel DAC enable 0 = DAC disabled 1 = DAC enabled Analogue Outputs 0 DACENL 0 Left channel DAC enable 0 = DAC disabled 1 = DAC enabled Analogue Outputs 8 BCP 0 BCLK polarity 0=normal 1=inverted Digital Audio Interfaces 7 LRP 0 LRC clock polarity 0=normal 1=inverted Digital Audio Interfaces 6:5 WL 10 Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Digital Audio Interfaces 4:3 FMT 10 Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Digital Audio Interfaces 4 4 (04h) DEFAULT w PD, Rev 4.6, July 2009 95 WM8985 REGISTER ADDRESS 5 (05h) 6 (06h) Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO 2 DLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=DAC data appear in ‘left’ phase of LRC 1=DAC data appears in ‘right’ phase of LRC Digital Audio Interfaces 1 ALRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=ADC data appear in ‘left’ phase of LRC 1=ADC data appears in ‘right’ phase of LRC Digital Audio Interfaces 0 MONO 0 Selects between stereo and mono device operation: 0=Stereo device operation 1=Mono device operation. Data appears in ‘left’ phase of LRC Digital Audio Interfaces 000 Reserved. Initialise to 0 5 8:6 WL8 0 Companding Control 8-bit mode 0=off 1=device operates in 8-bit mode Digital Audio Interfaces 4:3 DAC_COMP 00 DAC companding 00=off (linear mode) 01=reserved 10=μ-law 11=A-law Digital Audio Interfaces 2:1 ADC_COMP 00 ADC companding 00=off (linear mode) 01=reserved 10=μ-law 11=A-law Digital Audio Interfaces 0 LOOPBACK 0 Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Digital Audio Interfaces 8 CLKSEL 1 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Digital Audio Interfaces 7:5 MCLKDIV 010 Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Digital Audio Interfaces w PD, Rev 4.6, July 2009 96 WM8985 Production Data REGISTER ADDRESS BIT 4:2 LABEL BCLKDIV 1 7 (07h) 8 (08h) DEFAULT DESCRIPTION REFER TO 000 Configures the BCLK output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Digital Audio Interfaces 0 Reserved. Initialise to 0 0 MS 0 Sets the chip to be master over LRC and BCLK 0=BCLK and LRC clock are inputs 1=BCLK and LRC clock are outputs generated by the WM8985 (MASTER) Digital Audio Interfaces 8 M128ENB 0 0 = low power mode enabled 1 = low power mode disabled Additional Control 7:4 DCLKDIV 1000 Controls clock division from SYSCLK to generate suitable class D clock. Recommended class D clock frequency = 1.4MHz. 0000 = divide by 1 0010 = divide by 2 0011 = divide by 3 0100 = divide by 4 0101 = divide by 5.5 0110 = divide by 6 1000 = divide by 8 1001 = divide by 12 1010 = divide by 16 Class A / D Headphone Outputs 3:1 SR 000 Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Audio Sample Rates 0 SLOWCLKEN 0 Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled Analogue Outputs 8 GPIO1GP 0 GPIO1 Open drain enable 0 = Open drain disabled 1 = Open drain enabled General Purpose Input/Output (GPIO) 7 GPIO1GPU 0 GPIO1 Internal pull-up enable: 0 = Internal pull-up disabled 1 = Internal pull-up enabled General Purpose Input/Output (GPIO) w PD, Rev 4.6, July 2009 97 WM8985 REGISTER ADDRESS 9 (09h) 10 (0Ah) Production Data BIT LABEL DESCRIPTION REFER TO 6 GPIO1GPD 0 GPIO1 Internal pull-down enable: 0 = Internal pull-down disabled 1 = Internal pull-down enabled General Purpose Input/Output (GPIO) 3 GPIO1POL 0 GPIO1 Polarity invert 0=Non inverted 1=Inverted General Purpose Input/Output (GPIO) 2:0 GPIO1SEL [2:0] 000 CSB/GPIO1 pin function select: 000= input (CSB/jack detection: depending on MODE setting) 001= reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=logic 1 111=logic 0 General Purpose Input/Output (GPIO) 00 Reserved. Initialise to 00 8:7 6 JD_EN 0 Jack Detection Enable 0=disabled 1=enabled Output Switching (Jack Detect) 5:4 JD_SEL 00 Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = Reserved Output Switching (Jack Detect) 3:0 0 Reserved. Initialise to 0 8:7 00 Reserved. Initialise to 0 0 Softmute enable: 0=Disabled 1=Enabled 6 SOFTMUTE 5:4 11 (0Bh) DEFAULT Output Signal Path 00 Reserved. Initialise to 0 3 DACOSR128 0 DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Power Management 2 AMUTE 0 Automute enable 0 = Amute disabled 1 = Amute enabled Output Signal Path 1 DACPOLR 0 Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Output Signal Path 0 DACPOLL 0 Left DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Output Signal Path 8 DACVU N/A DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Digital to Analogue Converter (DAC) w PD, Rev 4.6, July 2009 98 WM8985 Production Data REGISTER ADDRESS 12 (0Ch) 13 (0Dh) 14 (0Eh) BIT LABEL DEFAULT DESCRIPTION REFER TO 7:0 DACVOLL 11111111 Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB … 0.5dB steps up to 1111 1111 = 0dB Digital to Analogue Converter (DAC) 8 DACVU N/A DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Output Signal Path 7:0 DACVOLR 11111111 Right DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Output Signal Path 8 0 Reserved. Initialise to 0 7:4 JD_EN1 0000 Output enabled when selected jack detection input is logic 1 [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1 Output Switching (Jack Detect) 3:0 JD_EN0 0000 Output enabled when selected jack detection input is logic 0. [0]= OUT1_EN_0 [1]= OUT2_EN_0 [2]= OUT3_EN_0 [3]= OUT4_EN_0 Output Switching (Jack Detect) 8 HPFEN 1 High Pass Filter Enable 0=disabled 1=enabled Analogue to Digital Converter (ADC) 7 HPFAPP 0 Select audio mode or application mode st 0=Audio mode (1 order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Analogue to Digital Converter (ADC) 6:4 HPFCUT / OPCLKDIV 000 Application mode cut-off frequency See Table 16 for details. Analogue to Digital Converter (ADC) PLL Output Clock Division Ratio 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4 General Purpose Input/Output (GPIO) Note: HPCUT and OPCLKDIV cannot be set independently 3 ADCOSR 128 0 0 Reserved. Initialise to 0 ADCRPOL 0 ADC right channel polarity adjust: 0=normal 1=inverted 2 1 w ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Power Management Analogue to Digital Converter (ADC) PD, Rev 4.6, July 2009 99 WM8985 REGISTER ADDRESS 15 (0Fh) 16 (10h) 18 (12h) Production Data BIT LABEL DEFAULT DESCRIPTION 0 ADCLPOL 0 ADC left channel polarity adjust: 0=normal 1=inverted Analogue to Digital Converter (ADC) 8 ADCVU N/A ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 16 or 17) Analogue to Digital Converter (ADC) 7:0 ADCVOLL 11111111 Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Analogue to Digital Converter (ADC) 8 ADCVU N/A ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 16 or 17) Analogue to Digital Converter (ADC) 7:0 ADCVOLR 11111111 Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Analogue to Digital Converter (ADC) 8 EQ3DMODE 1 0 = Equaliser and 3D Enhancement applied to ADC path 1 = Equaliser and 3D Enhancement applied to DAC path Output Signal Path 0 Reserved. Initialise to 0 EQ1C 01 EQ Band 1 Cut-off Frequency: 7 6:5 00=80Hz 01=105Hz 10=135Hz 11=175Hz 19 (13h) Output Signal Path 4:0 EQ1G 01100 EQ Band 1 Gain Control. See Table 31 for details. Output Signal Path 8 EQ2BW 0 EQ Band 2 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Output Signal Path 0 Reserved. Initialise to 0 EQ2C 01 EQ Band 2 Centre Frequency: 7 6:5 00=230Hz 01=300Hz 10=385Hz 11=500Hz 20 (14h) REFER TO Output Signal Path 4:0 EQ2G 01100 EQ Band 2 Gain Control. See Table 31 for details. Output Signal Path 8 EQ3BW 0 EQ Band 3 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Output Signal Path 0 Reserved. Initialise to 0 EQ3C 01 EQ Band 3 Centre Frequency: 7 6:5 00=650Hz Output Signal Path 01=850Hz 10=1.1kHz 11=1.4kHz w PD, Rev 4.6, July 2009 100 WM8985 Production Data REGISTER ADDRESS 21 (15h) BIT LABEL DEFAULT DESCRIPTION REFER TO 4:0 EQ3G 01100 EQ Band 3 Gain Control. See Table 31 for details. Output Signal Path 8 EQ4BW 0 EQ Band 4 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Output Signal Path 0 Reserved. Initialise to 0 EQ4C 01 EQ Band 4 Centre Frequency: 7 6:5 Output Signal Path 00=1.8kHz 01=2.4kHz 10=3.2kHz 11=4.1kHz 4:0 22 (16h) EQ4G 8:7 6:5 EQ5C 01100 EQ Band 4 Gain Control. See Table 31 for details. Output Signal Path 0 Reserved. Initialise to 0 Output Signal Path 01 EQ Band 5 Cut-off Frequency: Output Signal Path 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz 4:0 EQ5G 01100 EQ Band 5 Gain Control. See Table 31 for details. Output Signal Path 23 (17h) 8 CLASSDEN 0 Enable signal for class D mode on LOUT2 and ROUT2 0 = Class AB mode 1 = Class D mode Class D Control 000 1000 Reserved. 24 (18h) 8 LIMEN 0 Enable the DAC digital limiter: 0=disabled 1=enabled Output Signal Path 7:4 LIMDCY 0011 DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms Output Signal Path 7:0 0111=96ms 1000=192ms 1001=384ms 1010=768ms w PD, Rev 4.6, July 2009 101 WM8985 REGISTER ADDRESS Production Data BIT 3:0 LABEL LIMATK DEFAULT 0010 DESCRIPTION REFER TO DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. Output Signal Path 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms 25 (19h) 27 (1Bh) 28 (1Ch) 00 Reserved. Initialise to 0 6:4 8:7 LIMLVL 000 Programmable signal threshold level (determines level at which the DAC limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB Output Signal Path 3:0 LIMBOOST 0000 DAC Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB … (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved Output Signal Path 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) 7 NFEN 0 Notch filter enable: 0=Disabled 1=Enabled Analogue to Digital Converter (ADC) 6:0 NFA0[13:7] 0000000 Notch Filter a0 coefficient, bits [13:7] Analogue to Digital Converter (ADC) 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) 0 Reserved. Initialise to 0 NFA0[6:0] 0000000 Notch Filter a0 coefficient, bits [6:0] 7 6:0 w Analogue to Digital Converter (ADC) PD, Rev 4.6, July 2009 102 WM8985 Production Data REGISTER ADDRESS 29 (1Dh) BIT 8 LABEL 0 Reserved. Initialise to 0 6:0 NFA1[13:7] 0000000 Notch Filter a1 coefficient, bits [13:7] Analogue to Digital Converter (ADC) 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) 0 Reserved. Initialise to 0 6:0 NFA1[6:0] 0000000 Notch Filter a1 coefficient, bits [6:0] Analogue to Digital Converter (ADC) 8:7 ALCSEL 00 ALC function select: 00=ALC off 01=ALC right only 10=ALC left only 11=ALC both on Input Limiter/ Automatic Level Control (ALC) 0 Reserved. Initialise to 0 5:3 ALCMAXGAIN 111 Set Maximum Gain of PGA 111=+35.25dB 110=+29.25dB 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB Input Limiter/ Automatic Level Control (ALC) 2:0 ALCMINGAIN 000 Set minimum gain of PGA 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB Input Limiter/ Automatic Level Control (ALC) 7:4 ALCHLD 0000 ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s Input Limiter/ Automatic Level Control (ALC) 3:0 ALCLVL 1011 ALC target – sets signal level at ADC input Input Limiter/ Automatic Level Control (ALC) 6 33 (21h) REFER TO 0 7 32 (20h) DESCRIPTION NFU 7 30 (1Eh) DEFAULT Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. 1111 : -1.5dBFS 1110 : -1.5dBFS 1101 : -3dBFS 1100 : -4.5I...... (-1.5dB steps) 0001 : -21dBFS 0000 : -22.5dBFS w Analogue to Digital Converter (ADC) PD, Rev 4.6, July 2009 103 WM8985 REGISTER ADDRESS 34 (22h) Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO 8 ALCMODE 0 Determines the ALC mode of operation: 0=ALC mode 1=Limiter mode Input Limiter/ Automatic Level Control (ALC) 7:4 ALCDCY [3:0] 0011 Decay (gain ramp-up) time (ALCMODE ==0) Input Limiter/ Automatic Level Control (ALC) Per step Per 6dB 90% of range 0000 410us 3.3ms 24ms 0001 820us 6.6ms 48ms 0010 1.64ms 13.1ms 192ms … (time doubles with every step) 1010 or higher 0011 420ms 3.36s 24.576s Decay (gain ramp-up) time (ALCMODE ==1) Per step Per 6dB 90% of range 0000 90.8us 726.4us 5.26ms 0001 181.6us 1.453ms 10.53ms 0010 363.2us 2.905ms 21.06ms … (time doubles with every step) 1010 3:0 ALCATK 0010 93ms 744ms 5.39s ALC attack (gain ramp-down) time (ALCMODE == 0) Per step Per 6dB 90% of range 0000 104us 832us 6ms 0001 208us 1.664ms 12ms 0010 416us 3.328ms 24.1ms Input Limiter/ Automatic Level Control (ALC) … (time doubles with every step) 1010 or higher 0010 106ms 852ms 6.18s ALC attack (gain ramp-down) time (ALCMODE == 1) Per step Per 6dB 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms … (time doubles with every step) 1010 35 (23h) 36 (24h) 8:4 23.2ms 186ms 00000 Reserved. Initialise to 0 1.348s 3 NGEN 0 ALC Noise gate function enable 1 = enable 0 = disable Input Limiter/ Automatic Level Control (ALC) 2:0 NGTH 000 ALC Noise gate threshold: 000=-39dB 001=-45dB 010=-51db … (6dB steps) 111=-81dB Input Limiter/ Automatic Level Control (ALC) 0000 Reserved. Initialise to 0 8:5 w PD, Rev 4.6, July 2009 104 WM8985 Production Data REGISTER ADDRESS 37 (25h) BIT LABEL DEFAULT DESCRIPTION REFER TO 4 PLLPRESCALE 0 0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input to PLL Master Clock and Phase Locked Loop (PLL) 3:0 PLLN[3:0] 1000 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Master Clock and Phase Locked Loop (PLL) 000 Reserved. Initialise to 0 5:0 PLLK[23:18] 01100 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 38 (26h) 8:0 PLLK[17:9] 010010011 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 39 (27h) 8:0 PLLK[8:0] 011101001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 00000 Reserved. Initialise to 0 3:0 DEPTH3D 0000 Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3D effect) 3D Stereo Enhancement 8:6 OUT4_2ADCVOL 000 Controls the OUT4 to ADC input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain Analogue Outputs 5 OUT4_2LNR 0 OUT4 to L or R ADC input 0 = Right ADC input 1 = Left ADC input 00 Reserved. Initialise to 0 0 VMID independent current bias control 0 = Disable VMID independent current bias 1 = Enable VMID independent current bias 41 (29h) 42 (2Ah) 8:6 8:4 4:3 2 POBCTRL 1:0 43 (2Bh) 00 Reserved. Initialise to 0 8 BYPL2RMIX 0 Left bypass path (from the Left channel input PGA stage) to right output mixer 0 = not selected 1 = selected Analogue Outputs 7 BYPR2LMIX 0 Right bypass path (from the right channel input PGA stage) to Left output mixer 0 = not selected 1 = selected Analogue Outputs 6 0 Reserved. Initialise to 0 5 0 Reserved. Initialise to 0 4 0 Reserved. Initialise to 0 w PD, Rev 4.6, July 2009 105 WM8985 REGISTER ADDRESS 44 (2Ch) Production Data BIT LABEL DESCRIPTION REFER TO 3:1 000 0 0 Reserved. Initialise to 0 MBVSEL 0 Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD 0 Reserved. Initialise to 0 6 R2_2INPPGA 0 Connect R2 pin to right channel input PGA positive terminal. 0=R2 not connected to input PGA 1=R2 connected to input PGA amplifier positive terminal (constant input impedance). Input Signal Path 5 RIN2INPPGA 1 Connect RIN pin to right channel input PGA negative terminal. 0=RIN not connected to input PGA 1=RIN connected to right channel input PGA amplifier negative terminal. Input Signal Path 4 RIP2INPPGA 1 Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) Input Signal Path 0 Reserved. Initialise to 0 2 L2_2INPPGA 0 Connect L2 pin to left channel input PGA positive terminal. 0=L2 not connected to input PGA 1=L2 connected to input PGA amplifier positive terminal (constant input impedance). Input Signal Path 1 LIN2INPPGA 1 Connect LIN pin to left channel input PGA negative terminal. 0=LIN not connected to input PGA 1=LIN connected to input PGA amplifier negative terminal. Input Signal Path 0 LIP2INPPGA 1 Connect LIP pin to left channel input PGA amplifier positive terminal. 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) Input Signal Path 8 INPPGAU N/A INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) Input Signal Path 7 INPPGAZCL 0 Left channel input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Input Signal Path 6 INPPGAMUTEL 0 Mute control for left channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input Signal Path 5:0 INPPGAVOLL 010000 Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Input Signal Path 8 7 3 45 (2Dh) DEFAULT w Reserved. Initialise to 000 Input Signal Path PD, Rev 4.6, July 2009 106 WM8985 Production Data REGISTER ADDRESS 46 (2Eh) 47 (2Fh) BIT LABEL DESCRIPTION REFER TO 8 INPPGAU N/A INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) Input Signal Path 7 INPPGAZCR 0 Right channel input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Input Signal Path 6 INPPGAMUTER 0 Mute control for right channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input Signal Path 5:0 INPPGAVOLR 010000 Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Input Signal Path 8 PGABOOSTL 1 Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Input Signal Path 7 0 Reserved. Initialise to 0 L2_2BOOSTVOL 000 Controls the L2 pin to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage 0 Reserved. Initialise to 0 2:0 AUXL2BOOSTVOL 000 Controlٛ omm.ٛ arylliary amplifer to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage Input Signal Path 8 PGABOOSTR 1 Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Input Signal Path 0 Reserved. Initialise to 0 000 Controls the R2 pin to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage 0 Reserved. Initialise to 0 6:4 3 48 (30h) DEFAULT 7 6:4 R2_2BOOSTVOL 3 w Input Signal Path Input Signal Path PD, Rev 4.6, July 2009 107 WM8985 REGISTER ADDRESS Production Data BIT 2:0 49 (31h) LABEL AUXR2BOOSTVOL 8:7 DESCRIPTION REFER TO 000 Control auxilliary. amplifer to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage Input Signal Path 00 Reserved. Initialise to 0 6 DACL2RMIX 0 Left DAC output to right output mixer 0 = not selected 1 = selected Analogue Outputs 5 DACR2LMIX 0 Right DAC output to left output mixer 0 = not selected 1 = selected Analogue Outputs 00 Reserved. Initialise to 0 2 TSOPCTRL 0 Thermal Shutdown Output enable 0 = Disabled 1 = Enabled, i.e. all outputs will be disabled if TI set and the device junction temperature is more than 125ºC. Analogue Outputs 1 TSDEN 1 Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled Analogue Outputs 0 VROI 0 VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1kΩ 1: approx 30 kΩ Analogue Outputs 8:6 AUXLMIXVOL 000 Aux left channel input to left mixer volume control: 000 = -15dB 001 = -12dB … 101 = 0dB 110 = +3dB 111 = +6dB Analogue Outputs 5 AUXL2LMIX 0 Left Auxilliary input to left channel output mixer: 0 = not selected 1 = selected Analogue Outputs 4:2 BYPLMIXVOL 000 Left bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB … 101 = 0dB 110 = +3dB 111 = +6dB Analogue Outputs 1 BYPL2L MIX 0 Left bypass path (from the left channel input boost output) to left output mixer 0 = not selected 1 = selected Analogue Outputs 0 DACL2L MIX 1 Left DAC output to left output mixer 0 = not selected 1 = selected Analogue Outputs 4:3 50 (32h) DEFAULT w PD, Rev 4.6, July 2009 108 WM8985 Production Data REGISTER ADDRESS 51 (33h) 52 (34h) 53 (35h) BIT LABEL DEFAULT DESCRIPTION REFER TO 8:6 AUXRMIXVOL 000 Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB … 101 = 0dB 110 = +3dB 111 = +6dB Analogue Outputs 5 AUXR2RMIX 0 Right Auxilliary input to right channel output mixer: 0 = not selected 1 = selected Analogue Outputs 4:2 BYPRMIXVOL 000 Right bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB … 101 = 0dB 110 = +3dB 111 = +6dB Analogue Outputs 1 BYPR2RMIX 0 Right bypass path (from the right channel input boost output) to right output mixer 0 = not selected 1 = selected Analogue Outputs 0 DACR2RMIX 1 Right DAC output to right output mixer 0 = not selected 1 = selected Analogue Outputs 8 OUT1VU N/A LOUT1 and ROUT1 volumes do not update until a 1 is written to OUT1VU (in reg 52 or 53) Analogue Outputs 7 LOUT1ZC 0 Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Analogue Outputs 6 LOUT1MUTE 0 Left headphone output mute: 0 = Normal operation 1 = Mute Analogue Outputs 5:0 LOUT1VOL 111001 Left headphone output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Analogue Outputs 8 OUT1VU N/A LOUT1 and ROUT1 volumes do not update until a 1 is written to OUT1VU (in reg 52 or 53) Analogue Outputs 7 ROUT1ZC 0 Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Analogue Outputs 6 ROUT1MUTE 0 Right headphone output mute: 0 = Normal operation 1 = Mute Analogue Outputs 5:0 ROUT1VOL 111001 Right headphone output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Analogue Outputs w PD, Rev 4.6, July 2009 109 WM8985 REGISTER ADDRESS 54 (36h) 55 (37h) 56 (38h) Production Data BIT LABEL DESCRIPTION REFER TO 8 OUT2VU N/A LOUT2 and ROUT2 volumes do not update until a 1 is written to OUT2VU (in reg 54 or 55) Analogue Outputs 7 LOUT2ZC 0 Speaker volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Analogue Outputs 6 LOUT2MUTE 0 Left speaker output mute: 0 = Normal operation 1 = Mute Analogue Outputs 5:0 LOUT2VOL 111001 Left speaker output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Analogue Outputs 8 OUT2VU N/A LOUT2 and ROUT2 volumes do not update until a 1 is written to OUT2VU (in reg 54 or 55) Analogue Outputs 7 ROUT2ZC 0 Speaker volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Analogue Outputs 6 ROUT2MUTE 0 Right speaker output mute: 0 = Normal operation 1 = Mute Analogue Outputs 5:0 ROUT2VOL 111001 Right speaker output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Analogue Outputs 00 Reserved 0 0 = Output stage outputs OUT3 mixer 1 = Output stage muted – drives out VMID. Can be used as VMID buffer in this mode. (Not to be used for Capless HP pseudo GND) 8:7 6 OUT3MUTE 5:4 57 (39h) DEFAULT Analogue Outputs 00 Reserved. Initialise to 0 3 OUT4_2OUT3 0 OUT4 mixer output to OUT3 0 = disabled 1= enabled Analogue Outputs 2 BYPL2OUT3 0 Left ADC input to OUT3 0 = disabled 1= enabled Analogue Outputs 1 LMIX2OUT3 0 Left DAC mixer to OUT3 0 = disabled 1= enabled Analogue Outputs 0 LDAC2OUT3 1 Left DAC output to OUT3 0 = disabled 1= enabled Analogue Outputs 0 Reserved. Initialise to 0 7 8 OUT3_2OUT4 0 OUT3 mixer output to OUT4 0 = disabled 1 = enabled Analogue Outputs 6 OUT4MUTE 0 0 = Output stage outputs OUT4 mixer 1 = Output stage muted – drives out VMID. Can be used as VMID buffer in this mode. (Not to be used for Capless HP pseudo GND) Analogue Outputs w PD, Rev 4.6, July 2009 110 WM8985 Production Data REGISTER ADDRESS 61 (3Dh) BIT LABEL DEFAULT DESCRIPTION REFER TO 5 HALFSIG 0 0=OUT4 normal output 1=OUT4 attenuated by 6dB Analogue Outputs 4 LMIX2OUT4 0 Left DAC mixer to OUT4 0 = disabled 1= enabled Analogue Outputs 3 LDAC2OUT4 0 Left DAC to OUT4 0 = disabled 1= enabled Analogue Outputs 2 BYPR2OUT4 0 Right ADC input to OUT4 0 = disabled 1= enabled Analogue Outputs 1 RMIX2OUT4 0 Right DAC mixer to OUT4 0 = disabled 1= enabled Analogue Outputs 0 RDAC2OUT4 1 Right DAC output to OUT4 0 = disabled 1= enabled Analogue Outputs 8 0 Global bias control 0 = normal 1 = 0.5x Bias Control 7:0 000 0000 Reserved. Initialise to 0 w PD, Rev 4.6, July 2009 111 WM8985 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN +/- 0.025dB 0 TYP MAX UNIT ADC Filter Passband -6dB 0.454fs 0.5fs Passband Ripple +/- 0.025 Stopband Stopband Attenuation dB 0.546fs f > 0.546fs -60 Group Delay dB 21/fs ADC High Pass Filter High Pass Filter Corner Frequency -3dB 3.7 -0.5dB 10.4 -0.1dB 21.6 Hz DAC Filter Passband +/- 0.035dB 0 -6dB 0.454fs 0.5fs Passband Ripple +/-0.035 Stopband Stopband Attenuation Group Delay dB 0.546fs f > 0.546fs -55 dB 29/fs Table 54 Digital Filter Characteristics TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region w PD, Rev 4.6, July 2009 112 WM8985 Production Data DAC FILTER RESPONSES 3.05 0 3 -20 2.95 -40 2.9 Response (dB) Response (dB) 20 -60 -80 -100 2.85 2.8 2.75 -120 2.7 -140 2.65 2.6 -160 0 0.5 1 1.5 2 0 2.5 0.05 0.1 0.15 Figure 41 DAC Digital Filter Frequency Response (128xOSR) 0.25 0.3 0.35 0.4 0.45 0.5 0.45 0.5 Figure 42 DAC Digital Filter Ripple (128xOSR) 3.05 20 0 3 -20 2.95 -40 2.9 Response (dB) Response (dB) 0.2 Frequency (fs) Frequency (fs) -60 -80 -100 2.85 2.8 2.75 -120 2.7 -140 2.65 2.6 -160 0 0.5 1 1.5 2 0 2.5 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (fs) Frequency (fs) Figure 43 DAC Digital Filter Frequency Response (64xOSR) Figure 44 DAC Digital Filter Ripple (64xOSR) ADC FILTER RESPONSES 0.2 0 0.15 0.1 Response (dB) Response (dB) -20 -40 -60 -80 0.05 0 -0.05 -0.1 -100 -0.15 -0.2 -120 0 0.5 1 1.5 2 Frequency (Fs) Figure 45 ADC Digital Filter Frequency Response w 2.5 3 0 0.1 0.2 0.3 0.4 0.5 Frequency (Fs) Figure 46 ADC Digital Filter Ripple PD, Rev 4.6, July 2009 113 WM8985 Production Data HIGHPASS FILTER The WM8985 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cut-off frequency. 5 0 -5 Response (dB) -10 -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 45 Frequency (Hz) Figure 47 ADC Highpass Filter Response, HPFAPP=0 10 10 0 0 -10 -20 Response (dB) Response (dB) -10 -20 -30 -30 -40 -50 -40 -60 -50 -70 -80 -60 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 Frequency (Hz) Frequency (Hz) Figure 48 ADC Highpass Filter Responses (48kHz), HPFAPP=1, all cut-off settings shown Figure 49 ADC Highpass Filter Responses (24kHz), HPFAPP=1, all cut-off settings shown 10 0 -10 Response (dB) -20 -30 -40 -50 -60 -70 -80 -90 0 200 400 600 800 1000 1200 Frequency (Hz) Figure 50 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cut-off settings shown w PD, Rev 4.6, July 2009 114 WM8985 Production Data 5-BAND EQUALISER 15 15 10 10 5 5 Magnitude (dB) Magnitude (dB) The WM8985 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 51 to Figure 64 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of ±12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter. 0 -5 -5 -10 -10 -15 -1 10 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 -15 -1 10 5 Figure 51 EQ Band 1 Low Frequency Shelf Filter Cut-offs 15 15 10 10 5 5 0 -5 -10 -10 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 Figure 53 EQ Band 2 – Peak Filter Centre Frequencies, EQ2BW=0 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 0 -5 -15 -1 10 10 Figure 52 EQ Band 1 Gains for Lowest Cut-off Frequency Magnitude (dB) Magnitude (dB) 0 -15 -1 10 Figure 54 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 EQ Band 2 – Peak Filter Gains for Lowest Cut-off Frequency, EQ2BW=0 15 10 Magnitude (dB) 5 0 -5 -10 -15 -2 10 10 -1 10 0 1 10 Frequency (Hz) 10 2 10 3 10 4 Figure 55 EQ Band 2 – EQ2BW=0, EQ2BW=1 w PD, Rev 4.6, July 2009 115 Production Data 15 15 10 10 5 5 Magnitude (dB) Magnitude (dB) WM8985 0 0 -5 -5 -10 -10 -15 -1 10 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 -15 -1 10 Figure 56 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BFigure 57 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 EQ Band 3 – Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0 15 10 Magnitude (dB) 5 0 -5 -10 -15 -2 10 10 -1 10 0 1 10 Frequency (Hz) 10 2 10 3 10 4 Figure 58 EQ Band 3 – EQ3BW=0, EQ3BW=1 w PD, Rev 4.6, July 2009 116 WM8985 15 15 10 10 5 5 Magnitude (dB) Magnitude (dB) Production Data 0 0 -5 -5 -10 -10 -15 -1 10 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 -15 -1 10 5 Figure 59 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BW=0 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 Figure 60 EQ Band 4 – Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0 15 10 Magnitude (dB) 5 0 -5 -10 -15 -2 10 10 -1 10 0 1 10 Frequency (Hz) 10 2 10 3 10 4 15 15 10 10 5 5 Magnitude (dB) Magnitude (dB) Figure 61 EQ Band 4 – EQ3BW=0, EQ3BW=1 0 0 -5 -5 -10 -10 -15 -1 10 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 Figure 62 EQ Band 5 High Frequency Shelf Filter Cut-offs w -15 -1 10 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 Figure 63 EQ Band 5 Gains for Lowest Cut-off Frequency PD, Rev 4.6, July 2009 117 WM8985 Production Data Figure 64 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the peak filters. 20 15 Magnitude (dB) 10 5 0 -5 -10 -15 -1 10 10 0 10 1 2 10 Frequency (Hz) 10 3 10 4 10 5 Figure 64 Cumulative Frequency Boost/Cut w PD, Rev 4.6, July 2009 118 Production Data WM8985 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 65 External Component Diagram 1. When operating LOUT2 and ROUT2 in class D mode, it is recommended that LC filtering is placed as close to the LOUT2 and ROUT2 pins as possible. Low ESR components should be used for maximum efficiency. It is recommended that a filter, consisting of a 33μH inductor and a 220nF capacitor, is used for optimal performance. 2. The addition of ferrite beads to the outputs of LOUT2 and ROUT2 will suppress any potential interference noise produced by the class D switching clocks. w PD, Rev 4.6, July 2009 119 WM8985 Production Data PACKAGE DIAGRAM FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH CORNER TIE BAR 5 SEE DETAIL A D2 B D2/2 25 DM030.F D 32 L 1 24 INDEX AREA (D/2 X E/2) EXPOSED GROUND 6 PADDLE E2/2 A E2 17 E SEE DETAIL B 8 16 15 b 2X B e aaa C 2X 9 aaa C TOP VIEW BOTTOM VIEW DETAIL A ccc C (A3) 1 1 0.08 C SIDE VIEW bbb M C A B L A1 m m 0.5 66 1 e L1 3.2 3.2 0.35 L1 R 0.18 EXPOSED GROUND PADDLE R aaa bbb ccc REF: MIN 0.85 0 m Symbols m DATUM 43 0. DETAIL B A A1 A3 b D D2 E E2 e L L1 R K CORNER TIE BAR 5 32x b 32x K SEATING PLANE 1 e/2 TERMINAL TIP C A Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.2 REF 0.23 0.30 5.00 BSC 3.3 3.4 5.00 BSC 3.3 3.4 0.5 BSC 0.4 0.45 0.1 NOTE 1 2 2 1 b(min)/2 0.20 Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-2 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT . CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY . 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. w PD, Rev 4.6, July 2009 120 Production Data WM8985 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PD, Rev 4.6, July 2009 121