ARA2000 Address-Programmable Reverse Amplifier with Step Attenuator Data Sheet - Rev 2.3 features • Low cost integrated amplifier with step attenuator • Attenuation Range: 0-58 dB, adjustable in 1dB increments via a 3 wire serial control • Meets DOCSIS distortion requirements at a +60dBmV output signal level • Programmable address allows multiple parts to share control bus • Low distortion and low noise • Frequency range: 5-100MHz • 5 Volt operation • -40 to +85 oC temperature range Applications • MCNS/DOCSIS Compliant Cable Modems S12 Package 28 Pin SSOP with Heat Slug • CATV Interactive Set-Top Box • Telephony over Cable Systems • OpenCable Set-Top Box • Residential Gateway product description The ARA2000 is designed to provide the reverse path amplification and output level control functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. This device uses a balanced circuit design that exceeds the MCNS/DOCSIS requirement for harmonic performance at a +60dBmV output level while only requiring a single polarity +5V supply. Both the input and output are matched to 75 ohms with an appropriate transformer. The precision attenuator provides up to 58 dB of attenuation in 1 dB increments. The ARA2000 has a programmable address that allows multiple devices to share a common control bus. The ARA2000 is offered in a 28-pin SSOP package featuring a heat slug on the bottom of the package. Figure 1: Cable Modem or Set Top Box Application Diagram 04/2011 ARA2000 Figure 2: Functional Block Diagram Figure 3: Pin Out 2 Data Sheet - Rev 2.3 04/2011 ARA2000 Table 1: Pin Description pin nAMe 1 GND 2 descRiption pin nAMe descRiption Ground 15 C0 Device Address 0 VATTN Supply for Attenuator 16 C1 Device Address 1 3 ATTIN (+) Attenuator (+) Input (2) 17 N/C No Connection (1) 4 A1OUT (+) Amplifier A1 (+) Output 18 GND CMOS Ground for Digital CMOS Circuit 5 A1IN (+) Amplifier A1 (+) Input (2) 19 ATTOUT (-) Attenuator (-) Output (2) 6 Vg1 Amplifier A1 (+/-) Control 20 A2IN (-) Amplifier A2 (-) Input (2) 7 ISET1 Amplifier A1 (+/-) Current Adjust 21 A2OUT (-) Amplifier A2 (-) Output 8 A1IN (-) Amplifier A1 (-) Input (2) 22 ISET2 Amplifier A2 (+/-) Current Adjust 9 A1OUT (-) Amplifier A1 (-) Output 23 Vg2 Amplifier A2 (+/-) Control 10 ATTIN (-) Attenuator (-) Input (2) 24 A2OUT (+) Amplifier A2 (+) Output 11 VCMOS Supply For Digital CMOS Circuit 25 A2IN (+) Amplifier A2 (+) Input (2) 12 CLK Clock 26 ATTOUT (+) Attenuator (+) Output (2) 13 DAT Data 27 N/C No Connection (1) 14 EN Enable 28 GND Ground Notes: (1) All N/C pins should be grounded. (2) Pins should be AC-coupled. No external DC bias should be applied. Data Sheet - Rev 2.3 04/2011 3 ARA2000 electrical characteristics Table 2: Absolute Minimum and Maximum Ratings pARAMeteR Min MAX unit Analog Supply (pins 2, 4, 9, 21, 24) 0 9 VDC Digital Supply: VCMOS (pin 11) 0 6 VDC Amplifier Controls Vg1, Vg2 (pins 6, 23) -5 2 V RF Power at Inputs (pins 5, 8) - +60 dBmV Digital Interface (pins 12, 13, 14, 15, 16) -0.5 VCMOS+0.5 V Storage Temperature -55 +200 C Soldering Temperature - 260 C Soldering Time - 5 Sec Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Notes: 1. Pins 3, 5, 8, 10, 19, 20, 25 and 26 should be AC-coupled. No external DC bias should be applied. 2. Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC bias should be applied. Table 3: Operating Ranges pARAMeteR Min tYp MAX unit Amplifier Supply: VDD (pins 4, 9,21,24) 4.5 5.0 7.0 VDC VDD -0.5 5.0 7.0 VDC 3.0 - 5.5 VDC Digital Interface (pins 12, 13, 14, 15,16) 0 - VCMOS V Amplifier Controls Vg1, Vg2 (pins 6, 23) -5 1 2 V Case Temperature -40 25 85 C Attenuator Supply: VATTN (pin 2) Digital Supply: VCMOS (pin 11) The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. 4 Data Sheet - Rev 2.3 04/2011 ARA2000 Table 4: DC Electrical Specifications TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled) pARAMeteR Min tYp MAX unit coMMents Amplifier A1 Current (pins 4, 9) - 48 2.4 80 6 mA Tx enabled Tx disabled Amplifier A2 Current (pins 21, 24) - 77 3.7 120 9 mA Tx enabled Tx disabled Attenuator Current (pin 2) - 9 15 mA Total Power Consumption - 0.67 75 1.08 150 W mW Thermal Resistance (JC) - 38 - C/W Tx enabled Tx disabled Table 5: AC Electrical Specifications TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled) Min tYp MAX unit Gain (10 MHz) 27.5 29.3 30.5 dB 0 dB attenuation setting Gain Flatness - 0.75 1.5 - dB 5 to 42 MHz 5 to 65 MHz Gain Variation over Temperature - -0.006 - dB/8C 0.65 1.6 3.6 7.5 15.0 30.2 0.83 1.70 3.75 7.75 15.40 30.75 1.00 2.05 4.0 8.0 15.8 31.3 58.6 60.3 - dB 2nd Harmonic Distortion Level (10 MHz) - -75 -53 dBc +60 dBmV into 75 Ohms 3rd Harmonic Distortion Level (10 MHz) - -60 -53 dBc +60 dBmV into 75 Ohms 78 - - dBmV 1 dB Gain Compression Point - 68.5 - dBmV Noise Figure - 3.0 4.0 dB pARAMeteR Attenuation Steps 1 dB 2 dB 4 dB 8 dB 16 dB 32 dB Maximum Attenuation 3rd Order Output Intercept dB coMMents Monotonic Includes input balun loss Note: As measured in ANADIGICS test fixture Data Sheet - Rev 2.3 04/2011 5 ARA2000 continued: AC Electrical Specifications TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled) pARAMeteR Min tYp MAX unit coMMents Output Noise Power Active/ No Signal/ Min. Atten. Set Active/ No Signal/ Max. Atten. Set. - - -38.5 -53.8 dBmV Any 160 kHz bandwidth from 5 to 42 MHz Isolation (45 MHz) in Tx disable mode - 65 - dB Difference in output signal between Tx enable and Tx disable Differential Input Impedance - 300 - Ohms between pins 5 and 8 (Tx enabled) Input Impedance - 75 - Ohms with transformer (Tx enabled) Input Return Loss (75 Ohm characteristic impedance) - -20 -5 -12 - dB Differentail Output Impedance - 300 - Ohms between pins 21 and 24 Output Impedance - 75 - Ohms with transformer Output Return Loss (75 Ohm characteristic impedance) - -17 -15 -12 -10 dB Output Voltage Transient Tx enable/ Tx disable - 4 100 7 mVp-p Note: As measured in ANADIGICS test fixture 6 Data Sheet - Rev 2.3 04/2011 Tx enabled Tx disabled Tx enabled Tx disabled 0 dB attenuator setting 24 dB attenuator setting ARA2000 Figure 4: Test Circuit Data Sheet - Rev 2.3 04/2011 7 ARA2000 PERFORMANCE DATA Figure 5: Attenuation Level vs Control Word Figure 6: Gain & Noise Figure vs Frequency Figure 7: Gain & Noise Figure vs VDD 8 Data Sheet - Rev 2.3 04/2011 ARA2000 Figure 8: Gain & Noise Figure vs Temperature Figure 9: Harmonic Distortion vs VDD POUT = 58dBmV Figure 10: Harmonic Distortion vs VDD POUT = 58dBmV Data Sheet - Rev 2.3 04/2011 9 ARA2000 Figure 11: Harmonic Distortion vs Temperature POUT = 58dBmV Figure 12: Harmonic Distortion vs Power Out Figure 13: Transients vs Attenuation POUT = 55dBmV at 0dB attenuation 10 Data Sheet - Rev 2.3 04/2011 ARA2000 Figure 14: Harmonic Performance over Frequency POUT = +62dBmV Figure 15: IIP2 & IIP3 vs Frequency Figure 16: IIP2 & IIP3 vs VDD Data Sheet - Rev 2.3 04/2011 11 ARA2000 LOGIC PROGRAMMING Programming Instructions The programming word is set through a 16 bit shift register via the data, clock and enable lines. The data is entered in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The enable line must be low for the duration of the data entry, then set high to latch the shift register. The rising edge of the clock pulse shifts each data value into the register. Table 6: Programming Word dAtA Bit d15 d14 d13 d 12 d 11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Value P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 1 C1 C0 1 1 Table 7: Data Description 12 Table 8: Device Address VAlue function ( 1 = on, 0 = bypass) P7 N/A P6 N/A P5 loGic leVel input to AddRess deVice c1 c0 pin 16 (c1) pin 15 (c0) 0 0 0 0 1 0 1 0 32 dB Attenuator Bit 0 1 0 1 P4 16 dB Attenuator Bit 1 1 1 1 P3 8 dB Attenuator Bit P2 4 dB Attenuator Bit P1 2 dB Attenuator Bit P0 1 dB Attenuator Bit The device is selected when the logic inputs at pins 16 and 15 match the values of data bits C1 and C0, respectively. Data Sheet - Rev 2.3 04/2011 ARA2000 Table 9: Digital Interface Specification DATA pARAMeteR Min tYp MAX unit Logic High Input: VH 2.0 - - V Logic Low Input: VL - - 0.8 V Logic Input Current Consumption - - 0.01 mA Data to Clock Set Up Time: tCS 50 - - ns Data to Clock Hold Time: tCH 10 - - ns Clock Pulse Width High: tCWH 50 - - ns Clock Pulse Width Low: tCWL 50 - - ns Clock to Load Enable Setup Time: tES 50 - - ns Load Enable Pulse Width: tEW 50 - - ns Rise Time: tR - 10 - ns Fall Time: tF - 10 - ns D15: MSB D14 D8 D1 D7 D0: LSB CLOCK tCWL ENABLE OR ENABLE tCS tCH tCWH tES tEW Figure 17: Serial Data Input Timing Data Sheet - Rev 2.3 04/2011 13 ARA2000 application information Transmit Enable / Disable The ARA2000 includes two amplification stages that each can be shut down through external control pins Vg1 and Vg2 (pins 6 and 23, respectively.) By applying a slightly positive bias of typically +1.0 Volts, the amplifier is enabled. In order to disable the amplifier, the control pin needs to be pulled to ground. A practical way to implement the necessary control is to use bias resistor networks similar to those shown in the test circuit schematic (Figure 4.) Each network includes a resistor shunted to ground that serves as a pull-down to disable the amplifier when no control voltage is applied. When a positive voltage is applied, the network acts as a voltage divider that presents the required +1.0 Volts to enable the amplifier. By selecting different resistor values for the voltage divider, the network can accommodate different control voltage inputs. The Vg1 and Vg2 pins may be connected together directly, and controlled through a single resistor network from a common control voltage. Amplifier Bias Current The Iset pins (7 and 22) set the bias current for the amplification stages. Grounding these pins results in the maximum possible current. By placing a resistor from the pin to ground, the current can be reduced. The recommended bias conditions use the configuration shown in the test circuit schematic in Figure 4. Thermal Layout Considerations The device package for the ARA2000 features a heat slug on the bottom of the package body. Use of the heat slug is an integral part of the device design. Soldering this slug to the ground plane of the PC board will ensure the lowest possible thermal resistance for the device, and will result in the longest MTF (mean time to failure.) A PC board layout that optimizes the benefits of the heat slug is shown in Figure 18. The via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a sufficient heat sink. The recommended solder mask outline is shown in Figure 19. Figure 18: PC Board Layout 14 Data Sheet - Rev 2.3 04/2011 03/2011 ARA2000 Output Transformer Matching the output of the ARA2000 to a 75 Ohm load is accomplished using a 2:1 turns ratio transformer. In addition to providing an impedance transformation, this transformer provides the bias to the output amplifier stage via the center tap. The transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifiers. As a result, care must be taken when selecting the transformer to be used at the output. It must be capable of handling the RF and DC power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. It also must operate over the desired frequency and temperature range for the intended application. ESD Sensitivity Electrostatic discharges can cause permanent damage to this device. Electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. Proper precautions and handling are strongly recommended. Refer to the ANADIGICS application note on ESD precautions. Figure 19: Solder Mask Outline Data Sheet - Rev 2.3 04/2011 15 ARA2000 PACKAGE OUTLINE Figure 20: S12 Package Outline - 28 Pin SSOP with Heat Slug 16 Data Sheet - Rev 2.3 04/2011 ARA2000 COMPONENT PACKAGING Volume quantities of the ARA2000 are supplied on tape and reel. Each reel holds 3,500 pieces. Figure 21: Reel Dimensions Figure 22: Tape Dimensions Data Sheet - Rev 2.3 04/2011 17 ARA2000 Notes 18 Data Sheet - Rev 2.3 04/2011 ARA2000 Notes Data Sheet - Rev 2.3 04/2011 19 ARA2000 Notes 20 Data Sheet - Rev 2.3 04/2011 ARA2000 Ordering Information oRdeR nuMBeR teMpeRAtuRe RAnGe pAcKAGe descRiption ARA2000S12P1 -40 to 85 °C 28 Pin SSOP with Heat Slug coMponent pAcKAGinG 3,500 piece tape and reel ANADIGICS, Inc. 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: [email protected] IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. warning ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. 21 Data Sheet - Rev 2.3 04/2011