AVAGO ACPL-P480-500E

ACPL-P480 and ACPL-W480
High CMR Intelligent Power Module and Gate Drive Interface Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-P480 and ACPL-W480 fast speed optocouplers contain a GaAsP LED and photo detector with
built-in Schmitt trigger to provide logic-compatible
waveforms, eliminating the need for additional wave
shaping. The totem pole output eliminates the need for
a pull up resistor and allows for direct drive Intelligent
Power Module or gate drive. Minimized propagation
delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency
through reduced switching dead time.
• Performance Specified for Common IPM Applications
Over Industrial Temperature Range.
• Short Maximum Propagation Delays
• Minimized Pulse Width Distortion (PWD)
• Very High Common Mode Rejection (CMR)
•Hysteresis
• Totem Pole Output (No Pull-up Resistor Required)
• Available in Stretched SO-6 package.
• Safety Approval:
UL Recognized with 3750 Vrms for 1 minute (5000
Vrms for 1 minute for all ACPL-W480 devices and
Option 020 device for ACPL-P480) per UL1577.
CSA Approved.
IEC/EN/DIN EN 60747-5-5 Approved:
VIORM = 891 Vpeak for ACPL-P480, and VIORM = 1140
Vpeak for ACPL-W480.
Functional Diagrams
ACPL-P480
ANODE 1
6 VCC
N.C. 2
5 VO
CATHODE 3
SHIELD
4 Ground
Specifications
ACPL-W480
ANODE 1
6 VCC
N.C. 2
5 VO
CATHODE 3
SHIELD
4 Ground
Note: A 0.1 µF bypass capacitor must be connected between pins 4 and 6.
Truth Table (Positive Logic)
LED
VO
ON
HIGH
OFF
LOW
•
•
•
•
•
•
Wide operating temperature range: –40°C to 100°C.
Maximum propagation delay tPHL / tPLH = 350 ns
Maximum Pulse Width Distortion (PWD) = 250 ns.
Propagation Delay Difference: Min. –100 ns, Max. 250 ns
Wide Operating VCC Range: 4.5 to 20 Volts
20 kV/µs minimum common mode rejection (CMR) at
VCM = 1000 V.
Applications
•
•
•
•
•
IPM Interface Isolation
Isolated IGBT/MOSFET Gate Drive
AC and Brushless DC Motor Drives
Industrial Inverters
General Digital Isolation
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-P480 is UL Recognized with 3750 Vrms for 1 minute and ACPL-W480 is UL Recognized with 5000 Vrms for 1
minute per UL1577. Both are approved under CSA Component Accep­tance Notice #5, File CA 88324.
Option
Part number
RoHS
Compliant
Package
-000E
ACPL-P480
-520E
X
7mm
Stretched
SO-6
X
X
-560E
X
-500E
-060E
-560E
IEC/EN/DIN EN
60747-5-5
X
X
X
100 per reel
X
1000 per reel
X
100 per tube
X
1000 per reel
X
X
X
X
1000 per reel
X
X
X
8mm
Stretched
SO-6
Quantity
100 per tube
X
-060E
-000E
ACPL-W480
Tape & Reel
UL 1577
5000VRMS / 1
Minute Rating
X
-500E
-020E
Surface
Mount
X
100 per tube
X
1000 per reel
X
X
100 per tube
X
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P480-560E to order product of Stretched SO-6 package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-P480-000E to order product of Stretched SO-6 package in tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
ACPL-P480 Stretched SO-6 Package, 7 mm clearance
+0.254
0
+0.010
0.180
- 0.000
1.27 BSG
0.050
0.381 ±0.127
0.015 ±0.005
4.580
1.27
0.050
7.62
0.300
6.81
0.268
0.45
0.018
45°
10.7
0.421
1.590 ±0.127
0.063 ±0.005
0.76
0.030
2.16
0.085
3.180 ±0.127
0.125 ±0.005
7°
7°
7°
7°
0.20 ±0.10
0.008 ±0.004
0.254 ±0.050
0.010 ±0.002
5 NOM.
1±0.250
0.040 ±0.010
Floating Lead Protusions max. 0.25 [0.01]
Dimensions in Millimeters [ Inches ]
Lead Coplanarity= 0.1mm [0.004 Inches ]
9.7 ±0.250
0.382 ±0.010
ACPL-W480 Stretched SO-6 Package, 8 mm clearance
0.381 ±0.127
0.015 ±0.005
1
4
7.62
[0.300]
+0.127
6.807
- 0.000
+0.005
0.268
- 0.000
7°
45°
7°
35° NOM.
11.500 ±0.25
0.453 ±0.010
1.905
0.075
1.270
0.050
1.590 ±0.127
0.063 ±0.005
0.20 ±0.10
0.008 ±0.004
3
0.760
0.030
5
3
0.750 ±0.250
[0.0295 ±0.010]
12.650
0.498
6
2
0.45
0.018
+0.254
0
+0.010
0.180
- 0.000
4.580
1.27 BSG
0.050
0.254 ±0.050
0.010 ±0.002
3.180 ±0.127
0.125 ±0.005
7°
7°
Floating Lead protusion max. 0.25[0.01]
Dimensions in millimeters [inches]
Lead Coplanarity=0.1 mm [0.004 inches]
Solder Reflow Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-P480 and ACPL-W480 are approved by the following organizations:
IEC/EN/DIN EN 60747-5-5 (Option 60 only)
UL
Approval under:
IEC 60747-5-5 : 2007
EN 60747-5-5 : 2011
DIN EN 60747-5-5 (VDE 0884-5) : 2011-11
ACPL-P480: Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
ACPL-W480 and ACPL-P480 (option 020): Approval under
UL 1577, component recognition program up to VISO =
5000 VRMS. File E55361.
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060)
Characteristic
Description
Symbol
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
ACPL-P480
ACPL-W480
I - IV
I - III
I - III
I - IV
I - IV
I - IV
Climatic Classification
55/100/21
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
Unit
2
VIORM
891
1140
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge < 5 pC
VPR
1670
2137
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test with tm = 10 sec,
Partial discharge < 5 pC
VPR
1426
1824
Vpeak
VIOTM
6000
8000
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
Safety-limiting values - maximum values allowed in the event of a failure.
Case Temperature
Input Current
Output Power
Insulation Pesistance at TS, VIO = 500 V
TS
IS,INPUT
PS,OUTPUT
175
230
600
°C
mA
mW
RS
>109
W
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
4
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-P480
ACPL-W480
Units
Conditions
Minimum External Air Gap
(External Clearance)
L(101)
7.0
8.0
mm
Measured from input terminals to output
terminals shortest distance through air.
Minimum External Tracking
(External Creepage)
L(102)
8.0
8.0
mm
Measured from input terminals to output
terminals shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
mm
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Minimum Internal Tracking
(Internal Creepage)
NA
mm
Measured from input terminals to output
tereminals, along internal cavity.
>175
V
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
IIIa
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
100
°C
Average Input Current
IF(avg)
10
mA
Peak Transient Input Current
(<1 µs pulse width, 300 pps)
(<200 µs pulse width, < 1% duty cycle)
IF(tran)
1.0
40
A
mA
Reverse Input Voltage
VR
5
V
Average Output Current
IO
25
mA
Supply Voltage
VCC
0
25
Output Voltage
VO
-0.5
25
Total Package Power Dissipation
PT
Note
210
mW
1
Note
Table 4. Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage
VCC
4.5
20
V
Forward Input Current (ON)
IF(ON)
6
10
mA
Forward Input Voltage (OFF)
VF(OFF)
-
0.8
V
Operating Temperature
TA
-40
100
°C
Notes:
1. Derate total package power dissipation, PT, linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.
5
Table 5. Electrical Specifications
Over recommended operating conditions TA = -40 °C to 100 °C, VCC = +4.5 V to 20 V, IF(ON) = 6 mA to 10 mA, VF(OFF) = 0
V to 0.8 V, unless otherwise specified. All typicals at TA = 25 °C.
Parameter
Symbol
Logic Low Output Voltage
VOL
Logic High Output Voltage
ACPL-P480
ACPL-W480
VOH
Threshold Input Current
Low to High
IFLH
Output Leakage Current
(VO = VCC+0.5V)
IOHH
Logic Low Supply Current
ICCL
Logic High Supply Current
ICCH
Min.
2.4
2.7
2.7
Typ.
Units
Test Conditions
Fig.
0.5
V
IOL = 6.4 mA
1, 3, 9,
10
V
IOH = -2.6 mA
IOH = -0.4 mA
IOH = -1.6 mA
2, 3, 7,
9, 10
VCC - 1.1
2.2
5.5
mA
100
µA
VCC = 5 V, IF = 10mA
500
µA
VCC = 20 V, IF = 10mA
1.9
3.0
mA
VCC = 5.5 V, VF = 0 V, IO = Open
2.0
3.0
mA
VCC = 20 V, VF = 0 V, IO = Open
1.5
2.5
mA
VCC = 5.5 V, IF = 10 mA,
IO = Open
1.6
2.5
mA
VCC = 20 V, IF = 10 mA
IO = Open
25
mA
VO = VCC = 5.5 V, VF=0V
50
mA
VO = VCC = 20 V, VF=0V
-25
mA
VCC = 5.5 V, IF=6mA, VO=GND
-50
mA
VCC = 20 V, IF=6mA, VO=GND
1.7
V
TA = 25˚C, IF=6mA
1.85
V
IF=6mA
V
IR = 10 µA
Logic Low Short Circuit
Output Current
IOSL
Logic High Short Circuit
Output Current
IOSH
Input Forward Voltage
VF
Input Reverse
Breakdown Voltage
BVR
Input Diode Temperature
Coefficient
DVF/DTA
1.7
mV/°C
IF = 6 mA
Input Capacitance
CIN
60
pF
f = 1 MHz, VF = 0 V
1.5
5
Notes:
1. Duration of output short circuit time should not exceed 10 ms.
2. Input capacitance is measured between pin 1 and pin 3.
6
Max.
Note
1
1
4
2
Table 6. Switching Specifications
Over recommended operating conditions TA = -40 °C to 100 °C, VCC = +4.5 V to 20 V, IF(ON) = 6 mA to 10 mA, VF(OFF) = 0
V to 0.8 V, unless otherwise specified. All typicals at TA = 25 °C.
Parameter
Symbol
Propagation Delay Time to
Logic Low Output Level
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
tPHL
150
350
ns
With Peaking
Capacitor
5, 6
1
Propagation Delay Time to
Logic High Output Level
tPLH
110
350
ns
With Peaking
Capacitor
5, 6
1
Pulse Width Distortion
|tPHL - tPLH|
= PWD
250
ns
2
Propagation Delay Difference
Between Any 2 Parts
PDD
250
ns
3
Output Rise Time (10-90%)
tr
16
ns
5, 8
Output Fall Time (90-10%)
tf
20
ns
5, 8
Logic High Common Mode
Transient Immunity
|CMH|
20
kV/µs
|VCM| = 1000 V, IF = 6.0 11
mA, VCC = 5 V, TA = 25˚C
4
Logic Low Common Mode
Transient Immunity
|CML|
20
kV/µs
|VCM| = 1000 V, VF = 0 V,
VCC = 5 V, TA = 25˚C
11
4
Parameter
Symbol
Min.
Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage*
VISO
3750**
Vrms
RH < 50%, t = 1 min.
TA = 25°C
5, 6
Input-Output Resistance
RI-O
1012
VI-O = 500 Vdc
5
Input-Output Capacitance
CI-O
0.6
f = 1 MHz, VI-O = 0 Vdc
5
-100
Table 7. Package Characteristics
Typ.
5000***
Max.
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable).
** For all ACPL-P480 devices except Option 020
*** For ACPL-W480 and Option 020 of ACPL-P480)
Notes:
1. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing
edge of the output pulse.
2. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH | for any given device.
3. The difference between tPLH and tPHL between any two devices under the same test condition.
4.CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, VO > 2.0 V.
CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, VO < 0.8 V.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for one second (leakage
detection current limit, II-O ≤ 5 µA). ; each optocoupler with option 020 is proof tested by applying an insulation test voltage ≥ 6000 VRMS for
1 second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b)
shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
7. Use of a 0.1 μF bypass capacitor connected between pins 4 and 6 is recommended.
7
0
VCC = 4.5/20V
VF = 0V
IO = 6.4mA
0.14
0.13
IOH - HIGH LEVEL OUTPUT CURRENT - mA
VOL - LOW LEVEL OUTPUT VOLTAGE - V
0.15
VCC = 4.5V
VCC = 20V
0.12
0.11
0.1
-50
0
50
TA - TEMPERATURE - °C
100
VO = 2.4V
-20
-50
0
50
TA - TEMPERATURE - °C
100
150
Figure 2. Typical Logic High Output Current vs. Temperature
IO = -2.6mA
3.5
IF - FORWARD CURRENT - mA
Vo - OUTPUT VOLTAGE - V
VO = 2.7V
-15
1000
4
3
2.5
2
1.5
TA = 25C
1
VCC = 4.5V
0.5
0
1
2
3
IF - INPUT CURRENT - mA
TA = 25 °C
IF
100
VF
10
+
-
1.0
0.1
0.01
IO = 6.4mA
4
0.001
1.1
5
Figure 3. Typical Output Voltage vs. Forward Input Current
1.3
1.4
VF - FORWARD VOLTAGE - V
1.2
1.5
Figure 4. Typical Input Diode Forward Characteristic
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C1 AND C 2 .
PULSE GEN.
tr = tf = 5 ns
f = 100 kHz
10% DUTY
CYCLE
VO = 5 V
ZO = 50
VCC
1
6
2
INPUT
MONITORING
NODE
3
R1
C1 =
120 pF
5V
OUTPUT VO
MONITORING
NODE
*
R1
580 W
330 W
IF(ON)
6 mA
10 mA
ALL DIODES ARE 1N916 OR 1N3064.
D1
619 W
5
I F (ON)
50 % I F (ON)
0 mA
INPUT I F
D2
SHIELD
* 0.1 µF BYPASS - SEE NOTE 7
Figure 5. Circuit for tPLH, tPHL, tr, tf
8
-10
-25
4.5
0
-5
150
Figure 1. Typical Logic Low Output Voltage vs. Temperature
VCC = 4.5V
IF = 6mA
4
C2 =
15 pF
5 kkW
D3
D4
t PLH
OUTPUT VO
t PHL
V OH
1.3 V
V OL
25
210
190
tPHL
170
VCC = 20V
IF = 10mA
150
130
Vo - OUTPUT VOLTAGE - V
Tp - PROPAGATION DELAY - ns
230
tPLH
110
90
20
TA = 25oC
IO = -2.6mA
15
10
5
70
50
-60
-40
-20
0
20
40
60
TA - TEMPERATURE - C
80
100
Figure 6. Typical Propagation Delays vs. Temperature.
TP - PROPAGTION DELAY - ns
5
10
15
VCC - SUPPLY VOLTAGE - V
20
25
IF (mA)
10
6
180
tPHL
140
0
Figure 7. Typical Logic High Output Voltage vs. Supply Voltage
200
160
0
120
120
100
80
IF (mA)
6
10
tPLH
60
40
TA = 25oC
20
0
0
5
10
15
VCC - SUPPLY VOLTAGE - V
20
25
Figure 8. Typical Propagation Delay vs. Supply Voltage
0.16
Vcc=4.5V
IF=6mA
4.0
100 °C
3.5
25 °C
-40 °C
3.0
2.5
2.0
25 °C
0.12
-40 °C
0.10
0.08
0.06
0.04
0.02
-6
-5
-4
-3
-2
Ioh - HIGH OUTPUT CURRENT - mA
Figure 9. Voh vs Ioh Across Temperatures
9
100 °C
0.14
Vol - LOW OUTPUT VOLTAGE - V
Voh - HIGH OUTPUT VOLTAGE -V
4.5
-1
0
0
0.5
1.5
2.5
3.5
4.5
Iol - LOW OUTPUT CURRENT - mA
Figure 10. Vol vs Iol Across Temperatures
5.5
6.5
R IN
VCC
A
1
VFF
+
-
6
0.1 µF
B
2
5
3
SHIELD
+
|V CM |
4
OUTPUT V O
MONITORING
NODE
VCM
-
V CM (PEAK)
0V
VOH
OUTPUT VO
VOL
SWITCH AT A: I F = 6 mA
VO (MIN.)
SWITCH AT B: V F = 0 V
V O (MAX.)
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms
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Data subject to change. Copyright © 2005-2012 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0646EN
AV02-1305EN - December 21, 2012