X4C105 4K NOVRAM/EEPROM CPU Supervisor with NOVRAM and Output Ports FEATURES DESCRIPTION • 4Kbit serial EEPROM —400kHz serial interface speed —16-byte page write mode • One nibble NOVRAM —120ns NOVRAM access speed —AUTOSTORE —Direct/bus access of NOVRAM bits • Four output ports • Operates at 3.3V ± 10% • Low voltage reset when VCC < 3V —3% accurate thresholds available —Output signal shows low voltage condition —Activates NOVRAM AUTOSTORE —Internal block on EEPROM operation • Max EEPROM/NOVRAM nonvolatile write cycle: 5ms • High reliability —1,000,000 endurance cycles —Guaranteed data retention: 100 years • 20-lead TSSOP package The low voltage X4C105 combines several functions into one device. The first is a 2-wire, 4Kbit serial EEPROM memory with write protection. A Write Protect (WP) pin provides hardware protection for the upper half of this memory against inadvertent writes. A one nibble NOVRAM is provided and occupies a single location. This allows access of 4-bits in a single 150ns cycle. This is useful for tracking system operation or process status. The NOVRAM memory is completely isolated from the serial memory section. A low voltage detect circuit activates a RESET pin when VCC drops below 3V. This signal also blocks new read or write operations and initiates a NOVRAM AUTOSTORE. The AUTOSTORE operation is powered by an external capacitor to ensure that the value in the NOVRAM is always maintained in the event of a power failure. The four NOVRAM bits also appear on four separate output pins to allow continuous control of external circuitry, such as ASICs. Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. BLOCK DIAGRAM Write Control Logic WP SCL SDA S1 S2 Command Decode and Control Logic X Decoder HV Generation Timing and Control EEPROM Array EEPROM Memory Static RAM Memory 4Kbits Low Voltage Detect Power On Reset www.xicor.com O0 O1 O2 O3 I/O Buffers D0 D1 D2 D3 Control Logic and Timing Y Decoder Data Register REV 1.0.1 6/14/01 Output Buffers and Latches Voltage Monitor Supply CE OE WE CAP VCC VSS RESET Characteristics subject to change without notice. 1 of 19 X4C105 PACKAGE/PINOUTS A WP pin provides hardware write protection. The WP pin active (HIGH) prevents writes to the top half of the memory. 20-Lead TSSOP CAP 1 20 VCC S1 2 19 WP S2 3 18 SCL CE 4 17 SDA WE 5 16 D0 OE 6 15 D1 RESET 7 14 D2 O3 8 13 D3 O2 9 12 O0 VSS 10 11 O1 This section is a 4K-bit version of an industry standard 24C04 device. NOVRAM Section The X4C105 also contains a single nibble of NOVRAM, with parallel access. This memory is completely isolated from the serial memory section. The NOVRAM is intended to connect to the system memory bus and uses standard CE, OE, and WE pins to control access. A NOVRAM (or nonvolatile RAM) consists of an SRAM part and an EEPROM part. The SRAM is saved to EEPROM only when power fails and the EEPROM is recalled to SRAM only on power up. Output Ports The X4C105 has four output only ports. These are active whenever power is applied to the device. The state of the output pin reflects the value in the respective SRAM bit. As such, these port pins provide a nonvolatile state. The conditions on the pins are restored when power is re-applied to the device. This can be valuable as a DIP switch replacement for controlling the conditions of an ASIC or other system logic. Pin Names Pin Description VSS Ground SDA Serial Data VCC Power SCL Serial Clock WP Write Protect S1, S2 Device Select Inputs D0–D3 NOVRAM I/Os Low Voltage Detection When the internal low voltage detect circuitry senses that VCC is low, several things happen: RESET Low Voltage Detect Output – The RESET pin goes active. CE NOVRAM Chip Enable OE NOVRAM Read Signal – The contents of the SRAM are automatically saved to the “shadow” EEPROM. WE NOVRAM Write signal CAP O0-O3 External AUTOSTORE Capacitor NOVRAM Outputs DEVICE DESCRIPTION Serial Memory Section The device contains a 4Kbit EEPROM memory array with an internal address counter that allows it to be read sequentially, through its entire address space after receiving only 1 full address. The serial interface includes a current address read that requires no input address, but allows reading of the entire array starting from the address plus one of the last read or write. The address counter is also used for the write operation where the user may enter up to a page of data (16 bytes) after supplying only 1 full address. REV 1.0.1 6/14/01 – Internal circuitry switches to provide power for the AUTOSTORE operation from the CAP pin so the store operation can complete even in the event of a catastrophic power failure. To insure this, it is recommended that a 47µF capacitor be used on the CAP pin. The capacitor is continuously charged during normal operation to provide the necessary charge to complete the store operation. Other internal circuits are turned off to minimize current consumption during the store operations. — Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the operation is completed and is followed by a NOVRAM AUTOSTORE cycle. www.xicor.com Characteristics subject to change without notice. 2 of 19 X4C105 Capacitor Backup Circuit The diagram in Figure1 shows a representation of the capacitor backup circuit. Figure 1. To Internal Voltage Supply VCC VTRIP HIGH when VCC > VTRIP LOW when VCC<VTRIP-0.2V Start NOVRAM AUTOSTORE CAP SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 2. Figure 2. Valid Data Changes on the SDA Bus SCL SDA Data Stable REV 1.0.1 6/14/01 Data Change www.xicor.com Data Stable Characteristics subject to change without notice. 3 of 19 X4C105 Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 3. Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 2. Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. The device will respond with an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect or when the device is busy, such as during a nonvolatile write. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to standby mode and place the device into a known state. Figure 3. Valid Start and Stop Conditions SCL SDA Start Stop Figure 4. Acknowledge Response From Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver Start REV 1.0.1 6/14/01 Acknowledge www.xicor.com Characteristics subject to change without notice. 4 of 19 X4C105 Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same page. This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 5 bytes are written to locations 10 through 15, and the last 7 bytes are written to locations 0 through 6. Afterwards, the address counter would point to location 7 of the page that was just written. See Figure 6. If the master supplies more than 16 bytes of data, then new data over-writes the previous data, one byte at a time. SERIAL WRITE OPERATIONS Byte Write For a write operation, the device requires the slave address byte and a word address byte. This gives the master access to any one of the words in the array. After receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 5. An attempted write to a protected block of memory will suppress the acknowledge bit and the operation will terminate. Figure 5. Byte Write Sequence Signals from the Master S t a r t Byte Address Slave Address SDA Bus S t o p Data 0 A C K Signals from the Slave A C K A C K Figure 6. Writing 12 bytes to a 16-byte page starting at location 10. 7 Bytes Address =6 REV 1.0.1 6/14/01 5 Bytes Address Pointer Ends Here Addr = 7 Address 10 www.xicor.com Address n-1 Characteristics subject to change without notice. 5 of 19 X4C105 The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 7 for the address, acknowledge, and data transfer sequence. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be affected. Figure 7. Page Write Operation (1 < n < 16) Signals from the Master S t a r t Byte Address Slave Address Data (1) S t o p Data (n) SDA Bus 0 Signals from the Slave REV 1.0.1 6/14/01 A C K A C K www.xicor.com A C K A C K Characteristics subject to change without notice. 6 of 19 X4C105 Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the device initiates the internal non volatile write cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the slave address byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 8. Figure 8. Acknowledge Polling Sequence Issue START Issue Slave Address Byte (Read or Write) It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Issue STOP NO ACK returned? YES YES Continue Normal Read or Write Command Sequence PROCEED REV 1.0.1 6/14/01 Current Address Read Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the slave address byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to Figure 9 for the address, acknowledge, and data transfer sequence. Byte load completed by issuing STOP. Enter ACK Polling High Voltage Cycle complete. Continue command sequence? Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address byte is set to one. There are three basic read operations: current address read, random read, and sequential read. NO Issue STOP Random Read A random read operation allows the master to access any memory location in the array. Prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address byte. After acknowledging receipts of the word address byte, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 10 for the address, acknowledge, and data transfer sequence. www.xicor.com Characteristics subject to change without notice. 7 of 19 X4C105 Figure 9. Current Address Read Sequence Signals from the Master S t a r t S t o p Slave Address SDA Bus 1 A C K Signals from the Slave Data Figure 10. Random Address Read Sequence Signals from the Master SDA Bus Signals from the Slave S t a r t S t o p Slave Address 1 0 A C K A C K The device offers a similar operation, called “Set Current Address,” where the device ends the transmission and issues a stop instead of the second start, shown in Figure 10. The device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next current address read operation will then read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments REV 1.0.1 6/14/01 S t a r t Byte Address Slave Address A C K Data through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter “rolls over” to address 0000H and the device continues to output data for each acknowledge received. Refer to Figure 11 for the acknowledge and data transfer sequence. SERIAL DEVICE ADDRESSING Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several parts: – a device type identifier that is always ‘1010’. – two bits that provide the device select bits. – one bit that becomes the MSB of the address. – one bit of the slave command byte is a R/W bit. The R/W bit of the slave address byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 12. www.xicor.com Characteristics subject to change without notice. 8 of 19 X4C105 Figure 11. Sequential Read Sequence Signals from the Master Slave Address SDA Bus A C K A C K S t o p A C K 1 A C K Signals from the Slave Data (n-1) Data (2) Data (1) Data (n) (n is any integer greater than 1) After loading the entire slave address byte from the SDA bus, the device compares the device select bits with the status of the device select pins. Upon a correct compare, the device outputs an acknowledge on the SDA line. 0 Table 1. Write Protected Areas WP Pin Slave Byte 1 Write Protect Operations The WP pin provides write protection. The WP pin protects the upper half of the array. 1 0 S2 S1 A8 R/W LOW Writes possible to all locations HIGH No writes to 100H-1FFH, writes possible to 000H to 0FFH Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power up condition. REV 1.0.1 6/14/01 Serial Memory Write Protection www.xicor.com Characteristics subject to change without notice. 9 of 19 X4C105 ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to ground .................................-1.0V to 7.0V DC output current................................................ 5 mA Lead temperature (soldering, 10 seconds).........300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC OPERATING CHARACTERISTICS VCC = 3.0 to 3.6V at -40°C to +85°C unless otherwise specified. Symbol (1) Parameter Min. Max. Unit Test Conditions ICC1 Active supply current serial read or serial write (does not include the nonvolatile store operation) 2.0 mA VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz, SDA = Read/Write Operation, CE, OE, WE, D0–D3 = VIH; O0–O3, RESET = Open CAP is tied to VCC; VCC > VTRIP ICC2(1) Average active supply current during serial nonvolatile store operation 3.0 mA VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 = VIL, CE, OE, WE, D0–D3 = VIH; O0–O3, RESET = Open CAP is tied to VCC. Test during the N.V. write cycle. ICC3(1) Active supply current volatile NOVRAM read 3.0 mA VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 = VIL, WE = VIH; CE, OE = VIL, D0–D3, O0–O3, RESET = Open CAP is tied to VCC; VCC > VTRIP ICC4(1) Active supply current volatile NOVRAM write 3.0 mA VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 =VIL, OE = VIH; CE, WE = VIL, D0-D3 = VIL or VIH, O0-O3, RESET = Open CAP is tied to VCC; VCC > VTRIP ICC5(1) Average active supply current over NOVRAM store, or active current during recall 3.0 mA VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA, VIH; WP, S1, S2 = VIL, WE, CE, OE = VIH; D0–D3, O0–O3, RESET = Open CAP is tied to VCC, VCC < VTRIP for Store; VCC > VTRIP for Recall ISB1(1) Standby current 50 µA VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA, CE, WE, OE, D0–D3, = VIH, WP = VIL, O0–O3, RESET = Open; CAP is tied to VCC ILI Input leakage current 10 µA VIN = GND to VCC ILO Output leakage current 10 µA VSDA = GND to VCC; Device is in Standby(2) VCC x 0.3 V VIL(3) (3 Input LOW voltage -0.5 VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V VHYS Schmitt trigger input hysteresis .05 x VCC V VOL Output LOW voltage VOH Output HIGH voltage 0.4 VCC – 0.4 V IOL = 2.0mA, VCC = 3.3V V IOH = -1mA, VCC = 3.3V Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t WC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. (3) VIL min. and VIH max. are for reference only and are not tested. REV 1.0.1 6/14/01 www.xicor.com Characteristics subject to change without notice. 10 of 19 X4C105 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 3.0-3.6V Symbol CI/O(4) (4) CIN Note: Parameter Max. Unit Test Conditions Input/output capacitance (SDA, D0-D3, O0-O3) 8 pF VI/O = 0V Input capacitance (SCL, WP, CE, WE, OE, S1, S2) 6 pF VIN = 0V (4) This parameter is periodically sampled and not 100% tested. SERIAL NONVOLATILE WRITE CYCLE TIMING Symbol (5) tWC Note: Parameter Min. Typ.(5) Max. Unit 3 5 ms Write cycle time (5) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. SERIAL MEMORY AC CHARACTERISTICS Equivalent AC Output Load Circuit for VCC = 3.0–3.6V Serial AC Test Conditions 3.3V Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load 1533Ω For VOL = 0.4V and IOL = 2mA SDA 100pF REV 1.0.1 6/14/01 www.xicor.com Characteristics subject to change without notice. 11 of 19 X4C105 SERIAL AC SPECIFICATIONS TA = -40°C to +85°C, VCC = +3.0V to +3.6V, unless otherwise specified. 400kHz Option Symbol Parameter Min. Max. Unit SCL clock frequency 0 400 kHz tIN Pulse width of spikes to be suppressed by the input filter 0 50 ns tAA SCL LOW to SDA data out valid 0.1 0.9 µs tBUF Time the bus must be free before a new transmission can start 1.3 µs tLOW Clock LOW time 1.3 µs tHIGH Clock HIGH time 0.6 µs tSU:STA Start condition setup time 0.6 µs tHD:STA Start condition hold time 0.6 µs tSU:DAT Data in setup time 100 ns tHD:DAT Data in hold time 0 µs tSU:STO Stop condition setup time 0.6 µs Data output hold time 50 ns fSCL tDH +.1Cb(8) 300 ns 300 ns tR SDA and SCL rise time 20 tF SDA and SCL fall time 20 +.1Cb(8) tSU: S1, S2,WP S1, S2, and WP setup time 0.4 ms tHD: S1, S2,WP S1, S2, and WP hold time 0.4 ms Cb Capacitive load for each bus line 400 pF Notes: (7) This parameter is periodically sampled and not 100% tested. (8) Cb = total capacitance of one bus line in pF. SERIAL TIMING DIAGRAMS Bus Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA SDA IN tHD:STA tHD:DAT tSU:STO tAA tDH tBUF SDA OUT REV 1.0.1 6/14/01 www.xicor.com Characteristics subject to change without notice. 12 of 19 X4C105 S1, S2, and WP Pin Timing START SCL Clk 1 Clk 9 Slave Address Byte SDA IN tHD: S1,S2,WP tSU: S1,S2,WP S1, S2, and WP Write Cycle Timing SCL SDA 8th Bit of Last Byte ACK tWC Stop Condition NOVRAM AC CHARACTERISTICS Start Condition NOVRAM Equivalent A.C Load Circuits 3.3V NOVRAM AC Conditions of Test Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 1596Ω 3093Ω REV 1.0.1 6/14/01 www.xicor.com 30pF Characteristics subject to change without notice. 13 of 19 X4C105 NOVRAM READ CYCLE SPECIFICATIONS Table 2. NOVRAM Read Cycle Limits VCC = 3.0V-3.6V -40°C to +85°C Symbol Parameter Min. Max. Unit tRC Read cycle time 120 ns tCE Chip enable access time 50 ns tOE Output enable access time 50 ns tOH Output hold from CE or OE HIGH 0 ns tWES Write enable HIGH setups time 25 ns tWEH Write enable HIGH hold time 25 ns tLZ Chip enable to output in low Z 0 ns tOLZ(9) Output enable to output in low Z 0 ns (9) (9) Chip disable to output in high Z 0 50 ns (9) Output disable to output in high Z 0 50 ns (9) OE setup prior to operation in 2-wire mode 100 ms (9) OE hold following operation in 2-wire mode 100 ms tHZ tOHZ tSOE tHOE Note: (9) tLZ and tOLZ min.; tSOE and tHOE min; and tHZ and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. NOVRAM Read Cycle tRC tCE CE tOE OE tWES tWEH WE tOHZ tOLZ tLZ tOH tHZ D0-D3 REV 1.0.1 6/14/01 www.xicor.com Characteristics subject to change without notice. 14 of 19 X4C105 NOVRAM WRITE CYCLE SPECIFICATIONS NOVRAM Write Cycle Limits VCC = 3.0V-3.6V, TA = -40°C to +85°C Symbol Parameter Min. Max. Unit tWC Write cycle time 120 ns tWC1 Write cycle time 170 ns tOES Output enable HIGH setup time 50 ns tOEH Output enable HIGH hold time 50 ns tCW Chip enable to end of write input 50 ns tCE Write setup time 0 ns tCH Write hold time 0 ns tWP Write pulse width 50 ns tWP1 Write pulse width 100 ns tWPH Write pulse HIGH recovery time 50 ns tDS Data setup to end of write 40 ns tDH Data hold time 0 ns tNDO New data output OE setup prior to operation in 2-wire mode 100 (10) OE hold following operation in 2-wire mode 100 tSOE tHOE tWZ Write enable to output in HIGH-Z tOW ns ms ms 50 ns Output active from end of write 0 (10) Chip disable to output in high Z 0 50 ns (10) Output disable to output in high Z 0 50 ns tCHZ tOHZ Note: 50 (10) ns (10)tLZ and tOLZ min.; tSOE and tHOE min; and tHZ and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. REV 1.0.1 6/14/01 www.xicor.com Characteristics subject to change without notice. 15 of 19 X4C105 NOVRAM WE Controlled Write Cycle OE tOES tCH tCW CE tCE tOEH tWP WE tWPH tWC tDS D0-D3 (Data I/O) tDH Data Valid tNDO O0-O3 (Data Out) New Valid Data Previous Valid Data NOVRAM CE Controlled Write Cycle OE tOES tCW tOEH CE tCE tCH tWP tWPH WE tWC tDS D0-D3 (Data In) tDH Data Valid tNDO O0-O3 (Data Out) REV 1.0.1 6/14/01 Previous Valid Data www.xicor.com New Valid Data Characteristics subject to change without notice. 16 of 19 X4C105 LOW VOLTAGE DETECT/POWER CYCLE PARAMETERS Symbols Parameters VTRIP Reset trip voltage—blank tRPD VCC detect to reset active Min. Typ. Max. Unit 2.80 2.875 2.95 V 500 ns 400 ms Power up reset time out delay (tPURST Option 1)—default 100 tF VCC fall time from VCC = 3V to VCC = 2.5V 100 µs tR VCC rise time from VCC = 2.5V to VCC = 3V 100 µs tOVT Output pins valid after VCC exceeds VTRIP tPURST 200 Reset valid VCC VRVALID 200 1 ns V Low Voltage Detect and Output Pin Recall VTRIP VCC tPURST tRPD tPURST tF tR VRVALID RST O0-O3 REV 1.0.1 6/14/01 tOVT tOVT Data Valid Data Valid www.xicor.com VCC(min) Characteristics subject to change without notice. 17 of 19 X4C105 PACKAGING INFORMATION 20-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.0.1 6/14/01 www.xicor.com Characteristics subject to change without notice. 18 of 19 X4C105 Ordering Information X4C105 X X Device –X VCC Limits Blank = 3.3V ±10%, VTRIP = 2.8–2.95V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package V20 = 20 Lead TSSOP Part Mark Convention 20-Lead TSSOP X4C105 YYWW XXX Blank = 3.3V ±10%, 0 to +70°C, VTRIP = 2.8–2.95V I = 3.3 ±10%, -40 to +85°C, VTRIP = 2.8–2.95V LIMITED WARRANTY ©Xicor, Inc. 2000 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.0.1 6/14/01 www.xicor.com Characteristics subject to change without notice. 19 of 19