ETC ACE1101EN

August 2001
ACE1101 Product Family
Arithmetic Controller Engine (ACEx™)
for Low Power Applications
■ On-chip oscillator
— No external components
— 1µs instruction cycle time
General Description
The ACE1101 (Arithmetic Controller Engine) family of
microcontrollers is a dedicated programmable monolithic integrated circuit for applications requiring high performance, low
power, and small size. It is a fully static part fabricated using
CMOS technology.
■ On-chip Power-on Reset
■ Brown-out Reset
■ Programmable read and write disable functions
■ Memory mapped I/O
The ACE1101 product family has an 8-bit microcontroller core, 64
bytes of RAM, 64 bytes of data EEPROM and 1K bytes of code
EEPROM. Its on-chip peripherals include a multi-function 16-bit
timer, watchdog/idle timer, and programmable under-voltage
detection circuitry. On-chip clock and reset functions reduce the
number of required external components. The ACE1101 product
family is available in 8-pin TSSOP, 8-pin DIP and 14-pin DIP
packages.
■ Multi-level Low Voltage Detection
■ Fully static CMOS
— Low power HALT mode (100nA @ 3.3V)
— Power saving IDLE mode
■ Single supply operation
— 1.8-5.5V (ACE1101L)
— 2.2-5.5V (ACE1101)
— 2.7-5.5V (ACE1101B)
Features
■ 1K bytes on-board code EEPROM
■ Software selectable I/O options
— Push-pull outputs with tri-state option
— Weak pull-up or high impedance inputs
■ 64 bytes data EEPROM
■ 40 years data retention
■ 64 bytes RAM
■ 1,000,000 writes
■ Watchdog
■ Multi-input wake-up on all I/O pins
■ 8-pin TSSOP, 8 and 14-pin DIP packages. (SOIC and CSP
packages available upon request)
■ 16-bit multifunction timer
■ In-circuit programming
■ Arithmetic Controller Engine
Block and Connection Diagram
1
VCC
1
GND
2
RESET
G0 (CKO)
G1 (CKI)
G2 (T1)
G3(Input only)
G4
G5
2
G6
2
G7
G port
general
purpose
I/O
with
multiinput
wakeup
Power-on
Reset
Internal
Oscillator
Low Battery/Brown-out
Detect
Watchdog/
12-Bit Timer 0
16-Bit Timer 1
ACE1101
Control
Unit
HALT/IDLE
Power saving
Modes
Programming
Interface
RAM block
64 bytes
1K bytes of CODE
EEPROM
64 bytes of DATA
EEPROM
1. 100nf Decoupling capacitor recommended
2. Available only in the 14-pin package option.
© 2001 Fairchild Semiconductor Corporation
ACE1101 Product Family Rev. B.2
1
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
PRELIMINARY
VCC
Optional
LED
G4
VCC
G3
G0
G1
RF Interface
G5
GND
RF Stage
G2
Figure 3: ACE1101 TSSOP/DIP 8-pin Device
a) Normal Mode Operation
b) Programming Mode Operation
G3
1
8
VCC
LOAD
1
8
VCC
G4
2
7
GND
SFT_IN
2
7
GND
G5
G0
3
6
NC/VCC
NC
6
5
G2
G1
3
4
4
5
SFT_OUT
CKI
Figure 4: ACE1101 DIP 14-pin Device
a) Normal Mode Operation
b) Programming Mode Operation
G3
1
14
VCC
LOAD
1
14
VCC
G4
2
13
GND
13
3
12
3
12
GND
RESET
4
11
RESET
G2
SFT_IN
NC
2
NC
G6
NC
4
11
SFT_OUT
G7
G5
5
10
10
9
NC
NC/VCC
5
6
NC
NC
6
9
NC
NC
G0
7
8
G1
NC
7
8
CKI
2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 2: ACE1101 Application Example (Remote Keyless Entry)
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Relative Humidity (non-condensing)
Input Voltage not including G3
-0.3V to VCC+0.3V
G3 Input Voltage
EEPROM write limits
0.3V to 13V
Lead Temperature (10s max)
Electrostatic Discharge on all pins
Device
See DC Electrical
Characteristics
+300°C
2000V min
Operating Voltage Ambient Operating Temperature
ACE1101
2.2 to 5.5V
0°C to 70°C
ACE1101E
2.2 to 5.5V
-40°C to +85°C
ACE1101V
2.2 to 5.5V
-40°C to +125°C
ACE1101B
2.7 to 5.5V
0°C to 70°C
ACE1101BE
2.7 to 5.5V
-40°C to +85°C
ACE1101BV
2.7 to 5.5V
-40°C to +125°C
ACE1101L
1.8 to 5.5V
0°C to 70°C
3
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
2.0 Electrical Characteristics
Absolute Maximum Ratings
VCC = 2.2/2.7/1.8 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
ICC
3
Parameter
Conditions
MIN
TYP
MAX
Units
0.2
0.4
0.7
1.2
3.7
0.5
1.0
1.2
2.0
5.5
mA
mA
mA
mA
mA
Supply Current –
no data EEPROM write in
progress
1.8V
2.2V
2.7V
3.3V
5.5V
ICCH
HALT Mode current
3.3V @ -40°C to +25°C
5.5V @ -40°C to +25°C
3.3V @ +85°C
5.5V @ +85°C
3.3V @ +125°C
5.5V @+125°C
10
60
75
400
600
1550
100
1000
1000
2500
5000
8000
nA
nA
nA
nA
nA
nA
ICCL4
IDLE Mode Current
3.3V
5.5V
150
200
200
300
µA
µA
VCCW
EEPROM Write Voltage
Code EEPROM in
Programming Mode
4.5
5.0
5.5
V
Data EEPROM in
Operating Mode
2.4
5.5
V
1µs/V
10ms/V
SVCC
Power Supply Slope
VIL
Input Low with Schmitt
Trigger Buffer
VCC = 1.8 -5.5V
VIH
Input High with Schmitt
Trigger Buffer
VCC = 1.8 - 5.5V
IIP
Input Pull-up Current
VCC =5.5V, VIN =0V
ITL
TRI-STATE Leakage
VCC =5.5V
VOL
Output Low Voltage
VCC = 1.8 - 2.2V
G0, G1, G2, G4, G6, G7
VOH
0.2VCC
0.8VCC
V
V
65
350
µA
2
200
nA
0.8 mA sink
0.2VCC
V
G5
1.0 mA sink
0.2VCC
V
Output Low Voltage
VCC = 2.2V – 3.3V
G0, G1, G2, G4, G6, G7
3.0 mA sink
0.2VCC
V
G5
5.0 mA sink
0.2VCC
V
Output Low Voltage
VCC = 3.3V – 5.5V
G0, G1, G2, G4, G6, G7
5.0 mA sink
0.2VCC
V
G5
10.0 mA sink
0.2VCC
V
Output High Voltage
VCC = 1.8 - 2.2V
G0, G1, G2, G4, G6, G7
0.1 mA source
0.8VCC
V
G5
0.2 mA source
0.8VCC
V
Output High Voltage
VCC = 3.3V – 5.5V
G0, G1, G2, G4, G6, G7
0.4 mA source
0.8VCC
V
G5
0.8 mA source
0.8VCC
V
Output High Voltage
VCC = 3.3V – 5.5V
G0, G1, G2, G4, G6, G7
0.4 mA source
0.8VCC
V
G5
1.0 mA source
0.8VCC
V
3
ICC active current is dependent on the program code.
4
Based on a continuous IDLE looping program.
4
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1101/1101B/1101L DC Electrical Characteristics
All measurements valid for ambient operating temperature range unless otherwise stated.
Parameter
Conditions
MIN
TYP
MAX
Units
0.9
1.0
1.1
µs
Instruction cycle time from
internal clock - setpoint
5.0V at +25°C
Internal clock voltage dependent
frequency variation
3.0V to 5.5V,
constant temperature
+5
%
Internal clock temperature
dependent frequency variation
3.0V to 5.5V,
full temperature range
+10
%
Internal clock frequency
deviation for 0.5V drop
3.0V to 4.5V,
constant temperature
+2
%
Crystal oscillator frequency
(Note 5)
4
MHz
External clock frequency
(Note 6)
4
MHz
EEPROM write time
10
ms
Internal clock start up time
(Note 6)
3
2
ms
Oscillator start up time
(Note 6)
2400
cycles
5
The maximum permissible frequency is guaranteed by design but not 100% tested.
6
The parameter is guaranteed by design but not 100% tested.
Preliminary ACE1101/1101B/1101L Electrical Characteristics for programming
All data following is valid between 4.5V and 5.5V at ambient temperature. The following characteristics are guaranteed by design but are not 100% tested. See "EEPROM write time" in the AC
Electrical Characteristics for definition of the programming ready time.
Parameter
Description
MIN
MAX
Units
tHI
CLOCK high time
500
DC
ns
tLO
CLOCK low time
500
DC
ns
tDIS
SHIFT_IN setup time
100
ns
tDIH
SHIFT_IN hold time
100
ns
tDOS
SHIFT_OUT setup time
100
ns
tDOH
SHIFT_OUT hold time
900
ns
tSV1, tSV2
LOAD supervoltage timing
50
µs
tLOAD1, tLOAD2, tLOAD3, tLOAD4
LOAD timing
5
µs
VSUPERVOLTAGE
Supervoltage level
11.5
5
ACE1101 Product Family Rev. B.2
12.5
V
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1101/1101B/1101L AC Electrical Characteristics
VCC = 2.2/2.7/1.8 to 5.5V
VCC = 2.2/1.8 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
LBD Voltage Threshold
Conditions
MIN
TYP
MAX
Units
Level 1 @ -40°C
2.84
V
Level 8 @ -40°C
2.02
V
Level 1 @ 0°C
2.98
V
Level 8 @ 0°C
2.05
V
Level 1 @ +25°C
3.08
V
Level 8 @ +25°C
2.12
V
Level 1 @ +85°C
3.31
V
Level 8 @ +85°C
2.27
V
Level 1 @ +125°C
3.36
V
Level 8 @ +125°C
2.40
V
Preliminary ACE1101 Brown-out Reset (BOR) Characteristics
VCC = 2.2 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
BOR Trigger Threshold
Conditions
MIN
TYP
MAX
Units
-40°C
1.98
V
0°C
2.06
V
+25°C
2.12
V
+85°C
2.27
V
+125°C
2.37
V
Preliminary ACE1101L Brown-out Reset (BOR) Characteristics
VCC = 1.8 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
BOR Trigger Threshold
Conditions
MIN
MAX
Units
0°C
1.78
V
+25°C
1.82
V
+70°C
1.96
V
6
ACE1101 Product Family Rev. B.2
TYP
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1101/1101L Low Battery Detect (LBD) Characteristics
Frequency (MHz)
Figure 5: RC Oscillator Frequency vs. Temperature (VCC=5.0V)
2.600
2.400
2.200
2.000
1.800
1.600
1.400
1.200
1.000
Avg
Min
Max
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Figure 6: RC Oscillator Frequency vs. Temperature (VCC=2.5V)
Frequency (MHz)
1.600
1.400
Avg
Min
Max
1.200
1.000
0.800
0.600
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Frequency (MHz)
Figure 7: Internal Oscillator Frequency
Temperature [°C]
7
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
3.0 AC & DC Electrical Characteristic Graphs
ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 8: Power Supply Rise Time
VCC
VBATT
1V
tS min
tS actual
Name
tS max
Parameter
time
Unit
VCC
Supply Voltage
[V]
VBATT
Battery Voltage (Nominal Operating Voltage)
[V]
tS min
Minimum Time for VCC to Rise by 1V
[ms]
tS actual
Actual Time for VCC to Rise by 1V
[ms]
tS max
Maximum Time for VCC to Rise by 1V
[ms]
SVCC
Power Supply Slope
[ms/V]
8
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 9: ICC Active
Icc Active (mA)
ICC Active (no data EEPROM writes) vs. Temperature
Temperature [°C]
Icc Active (mA)
ICC Active (data EEPROM writes) vs. Temperature
Temperature [°C]
9
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 10: HALT Mode Currents
Icc HALT (nA)
HALT current vs. Temperature
Temperature [°C]
10
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 11: IDLE Mode Currents
Icc IDLE (µA)
IDLE current vs. Temperature
Temperature [°C]
11
ACE1101 Product Family Rev. B.2
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segment of the memory map. This modification improves the
overall code efficiency of the ACEx microcontroller and takes
advantage of the flexibility found on Von Neumann style machines.
The ACEx microcontroller core is specifically designed for low
cost applications involving bit manipulation, shifting block encryption. It is based on a modified Harvard architecture meaning
peripheral, I/O, and RAM locations are addressed separately from
instruction data.
4.1 CPU Registers
The ACEx microcontroller has five general-purpose registers.
These registers are the Accumulator (A), X-Pointer (X), Program
Counter (PC), Stack Pointer (SP), and Status Register (SR). The
X, SP, and SR registers are all memory-mapped.
The core differs from the traditional Harvard architecture by
aligning the data and instruction memory sequentially. This allows
the X-pointer (11-bits) to point to any memory location in either
Figure 12: Programming Model
7
A
0
8-bit accumulator register
X
10
0
11-bit X pointer register
PC
9
0
10-bit program counter
0
4-bit stack pointer
SP
SR
3
8-bit status register
R 0 0GZCHN
NEGATIVE flag
HALF CARRY flag (from bit 3)
CARRY flag (from MSB)
ZERO flag
GLOBAL Interrupt Mask
READY flag (from EEPROM)
12
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.0 Arithmetic Controller Core
instruction, the address of the instruction is automatically pushed
onto the stack least significant byte first. When the subroutine is
finished, a return from subroutine (RET) instruction is executed.
The RET instruction pulls the previously stacked return address
from the stack and loads it into the program counter. Execution
then continues at the recovered return address.
The Accumulator is a general-purpose 8-bit register that is used
to hold data and results of arithmetic calculations or data manipulations.
4.1.2 X-Pointer (X)
4.1.5 Status Register (SR)
The X-Pointer register allows for an 11-bit indexing value to be
added to an 8-bit offset creating an effective address used for
reading and writing between the entire memory space. (Software
can only read from code EEPROM.) This provides software with the
flexibility of storing lookup tables in the code EEPROM memory
space for the core’s accessibility during normal operation.
This 8-bit register contains four condition code indicators (C, H, Z,
and N), one interrupt masking bit (G), and an EEPROM write flag
(R). In the ACEx microcontroller, condition codes are automatically updated by most instructions. (See Table 10)
Carry/Borrow (C)
The ACEx core allows software to access the entire 11-bit XPointer register using the special X-pointer instructions (e.g. LD X,
#000H). (See Table 9) However, software may also access the
register through any of the memory-mapped instructions using the
XHI (X[10:8]) and XLO (X[7:0]) variables located at 0xBE and
0xBF, respectively. (See Table 11)
The carry flag is set if the arithmetic logic unit (ALU) performs a carry
or borrow during an arithmetic operation and by its dedicated
instructions. The rotate instruction operates with and through the
carry bit to facilitate multiple-word shift operations. The LDC and
INVC instructions facilitate direct bit manipulation using the carry flag.
The X register is divided into two sections. The 10 least significant
bits (LSB) of the register is the address of the program or data
memory space. The most significant bit (MSB) of the register is
write only and selects between the data (0x000 to 0x0FF) or
program (0xC00 to 0xFFF) memory space.
Half Carry (H)
Example: If Bit 10 = 0, then the LD A, [00,X] instruction will take a
value from address range 0x000 to 0x0FF and load it into A. If Bit
10 = 1, then the LD A, [00,X] instruction will take a value from
address range 0xC00 to 0xFFF and load it into A.
Zero (Z)
The half carry flag indicates whether an overflow has taken place on the
boundary between the two nibbles in the accumulator. It is primarily
used for Binary Coded Decimal (BCD) arithmetic calculation.
The zero flag is set if the result of an arithmetic, logic, or data
manipulation operation is zero. Otherwise, it is cleared.
Negative (N)
The X register can also serve as a counter or temporary storage
register. However, this is true only for the 10-LSBs since the 11th
bit is dedicated for memory space selection.
The negative flag is set if the MSB of the result from an arithmetic,
logic, or data manipulation operation is set to one. Otherwise, the
flag is cleared. A result is said to be negative if its MSB is a one.
4.1.3 Program Counter (PC)
Interrupt Mask (G)
The 10-bit program counter register contains the address of the
next instruction to be executed. After a reset, if in normal mode the
program counter is initialized to 0xC00.
The interrupt request mask (G) is a global mask that disables all
maskable interrupt sources. If the G Bit is cleared, interrupts can
become pending, but the operation of the core continues uninterrupted. However, if the G Bit is set an interrupt is recognized. After any
reset, the G bit is cleared by default and can only be set by a software
instruction. When an interrupt is recognized, the G bit is cleared after
the PC is stacked and the interrupt vector is fetched. Once the interrupt
is serviced, a return from interrupt instruction is normally executed to
restore the PC to the value that was present before the interrupt
occurred. The G bit is reset to one after a return from interrupt is
executed. Although the G bit can be set within an interrupt service
routine, “nesting” interrupts in this way should only be done when there
is a clear understanding of latency and of the arbitration mechanism.
4.1.4 Stack Pointer (SP)
The ACEx microcontroller has an automatic program stack with a 4bit stack pointer. The stack can be initialized to any location between
addresses 0x30-0x3F. Normally, the stack pointer is initialized by one
of the first instructions in an application program. After a reset, the
stack pointer is defaulted to 0xF pointing to address 0x3F.
The stack is configured as a data structure which decrements from
high to low memory. Each time a new address is pushed onto the
stack, the core decrements the stack pointer by two. Each time an
address is pulled from the stack, the core increments the stack
pointer is by two. At any given time, the stack pointer points to the
next free location in the stack.
4.2 Interrupt handling
When an interrupt is recognized, the current instruction completes its execution. The return address (the current value in the
program counter) is pushed onto the stack and execution contin-
When a subroutine is called by a jump to subroutine (JSR)
Table 8: Interrupt Priority Sequence
Priority (4 highest, 1 lowest)
4
MIW
(EDGEI)
3
Timer0
(TMRI0)
2
Timer1
(TMRI1)
1
Software
(INTR)
13
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.1.1 Accumulator (A)
mode can be used to address either data or program memory space.
Indirect
The instruction allows the X-pointer to address any location within
the data memory space.
Direct
The ACEx microcontroller is capable of supporting four interrupts.
Three are maskable through the G bit of the SR and the fourth
(software interrupt) is not inhibited by the G bit (see Figure 13). The
software interrupt instruction is generated by the execution of the
INTR instruction. once the INTR instruction is executed, the ACEx
core will interrupt whether the G bit is set or not. The INTR interrupt
is executed in the same manner as the other maskable interrupts
where the program counter register is stacked and the G bit is
cleared. This means, if the G bit was enabled prior to the software
interrupt the RETI instruction must be used to return from interrupt
in order to restore the G bit to its previous state. However, if the G
bit was not enabled prior to the software interrupt the RET
instruction must be used.
The instruction contains an 8-bit address field that directly points
to the data memory space as an operand.
Immediate
The instruction contains an 8-bit immediate field as an operand.
Inherent
This instruction has no operands associated with it.
Absolute
In case of multiple interrupts occurring at the same time, the ACEx
microcontroller core has prioritized the interrupts. The interrupt
priority sequence in shown in Table 8.
The instruction contains a 10-bit address that directly points to a
location in the program memory space. There are two operands
associated with this addressing mode. Each operand contains a
byte of an address. This mode is used only for the long jump (JMP)
and JSR instructions.
4.3 Addressing Modes
Relative
The ACEx microcontroller has seven addressing modes indexed,
indirect, direct, immediate, absolute jump, and relative jump.
This mode is used for the short jump (JP) instructions where the
operand is a value relative to the current PC address. With this
instruction, software is limited to the number of bytes it can jump,
-31 or +32.
Indexed
The instruction allows an 8-bit unsigned offset value to be added to
the 10-LSBs of the X-pointer yielding a new effective address. This
Interrupt Source with Priority
Figure 13: Basic Interrupt Structure
INTR
T1
T1PND
T0
T0PND
MIW
WKPND
Interrupt
Pending
Flags
Interrupt
T1EN
T0INT
EN
WKINT
EN
G
Global Interrupt
Enable
Interrupt Enable Bits
14
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
ues at the address specified by the unique interrupt vector (see
Table 11). This process takes five instruction cycles. At the end
of the interrupt service routine, a return from interrupt (RETI)
instruction is executed. The RETI instruction causes the saved
address to be pulled off the stack in reverse order. The G bit is
set and instruction execution resumes at the return address.
Instruction
Immediate
Direct
Indexed
Indirect
ADC
A, #
A, M
A, [X]
ADD
A, #
A, M
A, [X]
AND
A, #
A, M
A, [X]
OR
A, #
A, M
A, [X]
SUBC
A, #
A, M
A, [X]
XOR
A, #
A, M
A, [X]
CLR
M
A
X
INC
M
A
X
DEC
M
A
X
IFEQ
A, #
X, #
IFGT
A, #
X, #
IFNE
A, #
IFLT
M,#
A, M
A, [X]
A, M
A, [X]
A, M
A, [X]
Inherent
no-op
RC
no-op
IFC
no-op
IFNC
no-op
INVC
no-op
LDC
#, M
STC
#, M
RLC
M
A
RRC
M
A
A, M
A, [00,X]
A, [X]
ST
A, M
A, [00,X]
A, [X]
LD
M, M
A, #
X, #
M, #
NOP
IFBIT
Absolute
X, #
SC
LD
Relative
no-op
#, A
#, M
SBIT
#, M
#, [X]
RBIT
#, M
#, [X]
JP
Rel
JSR
M
JMP
M
RET
no-op
RETI
no-op
INTR
no-op
15
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Table 9: Instruction Addressing Modes
Mnemonic Operand Bytes Cycles
Flags
affected
Mnemonic Operand Bytes Cycles
ADC
A, [X]
1
1
C,H,Z,N
JMP
ADC
A, M
2
2
C,H,Z,N
JP
ADC
A, #
2
2
C,H,Z,N
JSR
ADD
A, [X]
1
1
Z,N
ADD
A, M
2
2
Z,N
ADD
A, #
2
2
Z,N
AND
A, [X]
1
1
AND
A, #
2
AND
A, M
CLR
CLR
3
4
None
1
1
None
M
3
5
None
LD
A, #
2
2
None
LD
A, [00,X]
2
3
None
LD
A, [X]
1
1
None
Z,N
LD
A, M
2
2
None
2
Z,N
LD
M, #
3
3
None
2
2
Z,N
LD
X, #
3
3
None
X
1
1
Z
LDC
#, M
2
2
C
A
1
1
Z,N,C,H
LD
M, M
3
3
None
CLR
M
2
1
Z,N,C,H
NOP
1
1
None
DEC
A
1
1
Z,N
OR
A, #
2
2
Z,N
DEC
M
2
2
Z,N
OR
A, [X]
1
1
Z,N
DEC
X
1
1
Z
OR
A, M
2
2
Z,N
IFBIT
#, A
1
1
None
RBIT
#, [X]
1
2
Z,N
IFBIT
#, M
2
2
None
RBIT
#, M
2
2
Z,N
1
1
None
IFC
M
Flags
affected
RC
1
1
C,H
IFEQ
A, [X]
1
1
None
RET
1
5
None
IFEQ
A, #
2
2
None
RETI
1
5
None
IFEQ
A, M
2
2
None
RLC
A
1
1
C,Z,N
IFEQ
M, #
3
3
None
RLC
M
2
2
C,Z,N
IFEQ
X, #
3
3
None
RRC
A
1
1
C,Z,N
IFGT
A, #
2
2
None
RRC
M
2
2
C,Z,N
IFGT
A, [X]
1
1
None
SBIT
#, [X]
1
2
Z,N
IFGT
A, M
2
2
None
SBIT
#, M
2
2
Z,N
IFGT
X, #
3
3
None
SC
1
1
C,H
IFNE
A, #
2
2
None
ST
A, [00,X]
2
3
None
IFNE
A, [X]
1
1
None
ST
A, [X]
1
1
None
IFNE
A, M
2
2
None
ST
A, M
2
2
None
IFLT
X, #
3
3
None
STC
#, M
2
2
Z,N
1
1
None
IFNC
SUBC
A, #
2
2
C,H,Z,N
INC
A
1
1
Z,N
SUBC
A, [X]
1
1
C,H,Z,N
INC
M
2
2
Z,N
SUBC
A, M
2
2
C,H,Z,N
INC
X
1
1
Z
XOR
A, #
2
2
Z,N
INTR
1
5
None
XOR
A, [X]
1
1
Z,N
INVC
1
1
C
XOR
A, M
2
2
Z,N
16
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Table 10: Instruction Cycles and Bytes
All I/O ports, peripheral registers and core registers, except the accumulator and the program counter are mapped into memory space.
Table 11: Memory Map
Address
Memory Space
Block
Contents
0x00 - 0x3F
Data
SRAM
Data RAM
0x40 - 0x7F
Data
EEPROM
0xAA
Data
Timer1
Data EEPROM
T1RALO register
0xAB
Data
Timer1
T1RAHI register
0xAC
Data
Timer1
TMR1LO register
0xAD
Data
Timer1
TMR1HI register
0xAE
Data
Timer1
T1CNTRL register
0xAF
Data
MIW
WKEDG register
0xB0
Data
MIW
WKPND register
0xB1
Data
MIW
WKEN register
0xB2
Data
I/O
PORTGD register
0xB3
Data
I/O
PORTGC register
0xB4
Data
I/O
PORTGP register
0xB5
Data
Timer0
WDSVR register
0xB6
Data
Timer0
T0CNTRL register
0xB7
Data
Clock
0xB8 - 0xBC
HALT mode register
Reserved
0xBD
Data
LBD
LBD register
0xBE
Data
Core
XHI register
0xBF
Data
Core
XLO register
0xC0
Data
Core
Power mode clear (PMC) register
0xCE
Data
Core
SP register
0xCF
Data
Core
Status register (SR)
0xC00 - 0xFF5
Program
EEPROM
0xFF6 - 0xFF7
Program
Core
Timer0 Interrupt vector
0xFF8 - 0xFF9
Program
Core
Timer1 Interrupt vector
0xFFA - 0xFFB
Program
Core
MIW Interrupt vector
0xFFC - 0xFFD
Program
Core
Software Interrupt vector
0xFFE - 0xFFF
Reserved
17
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.4 Memory Map
4.6 Initialization Registers
The ACEx microcontroller device has 64 bytes of SRAM and 64
bytes of EEPROM available for data storage. The device also has
1K bytes of EEPROM for program storage. Software can read and
write to SRAM and data EEPROM but can only read from the code
EEPROM. While in normal mode, the code EEPROM is protected
from any writes. The code EEPROM can only be rewritten when
the device is in program mode and if the write disable (WDIS) bit
of the initialization register is not set to 1.
The ACEx microcontroller has two 8-bit wide initialization registers. These registers are read from the memory space on powerup to initialize certain on-chip peripherals. Figure 14 provides a
detailed description of Initialization Register 1. The Initialization
Register 2 is used to trim the internal oscillator to its appropriate
frequency. This register is pre-programmed in the factory to yield
an internal instruction clock of 1MHz.
Both Initialization Registers 1 and 2 can be read from and written
to during programming mode. However, re-trimming the internal
oscillator (writing to the Initialization Register 2) once it has left the
factory is discouraged.
While in normal mode, the user can write to the data EEPROM
array by 1) polling the ready (R) flag of the SR, then 2) executing
the appropriate instruction. If the R flag is 1, the data EEPROM
block is ready to perform the next write. If the R flag is 0, the data
EEPROM is busy. The data EEPROM array will reset the R flag
after the completion of a write cycle. Attempts to read, write, or
enter HALT/IDLE mode while the data EEPROM is busy (R = 0)
can affect the current data being written.
Figure 14: Initialization Register 1
Bit 7
CMODE[0]
Bit 6
CMODE[1]
Bit 5
WDEN
Bit 4
Bit 3
BOREN
BLSEL
Bit 2
9
UBD
7,8
Bit 1
WDIS
Bit 0
7,8
RDIS 7,8
(0) RDIS 7,8
If set, disables attempts to read the contents from the memory while in programming mode
(1) WDIS 7,8
If set, disables attempts to write new contents to the memory while in programming mode
(2) UBD 7,8
If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F)
(3) BLSEL 9
If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for the ACE1101
If not set, the BOR voltage reference level is set to its lower range for the ACE1101L
(4) BOREN
If set, allows a BOR to occur if VCC falls below the voltage reference level
(5) WDEN
If set, enables the on-chip processor watchdog circuit
(6) CMODE[1]
Clock mode select bit 1 (See Table 17)
(7) CMODE[0]
Clock mode select bit 0 (See Table 17)
7 If
both the WDIS and RDIS bits are set, the device will no longer be able to be placed into program mode.
8
If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits can be reset.
9
The BLSEL bit is set to its appropriate level in the factory. If writing to the initialization register is necessary, be sure to maintain BLSEL set value.
18
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.5 Memory
The timer can be started or stopped through the T1CNTRL
register bit T1C0. When running, the timer counts down (decrements) every clock cycle. Depending on the operating mode, the
timer’s clock is either the instruction clock or a transition on the T1
input. In addition, occurrences of timer underflow (transitions from
0x0000 to 0xFFFF/T1RA value) can either generate an interrupt
and/or toggle the T1 output pin.
Timer 1 is a versatile 16-bit timer that can operate in one of three
modes:
• Pulse Width Modulation (PWM) mode, which generates
pulses of a specified width and duty cycle
• External Event Counter mode, which counts occurrences
of an external event
Timer 1’s interrupt (TMRI1) can be enabled by interrupt enable
(T1EN) bit in the T1CNTRL register. When the timer interrupt is
enabled, depending on the operating mode, the source of the
interrupt is a timer underflow and/or a timer capture.
• Standard Input Capture mode, which measures the
elapsed time between occurrences of external events
Timer 1 contains a 16-bit timer/counter register (TMR1), a 16-bit
auto-reload/capture register (T1RA), and an 8-bit control register
(T1CNTRL). All register are memory-mapped for simple access
through the core with both the 16-bit registers organized as a pair
of 8-bit register bytes {TMR1HI, TMR1LO} and {T1RAHI, T1RALO}.
Depending on the operating mode, the timer contains an external
input or output (T1) that is multiplexed with the I/O pin G2. By
default, the TMR1 is reset to 0xFFFF, T1RA is reset to 0x0000,
and T1CNTRL is reset to 0x00.
5.1 Timer control bits
Reading and writing to the T1CNTRL register controls the timer’s
operation. By writing to the control bits, the user can enable or
disable the timer interrupts, set the mode of operation, and start or
stop the timer. The T1CNTRL register bits are described in Tables
12 and 13.
Table 12: TIMER1 Control Register Definition (T1CNTRL)
T1CNTRL Register
Name
Function
Bit 7
T1C3
Timer TIMER1 control bit 3 (see Table 13)
Bit 6
T1C2
Timer TIMER1 control bit 2 (see Table 13)
Bit 5
T1C1
Timer TIMER1 control bit 1 (see Table 13)
Bit 4
T1C0
Timer TIMER1 run: 1 = Start timer, 0 = Stop timer;
or Timer TIMER1 underflow interrupt pending flag
in input capture mode
Bit 3
T1PND
Timer1 interrupt pending flag: 1 = Timer1 interrupt
pending, 0 = Timer1 interrupt not pending
Bit 2
T1EN
Bit 1
-----------
Reserved
Bit 0
-----------
Reserved
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Table 13: TIMER1 Operating Mode Selection
T1
C3
T1
C2
T1
C1
Timer Mode
Interrupt A
Source
0
0
0
MODE 2
TIMER1 Underflow
T1 Pos. Edge
0
0
1
MODE 2
TIMER1 Underflow
T1 Neg. Edge
1
0
1
MODE 1 T1 Toggle
Autoreload T1RA
Instruction Clock
1
0
0
MODE 1 No T1 Toggle
Autoreload T1RA
Instruction Clock
0
1
0
MODE 3 Captures: T1 Pos. edge
Pos. T1 Edge
Instruction Clock
0
1
1
MODE 3 Captures: T1 Neg. Edge
Neg. T1 Edge
Instruction Clock
19
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.0 Timer 1
1. Configure T1 as an output by setting bit 2 of PORTGC.
- SBIT 2, PORTGC
; Configure G2 as an output
In the PWM mode, the timer counts down at the instruction clock
rate. When an underflow occurs, the timer register is reloaded from
T1RA and the count down proceeds from the loaded value. At every
underflow, a pending flag (T1PND) located in the T1CNTRL register is set. Software must then clear the T1PND flag and load the
T1RA register with an alternate PWM value. In addition, the timer
can be configured to toggle the T1 output bit upon underflow.
Configuring the timer to toggle T1 results in the generation of a
signal outputted from port G2 with the width and duty cycle
controlled by the values stored in the T1RA. A block diagram of the
timer’s PWM mode of operation is shown in Figure 15.
2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of
PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Load the initial PWM high (low) time into the timer register.
- LD TMR1LO, #6FH
; High (Low) for 1.391ms
(1MHz clock)
- LD TMR1HI, #05H
4. Load the PWM low (high) time into the T1RA register.
- LD T1RALO, #2FH
; Low (High) for .303ms
(1MHz clock)
- LD T1RAHI, #01H
The timer has one interrupt (TMRI1) that is maskable through the
T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit of
the SR is set. If interrupts are enabled, the timer will generate an
interrupt each time T1PND flags is set (whenever the timer
underflows provided that the pending flag was cleared.) The
interrupt service routine is responsible for proper handling of the
T1PND flag and the T1EN bit.
5. Write the appropriate control value to the T1CNTRL
register to select PWM mode with T1 toggle, to clear the
enable bit and pending flag, and to start the timer. (See
Table 12 and Table 13)
- LD T1CNTRL, #0B0H
; Setting the T1C0 bit starts
the timer
6. After every underflow, load T1RA with alternate values. If
the user wishes to generate an interrupt on a T1 output
transition, reset the pending flags and then enable the
interrupt using T1EN. The G bit must also be set. The
interrupt service routine must reset the pending flag and
perform whatever processing is desired.
- RBIT T1PND, T1CNTRL
; T1PND equals 3
- LD T1RALO, #6FH
; High (Low) for 1.391ms
(1MHz clock)
- LD T1RAHI, #05H
The interrupt will be synchronous with every rising and falling edge
of the T1 output signal. Generating interrupts only on rising or falling
edges of T1 is achievable through appropriate handling of the T1EN
bit or T1PND flag through software.
The following steps show how to properly configure Timer 1 to
operate in the PWM mode. For this example, the T1 output signal
is toggled with every timer underflow and the “high” and “low” times
for the T1 output can be set to different values. The T1 output signal
can start out either high or low depending on the configuration of
G2; the instructions below are for starting with the T1 output high.
Follow the instructions in parentheses to start the T1 output low.
Figure 15: Pulse Width Modulation Mode Block Diagram
16-bit Auto-Reload
Register (T1RA)
Underflow
Interrupt
T1
Data
Bus
Data
Latch
16-bit Timer (TMR1)
Instruction
Clock
20
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.2 Mode 1: Pulse Width Modulation (PWM) Mode
the instructions in parentheses to clock the counter every rising
edge.
The External Event Counter mode operates similarly to the PWM
mode; however, the timer is not clocked by the instruction clock
but by transitions of the T1 input signal. The edge is selectable
through the T1C1 bit of the T1CNTRL register. A block diagram of
the timer’s External Event Counter mode of operation is shown in
Figure 16.
1. Configure T1 as an input by clearing bit 2 of PORTGC.
- RBIT 2, PORTGC
; Configure G2 as an input
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Enable the global interrupt enable bit.
- SBIT 4, STATUS
The T1 input should be connected to an external device that
generates a positive/negative-going pulse for each event. By
clocking the timer through T1, the number of positive/negative
transitions can be counted therefore allowing software to capture
the number of events that occur. The input signal on T1 must have
a pulse width equal to or greater than one instruction clock cycle.
4. Load the initial count into the TMR1 and T1RA registers.
When the number of external events is detected, the counter
will reach zero; however, it will not underflow until the next
event is detected. To count N pulses, load the value N-1 into
the registers. If it is only necessary to count the number of
occurrences and no action needs to be taken at a particular
count, load the value 0xFFFF into the registers.
- LD TMR1LO, #0FFH
- LD TMR1HI, #00H
- LD T1RALO, #0FFH
- LD T1RAHI, #00H
The counter can be configured to sense either positive-going or
negative-going transitions on the T1 pin. The maximum frequency
at which transitions can be sensed is one-half the frequency of the
instruction clock.
As with the PWM mode, when the counter underflows the counter
is reloaded from the T1RA register and the count down
proceedsfrom the loaded value. At every underflow, a pending
flag (T1PND) located in the T1CNTRL register is set. Software
must then clear the T1PND flag and can then load the T1RA
register with an alternate value.
5. Write the appropriate control value to the T1CNTRL register
to select External Event Counter mode, to clock every falling
edge, to set the enable bit, to clear the pending flag, and to
start the counter. (See Table 12 and Table 13)
- LD T1CNTRL, #34H (#00h) ; Setting the T1C0 bit
starts the timer
The counter has one interrupt (TMRI1) that is maskable through
the T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit
of the SR is set. If interrupts are enabled, the counter will generate
an interrupt each time the T1PND flag is set (whenever timer
underflows provided that the pending flag was cleared.) The
interrupt service routine is responsible for proper handling of the
T1PND flag and the T1EN bit.
6. When the counter underflows, the interrupt service routine
must clear the T1PND flag and take whatever action is
required once the number of events occurs. If the software
wishes to merely count the number of events and the
anticipated number may exceed 65,536, the interrupt service
routine should record the number of underflows by
incrementing a counter in memory. Software can then
calculate the correct event count.
- RBIT T1PND, T1CNTRL
; T1PND equals 3
The following steps show how to properly configure Timer 1 to
operate in the External Event Counter mode. For this example, the
counter is clocked every falling edge of the T1 input signal. Follow
Figure 16: External Event Counter Mode Block Diagram
16-bit Auto-Reload
Register (T1RA)
Data
Bus
Underflow
Interrupt
16-bit Counter (TMR1)
T1
Edge Selector
Logic
21
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.3 Mode 2: External Event Counter Mode
input capture mode even while the timer is running. This feature
allows you to measure the width of a pulse received on an input pin.
In the Input Capture mode, the timer is used to measure elapsed time
between edges of an input signal. Once the timer is configured for this
mode, the timer starts counting down immediately at the instruction
clock rate. The Timer 1 will then transfer the current value of the TMR1
register into the T1RA register as soon as the selected edge of T1 is
sensed. The input signal on T1 must have a pulse width equal to or
greater than one instruction clock cycle. At every T1RA capture,
software can then store the values into RAM to calculate the elapsed
time between edges on T1. At any given time (with proper consideration of the state of T1) the timer can be configured to capture on
positive-going or negative-going edges. A block diagram of the
timer’s Input Capture mode of operation is shown in Figure 17.
For example, the T1 pin can be programmed to be sensitive to a
positive-going edge. When the positive edge is sensed, the TMR1
register contents is transferred to the T1RA register and a Timer 1
interrupt is generated. The Timer 1 interrupt service routine records
the contents of the T1RA register, changes the edge sensitivity from
positive to negative-going edge, and clears the T1PND flag. When the
negative-going edge is sensed another Timer 1 interrupt is generated.
The interrupt service routine reads the T1RA register again. The
difference between the previous reading and the current reading
reflects the elapsed time between the positive edge and negative
edge of the T1 input signal i.e. the width of the positive-going pulse.
Remember that the Timer1 interrupt service routine must test the
T1C0 and T1PND flags to determine the cause of the interrupt. If the
T1C0 flag caused the interrupt, the interrupt service routine should
record the occurrence of an underflow by incrementing a counter in
memory or by some other means. The software that calculates the
elapsed time between captures should take into account the
number of underflow that occurred when making its calculation.
The timer has one interrupt (TMRI1) that is maskable through the
T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit of the
SR is set. The Input Capture mode contains two interrupt pending
flags 1) the TMR1 register capture in T1RA (T1PND) and 2) timer
underflow (T1C0). If interrupts are enabled, the timer will generate an
interrupt each time a pending flag is set (provided that the pending flag
was previously cleared.) The interrupt service routine is responsible
for proper handling of the T1PND flag, T1C0 flag, and the T1EN bit.
The following steps show how to properly configure Timer 1 to
operate in the Input Capture mode.
For this operating mode, the T1C0 control bit serves as the timer
underflow interrupt pending flag. The Timer 1 interrupt service
routine must read both the T1PND and T1C0 flags to determine the
cause of the interrupt. A set T1C0 flag means that a timer underflow
occurred whereas a set T1PND flag means that a capture occurred
in T1RA. It is possible that both flags will be found set, meaning that
both events occurred at the same time. The interrupt service routine
should take this possibility into consideration.
1. Configure T1 as an input by clearing bit 2 of PORTGC.
- RBIT 2, PORTGC
; Configure G2 as an input
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Enable the global interrupt enable bit.
- SBIT 4, STATUS
4. With the timer stopped, load the initial time into the TMR1
register (typically the value is 0xFFFF.)
- LD TMR1LO, #0FFH
- LD TMR1HI, #00H
Because the T1C0 bit is used as the underflow interrupt pending
flag, it is not available for use as a start/stop bit as in the other modes.
The TMR1 register counts down continuously at the instruction
clock rate starting from the time that the input capture mode is
selected. (See Table 12and Table 13) To stop the timer from
running, you must change the mode to an alternate mode (PWM
or External Event Counter) while resetting the T1C0 bit.
5. Write the appropriate control value to the T1CNTRL register
to select Input Capture mode, to sense the appropriate edge,
to set the enable bit, and to clear the pending flags. (See
Table 12 and Table 13)
- LD T1CNTRL, #64H
; T1C1 is the edge select bit
The input pins can be independently configured to sense positivegoing or negative-going transitions. The edge sensitivity of pin T1
is controlled by bit T1C1 as indicated in Table 13.
6. As soon as the input capture mode is enabled, the timer
starts counting. When the selected edge is sensed on T1,
the T1RA register is loaded and a Timer 1 interrupt is
triggered.
The edge sensitivity of a pin can be changed without leaving the
Figure 17: Input Capture Mode Block Diagram
Capture
Interrupt
16-bit Input Capture
Register (T1RA)
T1
Edge Selector
Logic
Data
Bus
Underflow
Interrupt
16-bit Timer (TMR1)
Instruction
Clock
22
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.4 Mode 3: Input Capture Mode
reset by software or system reset.
Timer 0 is a 12-bit free running idle timer. Upon power-up or any
reset, the timer is reset to 0x000 and then counts up continuously
based on the instruction clock of 1MHz (1 µs). Software cannot
read from or write to this timer. However, software can monitor the
timer’s pending (T0PND) bit that is set every 8192 cycles (initially
4096 cycles after a reset). The T0PND flag is set every other time
the timer overflows (transitions from 0xFFF to 0x000) through a
divide-by-2 circuit. After an overflow, the timer will reset and restart
its counting sequence.
The WKINTEN bit is used in the Multi-input Wakeup/Interrupt
block. See Section 8 for details.
7.0 Watchdog
The Watchdog timer is used to reset the device and safely recover
in the rare event of a processor “runaway condition.” The 12-bit
Timer 0 is used as a pre-scaler for Watchdog timer. The Watchdog
timer must be serviced before every 61,440 cycles but no sooner
than 4096 cycles since the last Watchdog reset. The Watchdog is
serviced through software by writing the value 0x1B to the
Watchdog Service (WDSVR) register (see Figure 19). The part
resets automatically if the Watchdog is serviced too frequent, or
not frequent enough.
Software can either poll the T0PND bit or vector to an interrupt
subroutine. In order to interrupt on a T0PND, software must be
sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the
Timer 0 control (T0CNTRL) register and also make sure the G bit
is set in SR. Once the timer interrupt is serviced, software should
reset the T0PND bit before exiting the routine. Timer 0 supports
the following functions:
The Watchdog timer must be enabled through the Watchdog
enable bit (WDEN) in the initialization register. The WDEN bit can
only be set while the device is in programming mode. Once set, the
Watchdog will always be powered-up enabled. Software cannot
disable the Watchdog. The Watchdog timer can only be disabled
in programming mode by resetting the WDEN bit as long as the
memory write protect (WDIS) feature is not enabled.
1. Exiting from IDLE mode (See Section 16.0 for details.)
2. Start up delay from HALT mode
3. Watchdog pre-scaler (See Section 7.0 for details.)
The T0INTEN bit is a read/write bit. If set to 0, interrupt requests
from the Timer 0 are ignored. If set to 1, interrupt requests are
accepted. Upon reset, the T0INTEN bit is reset to 0.
WARNING
Ensure that the Watchdog timer has been serviced before entering IDLE mode because it remains operational during this time.
The T0PND bit is a read/write bit. If set to 1, it indicates that a Timer
0 interrupt is pending. This bit is set by a Timer 0 overflow and is
Figure 18: Timer 0 Control Register Definition (T0CNTRL)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WKINTEN
x
x
x
x
x
T0PND
T0INTEN
Figure 19: Watchdog Server Register (WDSVR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
1
1
23
ACE1101 Product Family Rev. B.2
www.fairchildsemi.com
ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
6.0 Timer 0
6. Set the WKEN bits associated with the pins to be used, thus
enabling those pins for the Wakeup/Interrupt function.
- LD WKEN, #10H
; Enabling G4
The Multi-Input Wakeup (MIW)/Interrupt contains three memorymapped registers associated with this circuit: WKEDG (Wakeup
Edge), WKEN (Wakeup Enable), and WKPND (Wakeup Pending).
Each register has 8-bits with each bit corresponding to an input pins as
shown in Figure 20. All three registers are initialized to zero upon reset.
Once the Multi-Input Wakeup/Interrupt function has been configured, a transition sensed on any of the I/O pins will set the
corresponding bit in the WKPND register. The WKPND bits , where
the corresponding enable (WKEN ) bits are set, will bring the device
out of the HALT/IDLE mode and can also trigger an interrupt if
interrupts are enabled. The interrupt service routine can read the
WKPND register to determine which pin sensed the interrupt.
The WKEDG register establishes the edge sensitivity for each of the wakeup input pin: either positive going-edge (0) or negative-going edge (1).
The WKEN register enables (1) or disables (0) each of the port
pins for the Wakeup/Interrupt function. The wakeup I/Os used for
the Wakeup/Interrupt function must also be configured as an input
pin in its associated port configuration register. However, an
interrupt of the core will not occur unless interrupts are enabled for
the block via bit 7 of the T0CNTRL register (see Figure 18) and the
G (global interrupt enable) bit of the SR is set.
The interrupt service routine or other software should clear the
pending bit. The device will not enter HALT/IDLE mode as long as
a WKPND pending bit is pending and enabled. The user has the
responsibility of clearing the pending flags before attempting to
enter the HALT/IDLE mode.
Upon reset, the WKEDG register is configured to select positivegoing edge sensitivity for all wakeup inputs. If the user wishes to
change the edge sensitivity of a port pin, use the following procedure to avoid false triggering of a Wakeup/Interrupt condition.
The WKPND register contains the pending flags corresponding to
each of the port pins (1 for wakeup/interrupt pending, 0 for
wakeup/interrupt not pending).
To use the Multi-Input Wakeup/Interrupt circuit, perform the steps listed
below. Performing the steps in the order shown will prevent false
triggering of a Wakeup/Interrupt condition. This same procedure
should be used following any type of reset because the wakeup inputs
are left floating after resets resulting in unknown data on the port inputs.
1. Clear the WKEN bit associated with the pin to disable that pin.
2. Write the WKEDG register to select the new type of edge
sensitivity for the pin.
3. Clear the WKPND bit associated with the pin.
4. Set the WKEN bit associated with the pin to re-enable it.
1. Clear the WKEN register.
- CLR WKEN
PORTG provides the user with three fully selectable, edge sensitive interrupts that are all vectored into the same service subroutine. The interrupt from PORTG shares logic with the wakeup
circuitry. The WKEN register allows interrupts from PORTG to be
individually enabled or disabled. The WKEDG register specifies
the trigger condition to be either a positive or a negative edge. The
WKPND register latches in the pending trigger conditions.
2. If necessary, write to the port configuration register to select
the desired port pins to be configured as inputs.
- RBIT 4, PORTGC
; G4
3. If necessary, write to the port data register to select the
desired port pins input state.
- SBIT 4, PORTGD
; Pull-up
Since PORTG is also used for exiting the device from the HALT/IDLE
mode, the user can elect to exit the HALT/IDLE mode either with or without
the interrupt enabled. If the user elects to disable the interrupt, then the
device restarts execution from the point at which it was stopped (first
instruction cycle of the instruction following HALT/IDLE mode entrance
instruction). In the other case, the device finishes the instruction that was
being executed when the part was stopped and then branches to the
interrupt service routine. The device then reverts to normal operation.
4. Write the WKEDG register to select the desired type of edge
sensitivity for each of the pins used.
- LD WKEDG, #0FFH
; All negative-going edges
5. Clear the WKPND register to cancel any pending bits.
- CLR WKPND
Figure 20: Multi-input Wakeup (MIW) Register Definition
WKEDG, WKEN, WKPND
10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10G7
10G6
G5
G4
G3
G2
G1
G0
Available only on the 14-pin package option
Figure 21: Multi-input Wakeup (MIWU) Block Diagram
Data Bus
7
0
WKEN[7:0]
G0
0
WKOUT
EDGEI
G7
7
WKEDG[0:7]
11
WKINTEN 11
WKPND[0:7]
WKINTEN: Bit 7 of T0CNTRL
24
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
8.0 Multi-Input Wakeup/interrupt Block
I/O Port
(PORTGC), a port data register (PORTGD), and a port input
register (PORTGP). PORTGC is used to configure the pins as
inputs or outputs. A pin may be configured as an input by writing
a 0 or as an output by writing a 1 to its corresponding PORTGC bit.
If a pin is configured as an output, its PORTGD bit represents the
state of the pin (1 = logic high, 0 = logic low). If the pin is configured
as an input, its PORTGD bit selects whether the pin is a weak pullup or a high-impedence input. Table 14 provides details of the port
configuration options. The port configuration and data registers
can both be read from or written to. Reading PORTGP returns the
value of the port pins regardless of how the pins are configured.
Since this device supports MIW, PORTG inputs have Schmitt
triggers.
The six I/O pins (eight on 14-pin package option) are bi-directional
(see Figure 22) with the exception of G3 which is always an input
with weak pull-up. The bi-directional I/O pins can be individually
configured by software to operate as high-impedance inputs, as
inputs with weak pull-up, or as push-pull outputs. The operating
state is determined by the contents of the corresponding bits in the
data and configuration registers. Each bi-directional I/O pin can be
used for general purpose I/O, or in some cases, for a specific
alternate function determined by the on-chip hardware.
9.1 I/O registers
The I/O pins (G0-G7) have three memory-mapped port registers
associated with the I/O circuitry: a port configuration register
Figure 22: PORTG Logic Diagram
GXPULLEN
GXBUFEN
PADGX
GXOUT
GXIN
Figure 23: I/O Register bit assignments (PORTGC, PORTGD, PORTGD)
PORTGC, PORGD, PORTGD
Bit 7
Bit 6
G712
G612
12
Available only on the 14-pin package option
13
G3 is always an input with weak pull-up.
Bit 5
G5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G4
G313
G2
G1
G0
Table 14: I/O configuration options
Configuration Bit
Data Bit
Port Pin Configuration
0
0
High-impedence input (TRI-STATE input)
0
1
Input with pull-up (weak one input)
1
0
Push-pull zero output
1
1
Push-pull one output
25
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
9.0
The ACEx microcontroller supports in-circuit programming of the
internal data EEPROM, code EEPROM, and the initialization registers. An externally controlled four wire interface consisting of a LOAD
control pin (G3), a serial data SHIFT-IN input pin (G4), a serial data
SHIFT-OUT output pin (G2), and a CLOCK pin (G1) is used to access
the on-chip memory locations. Communication between the ACEx
microcontroller and the external programmer is made through a 32bit command and response word described in Table 15.
0V phase (if the timing specifications in Figure 24 are obeyed).
The device will set the R bit of the Status register when the write
operation has completed. The external programmer must wait for
the SHIFT_OUT pin to go high before bringing the LOAD signal to
5V to initiate a normal command cycle.
10.2 Read Sequence
When reading the device after a write, the external programmer must
set the LOAD signal to 5V before it sends the new command word.
Next, the 32-bit serial command word (for during a READ) should be
shifted into the device using the SHIFT_IN and the CLOCK signals
while the data from the previous command is serially shifted out on
the SHIFT_OUT pin. After the Read command has been shifted into
the device, the external programmer must, once again, set the LOAD
signal to 0V and apply two clock pulses as shown in Figure 24 to
complete READ cycle. Data from the selected memory location, will
be latched into the lower 8 bits of the command word shortly after the
second rising edge of the CLOCK signal.
The serial data timing for the four-wire interface is shown in Figure
25 and the programming protocol is shown in Figure 24.
10.1 Write Sequence
The external programmer brings the ACEx microcontroller into
programming mode by applying a super voltage level to the LOAD
pin. The external programmer then needs to set the LOAD pin to 5V
before shifting in the 32-bit serial command word using the SHIFT_IN
and CLOCK signals. By definition, bit 31 of the command word is
shifted in first. At the same time, the ACEx microcontroller shifts out
the 32-bit serial response to the last command on the SHIFT_OUT
pin. It is recommended that the external programmer samples this
signal tACCESS (1µs) after the rising edge of the CLOCK signal. The
serial response word, sent immediately after entering programming
mode, contains indeterminate data.
Writing a series of bytes to the device is achieved by sending a
series of Write command words while observing the devices
handshaking requirements.
Reading a series of bytes from the device is achieved by sending
a series of Read command words with the desired addresses in
sequence and reading the following response words to verify the
correct address and data contents.
After 32 bits have been shifted into the device, the external
programmer must set the LOAD signal to 0V, and then apply two
clock pulses as shown in Figure 24 to complete program cycle.
The SHIFT_OUT pin acts as the handshaking signal between the
device and programming hardware once the LOAD signal is
brought low. The device sets SHIFT_OUT low by the time the
programmer has sent the second rising edge during the LOAD =
The addresses of the data EEPROM and code EEPROM locations are the same as those used in normal operation.
Powering down the device will cause the part to exit programming
mode.
Table 15: 32-Bit Command and Response Word
Bit number
Output response word
bits 31 – 30
Must be set to 0
X
bit 29
Set to 1 to read/write data EEPROM or the initialization registers, otherwise 0
X
bit 28
Set to 1 to read/write code EEPROM,
otherwise 0
X
bits 27 – 25
Must be set to 0
X
bit 24
Set to 1 to read, 0 to write
X
bits 23 – 18
Must be set to 0
X
bits 17 – 8
Address of the byte to be read or written
Same as Input command word
bits 7 – 0
Data to be programm ed or zero if data is to be read
Programmed data or data read at specified address
14Ffor
15
Input command word
further information see Application Note AN-8005.
During in-circuit programming, G5 must be either not connected or driven high.
26
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
10.0 In-circuit Programming Specification14, 15
tSV1
tSV2
A
A
tload1 tload2
LOAD (G3)
enter prog.
mode
tready
tload3
tload4
32 clock pulses
CLOCK (G1)
SHIFT_IN (G4)
bit 31
bit 30
bit 0
bit 31
BUSY low by
2nd clock pulse
SHIFT_OUT (G2)
(in write mode)
READY
BUSY
SHIFT_OUT (G2)
(in read mode)
A: start of programming cycle
Figure 25- Serial Data Timing
tLO
tHI
CLOCK (G1)
tDIS
SHIFT_IN (G4)
tDIH
Valid
tDOS
tDOH
Valid
SHIFT_OUT (G2)
tACCESS
27
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 24- Programming Protocol15
can be thought of as a supplement function to the Power-on Reset
when VCC does not fall below ~1.5V. The Power-on Reset circuit
works best when VCC starts from zero and rises sharply. So in
applications where VCC is not constant, the BOR will give added
device stability.
The Brown-out Reset (BOR) and Low Battery Detect (LBD)
circuits on the ACEx microcontroller have been designed to offer
two types of voltage reference comparators. The sections below
will describe the functionality of both circuits.
The BOR circuit must be enabled through the BOR enable bit
(BOREN) in the initialization register. The BOREN bit can only be
set while the device is in programming mode. Once set, the BOR
will always be powered-up enabled. Software cannot disable the
BOR. The BOR can only be disabled in programming mode by
resetting the BOREN bit as long as the global write protect (WDIS)
feature is not enabled.
Figure 26: BOR/LBD Block Diagram
Vcc
1.8V
0
2.2V
1
S
_
to RESET logic
BOR
+
BLSEL16
11.2 Low Battery Detect
_
The Low Battery Detect (LBD) circuit allows software to monitor
the VCC level at the lower voltage ranges. LBD has an eight level
software programmable voltage reference threshold that can be
changed on the fly. Once VCC falls below the selected threshold,
the LBD flag in the LBD control register is set. The LBD flag will
hold its value until VCC rises above the threshold. (See Table 16)
LBD
+
Adjust Reference Voltage
7
6
5
4
11.1 Brown-out
3
2
1
0
LBD
Control
Register
The LBD bit is read only. If LBD is 0, it indicates that the VCC level
is higher than the selected threshold. If LBD is 1, it indicates that
the VCC level is below the selected threshold. The threshold level
can be adjusted up to eight levels using the three trim bits
(Bat_trim[2:0]) of the LBD control register. The LBD flag does not
cause any hardware actions or an interruption of the processor. It
is for software monitoring only.
Reset 17
The Brown-out Reset (BOR) function is used to hold the device in
reset when VCC drops below a fixed threshold. (See BOR Electrical Characteristics for threshold voltage.) While in reset, the
device is held in its initial condition until VCC rises above the
threshold value. Shortly after VCC rises above the threshold value,
an internal reset sequence is started. After the reset sequence, the
core fetches the first instruction and starts normal operation.
The LBD function is disabled during HALT/IDLE mode. After
exiting HALT/IDLE, software must wait at lease 10 µs before
reading the LBD bit to ensure that the internal circuit has stabilized.
On the devices, the BOR should be used in situations when VCC
rises and falls slowly and in situations when VCC does not fall to
zero before rising back to operating range. The Brown-out Reset
16
See Figure 14 for information on BLSEL.
17
BOR is not available on the ACE1101B device.
Table 16: LBD Control Register Definition
Bit 7
Bit 6
Bit 5
Bat_trim[2:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
LBD
Level
Bat_trim[2]
Bat_trim[1]
1
0
0
0
2.9 - 3.0
2
0
0
1
2.8 - 2.9
3
0
1
0
2.7 - 2.8
4
0
1
1
2.6 - 2.7
5
1
0
0
2.5 - 2.6
6
1
0
1
2.4 - 2.5
7
1
1
0
2.3 - 2.4
8
1
1
1
2.2 - 2.3
28
ACE1101 Product Family Rev. B.2
Voltage
Reference
Bat_trim[0] Range (±20%)
www.fairchildsemi.com
ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
11.0 Brown-out/Low Battery Detect Circuit
The external reset provides a way to properly reset the ACEx
microcontroller if POR cannot be used in the application. The
external reset pin contains an internal pull-up resistor. Therefore,
to reset the device the reset pin should be held low for at least 2ms
so that the internal clock has enough time to stabilize.
When a RESET sequence is initiated, all I/O registers will be reset
setting all I/Os to high-impedence inputs. The system clock is
restarted after the required clock start-up delay. A reset is generated by any one of the following three conditions:
14.0 CLOCK
• Power-on Reset (as described in Section 13.0)
The ACEx microcontroller has an on-board oscillator trimmed to
a frequency of 2MHz who is divided down by two yielding a 1MHz
frequency. (See AC Electrical Characteristics.) Upon power-up,
the on-chip oscillator runs continuously unless entering HALT
mode or using an external clock source.
• Brown-out Reset (as described in Section 11.1)
• Watchdog Reset (as described in Section 7.0)
• External Reset18 (as described in Section 13.0)
13.0 Power-On-Reset
If required, an external oscillator circuit may be used depending on
the states of the CMODE bits of the initialization register. (See
Table 17) When the device is driven using an external clock, the
clock input to the device (G1/CKI) can range between DC to
4MHz. For external crystal configuration, the output clock (CKO)
is on the G0 pin. (See Figure 28) If an external crystal or RC is
used, internally the input frequency (CKI) is divided-down by four
to yield the corresponding instruction clock. If the device is
configured for an external square clock, it will not be divided.
The Power-On Reset (POR) circuit is guaranteed to work if the
rate of rise of VCC is no slower than 10ms/1volt. The POR circuit
was designed to respond to fast low to high transitions between 0V
and VCC. The circuit will not work if VCC does not drop to 0V before
the next power-up sequence. In applications where 1) the VCC rise
is slower than 10ms/1 volt or 2) VCC does not drop to 0v before the
next power-up sequence the external reset option should be used.
Table 17: CMODEx Bit Definition
CMODE[1]
CMODE[0]
0
0
Internal 1 MHz clock
Clock Type
0
1
External square clock
1
0
External crystal/resonator
1
1
External RC clock
Figure 27: BOR and POR Circuit Relationship Diagram
VCC (Pin 8)
BOR
output
VCC
1.75
VCC
0
VCC
0
Time
BOR Output
A
POR
output
External
Reset
Pin
(14-Pin Only)
VCC
5.0V
(Pin 7)
18
Reset
circuit
output
1.8V
0
VCC
POR
output 0
Global Reset
to Logic
B
The Reset circuit will trigger
when inputs A or B transition
from High to Low. At that time
the Global Reset signal will go
high which will reset all controller
logic. The Global Reset will go
high and stay high for around 1µs.
POR Output
Pulse
Available only on the 14-pin package option.
29
ACE1101 Product Family Rev. B.2
www.fairchildsemi.com
ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
12.0 RESET block
a)
b)
CKI
(G1)
CKO
(G0)
CKI
(G1)
CKO
(G0)
1M
R
VCC
C
33pF
33pF
15.0 HALT Mode
16.0 IDLE Mode
The HALT mode is a power saving feature that almost completely
shuts down the device for current conservation. The device is
placed into HALT mode by setting the HALT enable bit (EHALT)
of the HALT register through software using only the “LD M, #”
instruction. EHALT is a write only bit and is automatically cleared
upon exiting HALT. When entering HALT, the internal oscillator
and all the on-chip systems including the LBD and the BOR
circuits are shut down.
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed into
IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT
register through software using only the “LD M, #” instruction.
EIDLE is a write only bit and is automatically cleared upon exiting
IDLE. The IDLE mode operation is similar to HALT except the
internal oscillator, the Watchdog, and the Timer 0 remain active
while the other on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit HALT mode only by the MIW circuit. Therefore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 8) After a wakeup from
HALT, a 1ms start-up delay is initiated to allow the internal
oscillator to stabilize before normal execution resumes. Immediately after exiting HALT, software must clear the Power Mode
Clear (PMC) register by only using the “LD M, #” instruction. (See
Figure 30)
The device can exit IDLE by a Timer 0 overflow every 8192 cycles
or/and by the MIW circuit. If exiting IDLE mode with the MIW, prior
to entering, software must configure the MIW circuit accordingly.
(See Section 8) Once a wake from IDLE mode is triggered, the
core will begin normal operation by the next clock cycle. Immediately after exiting IDLE mode, software must clear the Power
Mode Clear (PMC) register by using only the “LD M, #” instruction.
(See Figure 31)
Figure 29: HALT Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
undefined
undefined
undefined
undefined
undefined
undefined
EIDLE
EHALT
Figure 30: Recommended HALT Flow
Figure 31: Recommended IDLE Flow
Normal Mode
Normal Mode
LD
LD HALT, #01h
HALT, #01H
Timer0
Underflow
IDLE Mode
Multi-Input
Wakeup
Multi-Input
Wakeup
Halt
LD
PMC, #00H
Resume Normal
Mode
LD PMC, #00h
Resume
Normal Mode
30
ACE1101 Product Family Rev. B.2
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 28: Crystal (a) and RC (b) Oscillator Diagrams
Part Numbe
Core Type
0
1
2
Max. #
I/Os
8
Program
Memory Size
1K
2K
Operating Voltage Range
1.8 –
5.5V
2.2 –
5.5V
2.7 –
5.5V
Temperature Range
0 to
70°C
-40 to
+85C
Package
-40 to
+125°C
8-pin
TSSOP
ACE1101MT8
X
X
X
X
X
X
ACE1101MT8X
X
X
X
X
X
X
ACE1101N
X
X
X
X
X
ACE1101N14
X
X
X
X
X
ACE1101EMT8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101EN14
X
X
X
X
X
ACE1101VMT8
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101VN
X
X
X
X
X
ACE1101VN14
X
X
X
X
ACE1101BMT8
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101BN
X
X
X
X
X
ACE1101BN14
X
X
X
X
X
ACE1101BEMT8
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101BEN
X
X
X
X
X
X
ACE1101BEN14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101BVMT8X
X
X
X
X
X
ACE1101BVN
X
X
X
X
X
ACE1101BVN14
X
X
X
ACE1101LMT8
X
X
X
X
X
X
ACE1101BEMT8X
ACE1101BVMT8
X
X
ACE1101BMT8X
X
X
X
X
X
X
X
ACE1101LMT8X
X
X
X
X
X
ACE1101LN
X
X
X
X
X
ACE1101LN14
X
X
X
X
X
ACE1101 Product Family Rev. B.2
X
X
ACE1101VMT8X
31
X
X
X
ACE1101EN
X
14-pin
DIP
X
ACE1101EMT8X
X
8-pin
DIP
Tape
and
Reel
X
X
X
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ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Ordering Information
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0118
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP (MT8)
Order Number ACE1101(1101L)MT8/ACE1101EMT8/ACE1101VMT8
ACE1101BMT8/ACE1101BEMT8/ACE1101BVMT8
Package Number MTC08
32
ACE1101 Product Family Rev. B.2
www.fairchildsemi.com
ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
8-Pin DIP (N)
Order Number ACE1101(1101L)N/ACE1101EN/ACE1101VN
ACE1101BN/ACE1101BEN/ACE1101BVN
Package Number N08E
33
ACE1101 Product Family Rev. B.2
www.fairchildsemi.com
ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
14-Pin DIP (N14)
Order Number ACE1101(1101L)N14/ACE1101EN14/ACE1101VN14
ACE1101BN14/ACE1101BEN14/ACE1101BVNT14
Package Number N014A
34
ACE1101 Product Family Rev. B.2
www.fairchildsemi.com
ACEx Emulator Kit: Fairchild also offers a low cost real-time incircuit emulator kit that includes:
General Information
Emulator board
Fairchild Semiconductor offers different possibilities to evaluate
and emulate software written for ACEx.
Emulator software
ACEx Starter Kit includes:
Power supply
Assembler and Manuals
Programmer Board
DIP14 target cable
Simulator Software
PC cable
Programmer Software
The ACEx emulator allows for debugging the program code in a
symbolic format. It is possible to place one breakpoint and watch
various data locations. It also has built-in programming capability.
Assembler and Manuals
Cables and samples devices
Prototype Board Kits: Fairchild offer two solutions for the simplification of the breadboard operation so that ACEx Applications
can be quickly tested.
DIP programming sockets
Programmer board: Interfaces with a PC through a Windows
program using the serial communication port. This board is
intended for engineering prototype and can be used for small
volume production. Fairchild offers factory pre-programming and
serialization (for justified quantities) for a small additional cost.
Please refer to your local distributor for details regarding factory
programming.
1) ACEDEMO is can be used for general purpose applications
2) ACETXRX for transmitting / receiving (RF, IR, RS232,
RS485) applications.
ACEDEMO has 8 switches, 8 LEDs, RS232 voltage translator,
buzzer, and a lamp with a small breadboard area.
Simulator: Is a Windows program able to load, assemble, and
debug ACEx programs. It is possible to place as many breakpoints
as needed, trace the program execution in symbolic format, and
program a device with the proper options. The ACEx Simulator is
available free-of-charge and can be downloaded from Fairchild’s
web site at www.fairchildsemi.com/products/memory/ace
Ordering P/Ns
Starter Kit:
ACESTART1101
ACESTART1202
Programming Adapters:
DIP8 - ACESDIP8
DIP14 - ACESDIP14
TSSOP8 - ACESTSSOP8
SO8 - ACESSOP8
SO14 - ACESSOP15
Emulator Kit: ACEICE (110Vac)
ACEICE_EU (220Vac)
Prototype Boards:
ACEDEMO
ACETXRX (specify RF freq. 433 or 315MHz)
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
35
ACE1101 Product Family Rev. B.2
www.fairchildsemi.com
ACE1101 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
ACEx Development Tools