25/0251 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM • Fully asynchronous operation • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Pin select for Master or Slave • Commercial and Industrial Temperature Ranges • Available in 68-pin PLCC (all) and 64-pin TQFP (7C006AV & 7C144AV) • Pin-compatible and functionally equivalent to IDT70V05, 70V06, and 70V07. Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 4K/8K/16K/32K x 8 organizations (CY7C0138AV/144AV/006AV/007AV) • 4K/8K/16K/32K x 9 organizations (CY7C0139AV/145AV/016AV/017AV) • 0.35-micron CMOS for optimum speed/power • High-speed access: 20/25 ns • Low operating power — Active: ICC = 115 mA (typical) — Standby: ISB3 = 10 µA (typical) Logic Block Diagram R/WL R/WR CEL CER OEL OER [1] 8/9 I/O0R–I/O7/8R I/O Control [2] A0L–A11–14L [2] 12–15 Address Decode I/O Control Address Decode True Dual-Ported RAM Array 12–15 12–15 [2] A0R–A11–14R 12–15 A0L–A11–14L CEL OEL R/WL SEM L [1] 8/9 I/O0L–I/O7/8L [2] A0R–A11–14R CER OE R Interrupt Semaphore Arbitration [3] [3] BUSYL INTL R/WR SEM R BUSYR INT R M/S Notes: 1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 2. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices; 3. BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 7, 2000 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Functional Description sor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. The CY7C138AV/144AV/006AV/007AV and CY7C139AV/ 145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and 32K x8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interproces- Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. Pin Configurations 9 8 7 6 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A8L A7L A6L NC NC VCC NC A 11L A 10L A9L NC [4] OE L R/W L SEM L CEL I/O 1L I/O 0L 68-Pin PLCC Top View 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C138AV (4K x 8) 52 CY7C139AV (4K x 9) 51 50 49 48 47 46 45 44 Notes: 4. I/O8L on the CY7C139AV. 5. I/O8R on the CY7C139AV. 2 A5R A7R A6R A 9R A8R R/W R SEM R CER NC NC GND NC A 11R A10R [5] NC OER I/O7R 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Pin Configurations (continued) 9 8 7 6 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A6L A8L A7L NC NC VCC A12L A 11L A 10L A9L [6] NC OE L R/W L SEM L CEL I/O 1L I/O 0L 68-Pin PLCC Top View 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C144AV (8K x 8) 52 CY7C145AV (8K x 9) 51 50 49 48 47 46 45 44 A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A7R A6R A 9R A8R R/W R SEM R CER NC NC GND A12R A 11R A10R [7] NC OER I/O7R 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 A6L A5L 49 54 A7L A12L 56 55 51 50 VCC 57 A8L CEL NC 59 A9L SEML 60 52 R/WL 53 OEL 62 61 A11L A10L I/O0L 63 58 I/O1L 64 64-Pin TQFP Top View I/O2L 1 48 A4L I/O3L I/O4L 2 47 3 4 46 45 A3L A2L 5 44 A0L I/O6L I/O7L 6 43 7 42 INTL BUSYL GND M/S I/O5L GND A1L VCC 8 GND I/O0R I/O1R 9 10 11 38 INTR I/O2R 12 37 VCC 13 36 A0R A1R I/O3R I/O4R 14 15 35 34 A2R I/O5R 16 33 A4R 41 3 30 31 A7R 32 29 A6R A5R 28 A8R 40 39 A9R 27 24 GND Notes: 6. I/O8L on the CY7C145AV. 7. I/O8R on the CY7C145AV. A11R A10R 23 25 26 22 CER NC A12R 21 SEMR 19 20 OER 18 I/O7R R/WR 17 I/O6R CY7C144AV (8K x 8) BUSYR A3R CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Pin Configurations (continued) I/O2L I/O3L I/O4L 10 I/O5L GND I/O6L I/O7L 13 A9L A8L A7L A6L 64 63 62 61 VCC 68 67 A11L A10L A14L A13L 2 1 65 CEL 3 A12L SEML 4 66 R/WL 5 [9] I/O0L I/O8L [8] OEL 7 6 I/O1L 12 I/O2R VCC 21 22 23 24 A5L A4L 58 A3L A2L A1L 56 55 16 17 18 60 59 57 14 15 GND I/O0R I/O1R CY7C006AV (16K CY7C007AV (32K CY7C016AV (16K CY7C017AV (32K 19 20 x 8) x 8) x 9) x 9) INTL 53 BUSYL GND M/S 52 51 50 47 41 42 43 A6R A5R 40 A8R A7R 37 A11R A10R A9R 36 A12R 38 39 35 GND A13R 33 34 32 A14R[9] 31 CER 44 30 26 SEMR 46 45 29 25 OER R/WR A0L 54 49 48 27 28 I/O3R I/O4R I/O5R I/O6R 8 11 I/O7R I/O8R[8] VCC 9 68-Pin PLCC Top View BUSYR INTR A0R A1R A2R A3R A4R 49 54 A6L A5L A12L 56 55 51 50 VCC 57 A8L A7L CEL A13L 59 52 SEML A9L R/WL 60 53 OEL 62 61 A11L A10L I/O0L 63 58 I/O1L 64 64-Pin TQFP Top View I/O2L 1 48 A4L I/O3L I/O4L 2 47 3 4 46 45 A3L A2L 5 44 A0L I/O6L I/O7L 6 43 7 42 VCC 8 INTL BUSYL GND M/S I/O5L GND 41 CY7C006AV (16K x 8) A1L 4 32 30 31 A6R A5R 29 R/WR Notes: 8. I/O for CY7C016AV and CY7C017AV only. NC for other parts. 9. Address line for CY7C007AV and CY7C017AV only. NC for other parts. A8R A7R A4R 28 33 A9R 16 27 I/O5R A11R A10R A2R 25 26 35 34 A12R 14 15 24 I/O3R I/O4R GND A0R A1R 23 36 22 13 CER A13R VCC 21 37 SEMR 12 19 20 INTR I/O2R OER 38 18 11 17 40 39 I/O6R 9 10 I/O7R GND I/O0R I/O1R BUSYR A3R CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Selection Guide CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -20 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -25 Maximum Access Time (ns) 20 25 Typical Operating Current (mA) 120 115 Typical Standby Current for ISB1 (mA) (Both Ports TTL level) 35 30 Typical Standby Current for ISB3 (µA) (Both Ports CMOS level) 10 µA 10 µA Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A14L A0R–A14R Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K) I/O0L–I/O 8L I/O0R–I/O8R Data Bus Input/Output (I/O 0–I/O7 for x8 devices and I/O0–I/O8 for x9) SEML SEM R Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current .................................................... >200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied .............................................–55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................–0.5V to VCC+0.5V Range Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 300 mV –40°C to +85°C 3.3V ± 300 mV Industrial DC Input Voltage[10] .................................–0.5V to VCC+0.5V Notes: 10. Pulse width < 20 ns. 11. Industrial parts are available in CY7C007AV and CY7C017AV only. 5 [11] CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Electrical Characteristics Over the Operating Range CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -20 Parameter Description Min. VOH Output HIGH Voltage (V CC = 3.3V) VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled –10 10 120 175 Ind.[11] 140 195 Com’l. 35 45 [11] 45 55 Com’l. 75 110 Ind.[11] 85 130 Com’l. 10 500 [11] 10 500 Com’l. 70 95 Ind.[11] 80 105 Ind. Unit 0.4 V 2.0 Com’l. Ind. Max. V V 0.8 Standby Current (One Port CMOS Level) CEL | CER ≥ V IH, f = fMAX[12] ISB4 Typ. 2.4 2.0 Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC – 0.2V, f = 0[12] ISB3 Min. 0.4 Standby Current (One Port TTL Level) CEL | CER ≥ V IH, f = fMAX[12] ISB2 Max. 2.4 Standby Current (Both Ports TTL Level) CEL & CER ≥ VIH, f = fMAX[12] ISB1 Typ. -25 0.8 –10 115 V 10 µA 165 mA mA 30 40 mA 65 95 mA mA mA 10 500 µA 60 80 mA µA mA Capacitance[13] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 10 pF 10 pF AC Test Loads and Waveforms 3.3V 3.3V R1 = 590Ω C = 30 pF RTH = 250Ω OUTPUT OUTPUT R1 = 590Ω OUTPUT C = 30 pF R2 = 435Ω C = 5 pF VTH = 1.4V (a) Normal Load (Load 1) (b) ThéveninEquivalent (Load 1) ALL INPUT PULSES 3.0V GND 10% R2 = 435Ω (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE & tLZWE including scope and jig) 90% 10% 90% ≤ 3 ns ≤ 3 ns Notes: 12. fMAX = 1/tRC. All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 13. Tested initially and after any design or process changes that may affect these parameters. 6 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Switching Characteristics Over the Operating Range[14] CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -20 Parameter Description Min. -25 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA tACE [15] 20 25 20 Output Hold From Address Change 3 ns 25 3 ns ns CE LOW to Data Valid 20 25 ns tDOE OE LOW to Data Valid 12 13 ns tLZOE[16, 17, 18] tHZOE[16, 17, 18] tLZCE[16, 17, 18] tHZCE[16, 17, 18] tPU[18] tPD[18] OE Low to Low Z 3 OE HIGH to High Z 3 12 CE LOW to Low Z 3 CE HIGH to High Z 15 3 12 CE LOW to Power-Up 0 CE HIGH to Power-Down ns ns 15 0 20 ns ns ns 25 ns WRITE CYCLE tWC Write Cycle Time 20 25 ns tSCE[15] CE LOW to Write End 16 20 ns tAW Address Valid to Write End 16 20 ns tHA Address Hold From Write End 0 0 ns tSA[15] Address Set-Up to Write Start 0 0 ns tPWE Write Pulse Width 16 20 ns tSD Data Set-Up to Write End 12 15 ns tHD Data Hold From Write End 0 tHZWE[17, 18] R/W LOW to High Z tLZWE[17, 18] tWDD[19] tDDD[19] R/W HIGH to Low Z 0 12 3 ns 15 3 ns ns Write Pulse to Data Delay 40 50 ns Write Data Valid to Read Data Valid 30 35 ns tBLA BUSY LOW from Address Match 20 20 ns tBHA BUSY HIGH from Address Mismatch 20 20 ns tBLC BUSY LOW from CE LOW 20 20 ns tBHC BUSY HIGH from CE HIGH 16 17 ns tPS Port Set-Up for Priority BUSY TIMING[20] 5 5 ns Note: 14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OI/IOH and 30-pF load capacitance. 15. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 17. Test conditions used are Load 3. 18. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 20. Test conditions used are Load 2. 7 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Switching Characteristics Over the Operating Range[14] (continued) CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -20 Parameter Description Min. -25 Max. Min. Max. Unit tWB R/W HIGH after BUSY (Slave) 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 15 17 ns tBDD[21] BUSY HIGH to Data Valid 20 25 ns INTERRUPT TIMING[20] tINS INT Set Time 20 20 ns tINR INT Reset Time 20 20 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 12 ns tSWRD SEM Flag Write to Read Time 5 5 ns tSPS SEM Flag Contention Window 5 5 ns tSAA SEM Address Access Time 20 Data Retention Mode 25 ns Timing The CY7C0138AV/144AV/006AV/007AV and CY7C139AV/ 145AV/016AV/017AV are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: Data Retention Mode VCC 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V. 3.0V VCC > 2.0V 3.0V VCC to VCC – 0.2V CE tRC V IH 2. CE must be kept between VCC – 0.2V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0 volts). Parameter ICC DR1 Notes: 21. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). 22. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested. 8 Test Conditions[22] @ VCCDR = 2V Max. Unit 50 µA CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Switching Waveforms Read Cycle No. 1 (Either Port Address Access)[23, 24, 25] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (Either Port CE/OE Access)[23, 26, 27] tACE CE tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Read Cycle No. 3 (Either Port)[23, 25, 26, 27] tRC ADDRESS tAA tOHA tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes: 23. R/W is HIGH for read cycles. 24. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads. 25. OE = VIL. 26. Address valid prior to or coincident with CE transition LOW. 27. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. 9 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31] tWC ADDRESS tHZOE [32] OE tAW CE [33] tPWE[31] tSA tHA R/W tHZWE[32] tLZWE [34] DATA OUT [34] tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 35] tWC ADDRESS tAW CE [33] tSA tSCE tHA R/W tSD tHD DATA IN Notes: 28. R/W must be HIGH during all address transitions. 29. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM. 30. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + t SD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 32. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 33. To access RAM, CE = VIL, SEM = VIH. 34. During this period, the I/O pins are in the output state, and input signals must not be applied. 35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 10 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side[36] tSAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O 0 DATA IN VALID tSA tPWE DATA OUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention[37, 38, 39] A0L –A 2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes: 36. CE = HIGH for the duration of the above timing (both write and read cycle). 37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 38. Semaphores are reset (available to both ports) at cycle start. 39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. 11 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH)[40] tWC ADDRESSR MATCH tPWE R/WR tHD tSD DATA IN R VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note: 40. CEL = CER = LOW. 12 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration)[41] CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Busy Timing Diagram No. 2 (Address Arbitration)[41] Left Address Valid First tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note: 41. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. 13 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR : ADDRESSL tWC WRITE FFF (See Functional Description) tHA [42] CE L R/W L INT R tINS [43] Right Side Clears INT R : tRC READ FFF (See Functional Description) ADDRESSR CE R tINR [43] R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE FFE (See Functional Description) tHA[42] CE R R/W R INT L [43] tINS Left Side Clears INT L: tRC READ FFE (See Functional Description) ADDRESSR CE L tINR[43] R/W L OE L INT L Notes: 42. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 43. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 14 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV neous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Architecture The CY7C138AV/144AV/006AV/007AV and CY7C139AV/ 145AV/016AV/017AV consist of an array of 4K, 8K, 16K, and 32K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the device can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The device also has an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Master/Slave An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Functional Description Read and Write Operations Semaphore Operation When writing data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. The CY7C138AV/144AV/006AV/007AV and CY7C139AV/ 145AV/016AV/017AV provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CY7C138AV/9AV, 1FFF for the CY7C144AV/5AV, 3FFF for the CY7C006AV/16AV, 7FFF for the CY7C007AV/17AV) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C138AV/9AV, 1FFE for the CY7C144AV/5AV, 3FFE for the CY7C006AV/16AV, 7FFE for the CY7C007AV/17AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Busy The CY7C138AV/144AV/006AV/007AV and CY7C139AV/ 145AV/016AV/017AV provide on-chip arbitration to resolve simulta- 15 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Table 1. Non-Contending Read/Write Inputs Outputs CE R/W OE SEM H X X H High Z Deselected: Power-Down H H L L Data Out Read Data in Semaphore Flag X X H X High Z I/O Lines Disabled X L Data In Write into Semaphore Flag H I/O0–I/O8 Operation L H L H Data Out Read L L X H Data In Write L X X L Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Right Port R/WL CEL OEL A0L–14L INTL R/WR CER OE R A0R–14R INTR Set Right INTR Flag L L X FFF[44] X X X X X L[45] Reset Right INTR Flag X X X X X X L L FFF[44] H[46] Set Left INTL Flag X X X X L[46] L L X 1FFE[44] X [45] X X X X X Reset Left INTL Flag X L L [44] 1FFE H Table 3. Semaphore Operation Example Function I/O0–I/O8 Left I/O0–I/O8 Right No action 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Note: 44. See Functional Description for specific addresses by device part number. 45. If BUSYL = L, then no change. 46. If BUSYR = L, then no change. 16 Status CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Ordering Information Package Availability Guide Device Organization 68-Pin PLCC CY7C138AV 4K x 8 X CY7C139AV 4K x 9 X CY7C144AV 8K x 8 X CY7C145AV 8K x 9 X CY7C006AV 16K x 8 X CY7C016AV 16K x 9 X CY7C007AV 32K x 8 X CY7C017AV 32K x 9 X 64-Pin TQFP X X 4K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C138AV–20JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 25 CY7C138AV–25JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 4K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C139AV–20JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 25 CY7C139AV–25JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 8K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Ordering Code CY7C144AV–20AC Package Name Package Type A65 64-Pin Thin Quad Flat Pack CY7C144AV–20JC J81 68-Pin Plastic Leaded Chip Carrier CY7C144AV–25AC A65 64-Pin Thin Quad Flat Pack CY7C144AV–25JC J81 68-Pin Plastic Leaded Chip Carrier Operating Range Commercial Commercial 8K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C145AV–20JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 25 CY7C145AV–25JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 16K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Ordering Code Package Name Package Type CY7C006AV–20AC A65 64-Pin Thin Quad Flat Pack CY7C006AV–20JC J81 68-Pin Plastic Leaded Chip Carrier CY7C006AV–25AC A65 64-Pin Thin Quad Flat Pack CY7C006AV–25JC J81 68-Pin Plastic Leaded Chip Carrier 17 Operating Range Commercial Commercial CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Ordering Information (continued) 16K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C016AV–20JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 25 CY7C016AV–25JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 32K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C007AV–20JC J81 68-Pin Plastic Leaded Chip Carrier Commercial CY7C007AV–20JI J81 68-Pin Plastic Leaded Chip Carrier Industrial 25 CY7C007AV–25JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 32K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C017AV–20JC J81 68-Pin Plastic Leaded Chip Carrier Commercial CY7C017AV–20JI J81 68-Pin Plastic Leaded Chip Carrier Industrial 25 CY7C017AV–25JC J81 68-Pin Plastic Leaded Chip Carrier Commercial Document #: 38-00837-*A 18 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Package Diagrams 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 51-85046-B 68-Lead Plastic Leaded Chip Carrier J81 51-85005-A © Cypress Semiconductor Corporation, 2000. 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