ETC HN29W6484AH03TE-1

HN29W6484AH03TE-1
Controller for AND Flash Memory
ADE-203-988A (Z)
Rev. 1.0
Apr. 16, 1999
Description
HN29W6484AH03TE-1 is a controller IC for flash ATA card. This IC is manufactured based on Hitachi 0.5
µm CMOS technology, and integrates control logic with 8 bit micro processor. This IC is able to control
maximum 20 pieces of Hitachi 64 Mega bit Flash Memory HN29W6411A and maximum 2 pieces of Hitachi
TM
84 Mega bit Flash Memory HN29W8411, and is used to build Flash ATA Card and CompactFlash .
Features
• Comform to PC-ATA Card and CompactFlash
TM
specification standard
• Control maximum 20 pieces of Hitachi 64 Mega bit Flash memory HN29W6411A and maximum 2 pieces
of Hitachi 84 Mega bit Flash Memory HN29W8411
• Operate by 3.3V or 5V single power supply
• Support card density up to 160/20 Mega bytes
• Execute internal self-diagnostic program at VCC power on
• Operate in 3 modes
 Memory Card Mode
 I/O Card Mode
 True-IDE Mode
• Assure a high reliability based on the internal ECC (Error Correcting Code) function
• Support Auto Sleep Mode
• Support interleave operation in 2 bank organization
Note:
TM
CompactFlash is a trademark of SanDisk Corporation and is licensed royalty-free to the CFA which
in turn will license it royalty-free to CFA members.
TM
*CFA: CompactFlash Association.
This Material Copyrighted by Its Respective Manufacturer
HN29W6484AH03TE-1
Pin Assignment
NO.
Controller
Memory card mode
I/O card mode
Signal name
Signal name
I/O
True IDE mode
I/O
Signal name
I/O
Remarks*
1
1
H_A(2)
A2
I
A2
I
A2
I
PC3B43C
2
H_INPACK_
–INPACK
O
–INPACK
O
–INPACK
O
PC3BI3C
3
H_REG_
–REG
I
–REG
I
–REG
I
PC3B63VC
4
DASP_
BVD2
I/O
–SPKR
I/O
–DASP
I/O
PC3B43VC
5
H_STSCHG_
BVD1
I/O
–STSCHG
I/O
–PDIAG
I/O
PC3B43VC
6
H_A(1)
A1
I
A1
I
A1
I
PC3B43C
7
H_A(0)
A0
I
A0
I
A0
I
PC3B43C
8
GND
GND
—
GND
—
GND
—
PV0A
9
H_D(0)
D0
I/O
D0
I/O
D0
I/O
PC3BH3CX
10
H_D(1)
D1
I/O
D1
I/O
D1
I/O
PC3BH3CX
11
H_D(2)
D2
I/O
D2
I/O
D2
I/O
PC3BH3CX
12
H_IOIS16_
WP
O
–IOIS16
O
–IOIS16
O
PC3N03C
13
H_D(8)
D8
I/O
D8
I/O
D8
I/O
PC3BH3CX
14
H_D(9)
D9
I/O
D9
I/O
D9
I/O
PC3BH3CX
15
H_D(10)
D10
I/O
D10
I/O
D10
I/O
PC3BH3CX
16
VCC
VCC
—
VCC
—
VCC
—
PV3I
17
TEST4
—
O
—
O
—
O
PC3BI3C
18
PORST_
PORST_
I
PORST_
I
PORST_
I
PC3B63C
19
TEST1
—
I
—
I
—
I
PC3B63C
20
TEST2
—
I
—
I
—
I
PC3D21
21
GND
GND
—
GND
—
GND
—
PV0I
22
XIN
XIN
I
XIN
I
XIN
I
PC3X11H
23
XOUT
XOUT
O
XOUT
O
XOUT
O
PC3X11OH
24
GND
GND
—
GND
—
GND
—
PV0A
25
VCC
VCC
—
VCC
—
VCC
—
PV3A
26
F_WEB_
F_WEB_
O
F_WEB_
O
F_WEB_
O
PC3B43C
27
F_SC_B1
F_SC_B1
O
F_SC_B1
O
F_SC_B1
O
PC3B43C
28
F_SC_B2
F_SC_B2
O
F_SC_B2
O
F_SC_B2
O
PC3B43C
29
F_DB(7)
F_DB(7)
I/O
F_DB(7)
I/O
F_DB(7)
I/O
PC3B42UX
30
F_DB(6)
F_DB(6)
I/O
F_DB(6)
I/O
F_DB(6)
I/O
PC3B42UX
2 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Pin Assignment (cont.)
Memory card mode
I/O card mode
True IDE mode
1
NO.
Controller
Signal name
I/O
Signal name
I/O
Signal name
I/O
Remarks*
31
F_DB(5)
F_DB(5)
I/O
F_DB(5)
I/O
F_DB(5)
I/O
PC3B42UX
32
F_DB(4)
F_DB(4)
I/O
F_DB(4)
I/O
F_DB(4)
I/O
PC3B42UX
33
F_DB(3)
F_DB(3)
I/O
F_DB(3)
I/O
F_DB(3)
I/O
PC3B42UX
34
GND
GND
—
GND
—
GND
—
PV0A
35
F_DB(2)
F_DB(2)
I/O
F_DB(2)
I/O
F_DB(2)
I/O
PC3B42UX
36
F_DB(1)
F_DB(1)
I/O
F_DB(1)
I/O
F_DB(1)
I/O
PC3B42UX
37
F_DB(0)
F_DB(0)
I/O
F_DB(0)
I/O
F_DB(0)
I/O
PC3B42UX
38
F_OEB_
F_OEB_
O
F_OEB_
O
F_OEB_
O
PC3B42C
39
F_CDEB_
F_CDEB_
O
F_CDEB_
O
F_CDEB_
O
PC3B42C
40
F_RDY_2
F_RDY_2
I
F_RDY_2
I
F_RDY_2
I
PC3B63UC
41
F_RES_
F_RES_
O
F_RES_
O
F_RES_
O
PC3O03C
42
F_CEB_1
F_CEB_1
O
F_CEB_1
O
F_CEB_1
O
PC3B43C
43
F_CEB_2
F_CEB_2
O
F_CEB_2
O
F_CEB_2
O
PC3B43C
44
F_CEB_3
F_CEB_3
O
F_CEB_3
O
F_CEB_3
O
PC3B43C
45
TEST3
—
I
—
I
—
I
@
46
VCC
VCC
—
VCC
—
VCC
—
PV3I
47
TEST5
—
I/O
—
I/O
—
I/O
PC3B63UC
48
GND
GND
—
GND
—
GND
—
PV0A
49
F_CEB_4
F_CEB_4
O
F_CEB_4
O
F_CEB_4
O
PC3B43C
50
F_CEB_5
F_CEB_5
O
F_CEB_5
O
F_CEB_5
O
PC3B43C
51
GND
GND
—
GND
—
GND
—
PV0I
52
F_CEB_6
F_CEB_6
O
F_CEB_6
O
F_CEB_6
O
PC3B43C
53
F_CEB_7
F_CEB_7
O
F_CEB_7
O
F_CEB_7
O
PC3B43C
54
F_CEB_8
F_CEB_8
O
F_CEB_8
O
F_CEB_8
O
PC3B43C
55
F_CEB_9
F_CEB_9
O
F_CEB_9
O
F_CEB_9
O
PC3B43C
56
F_CEB_10
F_CEB_10
O
F_CEB_10
O
F_CEB_10
O
PC3B43C
57
F_CEA_1
F_CEA_1
O
F_CEA_1
O
F_CEA_1
O
PC3BH3UC
58
F_CEA_2
F_CEA_2
O
F_CEA_2
O
F_CEA_2
O
PC3BH3UC
59
VCC
VCC
—
VCC
—
VCC
—
PV3A
60
F_SC_A1
F_SC_A1
O
F_SC_A1
O
F_SC_A1
O
PC3B43C
This Material Copyrighted by Its Respective Manufacturer
3
HN29W6484AH03TE-1
Pin Assignment (cont.)
Memory card mode
I/O card mode
True IDE mode
1
NO.
Controller
Signal name
I/O
Signal name
I/O
Signal name
I/O
Remarks*
61
F_SC_A2
F_SC_A2
O
F_SC_A2
O
F_SC_A2
O
PC3B43C
62
GND
GND
—
GND
—
GND
—
PV0A
63
F_CEA_3
F_CEA_3
O
F_CEA_3
O
F_CEA_3
O
PC3BH3UC
64
F_CEA_4
F_CEA_4
O
F_CEA_4
O
F_CEA_4
O
PC3BH3UC
65
F_CEA_5
F_CEA_5
O
F_CEA_5
O
F_CEA_5
O
PC3BH3UC
66
F_CEA_6
F_CEA_6
O
F_CEA_6
O
F_CEA_6
O
PC3BH3UC
67
F_CEA_7
F_CEA_7
O
F_CEA_7
O
F_CEA_7
O
PC3BH3UC
68
F_CEA_8
F_CEA_8
O
F_CEA_8
O
F_CEA_8
O
PC3BH3UC
69
GND
GND
—
GND
—
GND
—
PV0I
70
F_CEA_9
F_CEA_9
O
F_CEA_9
O
F_CEA_9
O
PC3BH3UC
71
F_CEA_10
F_CEA_10
O
F_CEA_10
O
F_CEA_10
O
PC3BH3UC
72
F_WEA_
F_WEA_
O
F_WEA_
O
F_WEA_
O
PC3B43UC
73
F_DA(7)
F_DA(7)
I/O
F_DA(7)
I/O
F_DA(7)
I/O
PC3B42UX
74
F_DA(6)
F_DA(6)
I/O
F_DA(6)
I/O
F_DA(6)
I/O
PC3B42UX
75
F_DA(5)
F_DA(5)
I/O
F_DA(5)
I/O
F_DA(5)
I/O
PC3B42UX
76
VCC
VCC
—
VCC
—
VCC
—
PV3A
77
F_DA(4)
F_DA(4)
I/O
F_DA(4)
I/O
F_DA(4)
I/O
PC3B42UX
78
F_DA(3)
F_DA(3)
I/O
F_DA(3)
I/O
F_DA(3)
I/O
PC3B42UX
79
F_DA(2)
F_DA(2)
I/O
F_DA(2)
I/O
F_DA(2)
I/O
PC3B42UX
80
F_DA(1)
F_DA(1)
I/O
F_DA(1)
I/O
F_DA(1)
I/O
PC3B42UX
81
GND
GND
—
GND
—
GND
—
PV0A
82
F_DA(0)
F_DA(0)
I/O
F_DA(0)
I/O
F_DA(0)
I/O
PC3B42UX
83
F_OEA_
F_OEA_
I/O
F_OEA_
I/O
F_OEA_
I/O
PC3B42UC
84
F_CDEA_
F_CDEA_
I/O
F_CDEA_
I/O
F_CDEA_
I/O
PC3B42UC
85
F_RDY_1
F_RDY_1
I
F_RDY_1
I
F_RDY_1
I
PC3B63UC
86
TEST6
—
O
—
O
—
O
PC3BI3C
87
VCC
VCC
—
VCC
—
VCC
—
PV3I
88
GND
GND
—
GND
—
GND
—
PV0A
89
H_D(3)
D3
I/O
D3
I/O
D3
I/O
PC3BH3CX
90
H_D(4)
D4
I/O
D4
I/O
D4
I/O
PC3BH3CX
4 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Pin Assignment (cont.)
Memory card mode
I/O card mode
True IDE mode
1
NO.
Controller
Signal name
I/O
Signal name
I/O
Signal name
I/O
Remarks*
91
H_D(5)
D5
I/O
D5
I/O
D5
I/O
PC3BH3CX
92
H_D(6)
D6
I/O
D6
I/O
D6
I/O
PC3BH3CX
93
H_D(11)
D11
I/O
D11
I/O
D11
I/O
PC3BH3CX
94
H_D(12)
D12
I/O
D12
I/O
D12
I/O
PC3BH3CX
95
H_D(13)
D13
I/O
D13
I/O
D13
I/O
PC3BH3CX
96
GND
GND
—
GND
—
GND
—
PV0A
97
H_D(14)
D14
I/O
D14
I/O
D14
I/O
PC3BH3CX
98
H_D(7)
D7
I/O
D7
I/O
D7
I/O
PC3BH3CX
99
H_CE1_
–CE1
I
–CE1
I
–CE1
I
PC3B63VC
100
H_A(10)
A10
I
A10
I
A10
I
PC3B43C
101
H_OE_
–OE
I
–OE
I
–ATASEL
I
PC3B63C
102
H_D(15)
D15
I/O
D15
I
D15
I
PC3BH3CX
103
H_CE2_
–CE2
I
–CE2
I
–CE2
I
PC3B63VC
104
H_IORD_
–IORD
I
–IORD
I
–IORD
I
PC3B63VC
105
H_IOWR_
–IOWR
I
–IOWR
I
–IOWR
I
PC3B63VC
106
VCC
VCC
—
VCC
—
VCC
—
PV3A
107
H_A(9)
A9
I
A9
I
A9
I
PC3B43C
108
H_A(8)
A8
I
A8
I
A8
I
PC3B43C
109
H_A(7)
A7
I
A7
I
A7
I
PC3B43C
110
H_A(6)
A6
I
A6
I
A6
I
PC3B43C
111
GND
GND
I
GND
I
GND
I
PV0A
112
H_WE_
–WE
I
–WE
I
–WE
I
PC3B63VC
113
H_IREQ_
RDY/–BSY
O
–IREQ
O
INTRQ
O
PC3BI3C
114
CSEL_
–CSEL
I
–CSEL
I
–CSEL
I
PT3B43VC
115
TEST7
—
O
—
O
—
O
@
116
H_RESET
RESET
I
RESET
I
–RESET
I
PT3B43C
117
H_WAIT_
–WAIT
O
–WAIT
O
IORDY
O
PC3BI3C
118
H_A(5)
A5
I
A5
I
A5
I
PC3B43C
119
H_A(4)
A4
I
A4
I
A4
I
PC3B43C
120
H_A(3)
A3
I
A3
I
A3
I
PC3B43C
This Material Copyrighted by Its Respective Manufacturer
5
HN29W6484AH03TE-1
Note:
1. Type of input/output buffer
PC3B42C
: CMOS level 3-state input/output (2 mA)
PC3B42UC : CMOS level 3-state input/output with pull-up resister (2 mA)
PC3B42UX : CMOS level 3-state input/output with pull-up resister (1 mA/2 mA)
PC3B43C
: CMOS level 3-state input/output (3 mA)
PC3B43UC : CMOS level 3-state input/output with pull-up resister (3 mA)
PC3B43VC : CMOS level 3-state input/output with pull-up resister 100 kΩ (3 mA)
PC3B63C
: CMOS level 3-state input/output with schmitt input (3 mA)
PC3B63UC : CMOS level 3-state input/output with schmitt input, pull-up resister (3 mA)
PC3B63VC : CMOS level 3-state input/output with schmitt input, pull-up resister 100 kΩ (3 mA)
PC3BH3CX : CMOS level 3-state input/output with active-LOW input enable (2 mA/3 mA)
PC3BH3UC : CMOS level 3-state input/output with active-LOW input enable and pull-up resister
(3 mA)
PC3BI3C
: CMOS level 3-state input/output with 3-state input enable (3 mA)
PC3D21
: CMOS level schmitt input only
PC3N03C
: Open drain output (3 mA)
PC3O03C
: Topempole output (3 mA)
PC3X11H
: Crystal OSC input
PC3X11OH : Crystal OSC output
PT3B43C
: TTL level input/output (3 mA)
PT3B43VC : TTL level input/output with pull-up resister 100 kΩ (3 mA)
PV0A
: I/O GND
PV0I
: Core and I/O GND
PV3A
: I/O VCC
PV3I
: Core and I/O VCC
@
: TEST pin only
6 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Host Interface Pin Explanation
Signal name
Direction Pin No.
A10 to A0
I
(PC Card Memory mode)
Description
100, 107, 108,
109, 110, 118,
119, 120, 1, 6, 7
Address bus is A10 to A0. A10 is MSB and A0 is
LSB.
A2 to A0
(True IDE mode)
1, 6, 7
Address bus is A10 to A0. Only A2 to A0 are used,
the remaining address lines should be grounded by
the host.
BVD1
I/O
(PC Card Memory mode)
5
BVD1 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
A10 to A0
(PC Card I/O mode)
-STSCHG
(PC Card I/O mode)
-STSCHG is used for changing the status of
Configuration and status register in attribute area.
-PDIAG
(True IDE mode)
-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.
BVD2
I/O
(PC Card Memory mode)
4
BVD2 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-SPKR
(PC Card I/O mode)
-SPKR outputs speaker signals. This output line is
constantly driven to a high state since this product
does not support the audio function.
-DASP
(True IDE mode)
-DASP is the Disk Active/Slave Present signal in the
Master/Slave handshake protocol.
-CE1, -CE2
I
(PC Card Memory mode)
Card Enable
99, 103
-CE1 and -CE2 are low active card select signals.
Byte/Word/Odd byte mode are defined by
combination of -CE1, -CE2 and A0.
-CE1, -CE2
(PC Card I/O mode)
Card Enable
-CE1, -CE2
(True IDE mode)
This Material Copyrighted by Its Respective Manufacturer
-CE2 is used for select the Alternate Status Register
and the Device Control Register while -CE1 is the
chip select for the other task file registers.
7
HN29W6484AH03TE-1
Signal name
Direction Pin No.
-CSEL
I
(PC Card Memory mode)
114
Description
This signal is not used.
-CSEL
(PC Card I/O mode)
-CSEL
(True IDE mode)
D15 to D0
I/O
(PC Card Memory mode)
This signal is used to configure this device as a
Master or a Slave when configured in the True IDE
mode. When this pin is grounded, this device is
configured as a Master. When the pin is open, this
device is configured as a Slave.
102, 97, 95, 94,
93, 15, 14, 13,
98, 92, 91, 90,
89, 11, 10, 9
Data bus is D15 to D0. D0 is the LSB of the even byte
of the word. D8 is the LSB of the odd byte of the
word.
D15 to D0
(PC Card I/O mode)
D15 to D0
(True IDE mode)
GND
—
(PC Card Memory mode)
8, 21, 24, 34, 48, Ground
51, 62, 69, 81,
88, 96, 111
GND
(PC Card I/O mode)
GND
(True IDE mode)
-INPACK
O
(PC Card Memory mode)
2
This signal is not used and should not be connected
at the host.
-INPACK
(PC Card I/O mode)
Input Acknowledge
This signal is asserted low by this card when the card
is selected and responding to an I/O read cycle at the
address that is on the address bus during -CE and
-IORD are low. This signal is used for the input data
buffer control.
-INPACK
(True IDE mode)
This signal is not used and should not be connected
at the host.
-IORD
I
(PC Card Memory mode)
104
This signal is not used.
-IORD
(PC Card I/O mode)
-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until I/O
card interface setting up.
-IORD
(True IDE mode)
-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until True
IDE interface setting up.
8 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Signal name
Direction Pin No.
-IOWR
I
(PC Card Memory mode)
105
Description
This signal is not used.
-IOWR
(PC Card I/O mode)
-IOWR is used for control of data write in I/O task file
area. This card does not respond to -IOWR until I/O
card interface setting up.
-IOWR
(True IDE mode)
-IOWR is used for control of data write in I/O task file
area. This card does not respond to -IOWR until True
IDE interface setting up.
-OE
I
(PC Card Memory mode)
101
-OE is used for the control of reading register’s data in
attribute area or task file area.
-OE
(PC Card I/O mode)
-OE is used for the control of reading register’s data in
attribute area.
-ATASEL
(True IDE mode)
To enable True IDE mode this input should be
grounded by the host.
RDY/-BSY
O
(PC Card Memory mode)
113
The signal is RDY/-BSY pin. RDY/-BSY pin turns low
level during the card internal initialization operation at
VCC applied or reset applied, so next access to the
card should be after the signal turned high level.
-IREQ
(PC Card I/O mode)
This signal is active low -IREQ pin. The signal of low
level indicates that the card is requesting software
service to host, and high level indicates that the card
is not requesting.
INTRQ
(True IDE mode)
This signal is the active high Interrupt Request to the
host.
-REG
I
(PC Card Memory mode)
Attribute memory select
3
-REG is used during memory cycles to distinguish
between task file and attribute memory accesses.
High for task file, Low for attribute memory is
accessed.
-REG
(PC Card I/O mode)
-REG is constantly low when task file or attribute
memory is accessed.
-REG
(True IDE mode)
This input signal is not used and should be connected
to VCC.
This Material Copyrighted by Its Respective Manufacturer
9
HN29W6484AH03TE-1
Signal name
Direction Pin No.
RESET
I
(PC Card Memory mode)
116
Description
This signal is active high RESET pin. If this signal is
asserted high, the card internal initialization begins to
operate. During the card internal initialization
RDY/-BSY is low. After the card internal initialization
RDY/-BSY is high.
RESET
(PC Card I/O mode)
This signal is active high RESET pin. If this signal is
asserted high, the card internal initialization begins to
operate. In this mode, RDY/-BSY signal can not be
used, so using Status Register the Ready/Busy status
can be confirmed.
-RESET
(True IDE mode)
This signal is active low -RESET pin. If this signal is
asserted low, all the register’s in this card are reset.
In this mode, RDY/-BSY signal can not be used, so
using status register the Ready/Busy status can be
confirmed.
VCC
—
(PC Card Memory mode)
16, 25, 46, 59,
76, 87, 106
+5 V, +3.3 V power.
117
This signal is active low -WAIT pin. In this card this
signal is constantly high level.
VCC
(PC Card I/O mode)
VCC
(True IDE mode)
-WAIT
O
(PC Card Memory mode)
-WAIT
(PC Card I/O mode)
IORDY
(True IDE mode)
-WE
I
(PC Card Memory mode)
This output signal may be used as IORDY. In this
card this signal is constantly high impedance.
112
-WE is used for the control of writing register’s data in
attribute memory area or task file area.
-WE
(PC Card I/O mode)
-WE is used for the control of writing register’s data in
attribute memory area.
-WE
(True IDE mode)
This input signal is not used and should be connected
to VCC by the host.
WP
O
(PC Card Memory mode)
Write Protect
12
WP is held low because this card does not have write
protect switch.
-IOIS16
(PC Card I/O mode)
-IOIS16 is asserted when task file registers are
accessed in 16-bit mode.
-IOIS16
(True IDE mode)
This output signal is asserted low when this device is
expecting a word data transfer cycle. Initial mode is
16-bit. If the user issues a Set Feature Command to
put the device in Byte access mode, the card permits
8-bit accesses.
10 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Flash Memory Interface Pin Explanation
Signal name
Direction Pin No.
Description
F_DA7 to F_DA0,
F_DB7 to F_DB0
I/O
73, 74, 75, 77,
78, 79, 80, 82,
29, 30, 31, 32,
33, 35, 36, 37
The Flash bus is F_DA0 to F_DA7 and F_DB0 to
F_DB7. This bus is used as command, address and
data bus for Flash memory.
F_CEA10 to F_CEA1,
F_CEB10 to F_CEB1
O
71, 70, 68, 67,
66, 65, 64, 63,
58, 57, 56, 55,
54, 53, 52, 50,
49, 44, 43, 42
Flash chip enable is used to select the Flash memory.
F_OEA_, F_OEB_
O
83, 38
Flash output enable is used to control read data
output from the Flash memory.
F_RDY_1, F_RDY_2
I
85, 40
Flash ready/busy is driven low by Flash memory
during program or erase operation. Flash ready/busy
becomes high impedance at the completion of the
program or erase operation.
F_WEA_, F_WEB_
O
72, 26
Flash write enable is used to strobe command and
address. The command and address are latched at
the rising edge of the Flash write enable.
F_SC_A1, F_SC_A2,
F_SC_B1, F_SC_B2
O
60, 61, 27, 28
Serial clock is used to read memory data and to
strobe programming data. The programming data is
latched at the rising edge of the Serial clock.
F_CDEA_, F_CDEB_
O
84, 39
Command data enable is used to control the
multiplexed Flash bus when Flash write enable is
asserted. Command and data are latched when
Command data enable is low, and Address is latched
when Command data enable is high.
F_RES_
O
41
Flash reset must be kept at VILR(Vss ± 0.2V) while Vcc
is turned on and off to prevent Flash memory from
unintentional erase or programming. Flash reset must
be kept at VIHR(VCC ± 0.2V) after VCC becomes stable
and while Flash memory is in various operations such
as programming, erase and read.
Other Pin Explanation
Signal name
Direction Pin No.
Description
XIN, XOUT
I/O
22, 23
XIN and XOUT are used to connect crystal oscillator.
PORST_
I
18
This pin is used to connect reset IC for power on
reset.
TEST3 to TEST1
—
45, 20, 19
TEST1 to TEST3 are used for diagnostic test and
should be kept at Vcc.
TEST7 to TEST4
—
115, 86, 47, 17
TEST4 to TEST7 are used for diagnostic test and
should be open.
This Material Copyrighted by Its Respective Manufacturer
11
HN29W6484AH03TE-1
Card Block Diagram
Power on
reset
Reset IC
X'tal
20 MHz
PC card slot
Flash memory
Flash bus A
Controller
Flash memory
Flash bus B
Controller Block Diagram
PC card
slot
Reset IC
X'tal
Power on
Reset
Clock
Control
Host interface
CIS, CCR
Task register
H8 Micro processor
Data transfer
control
Flash Memory
interface
Data buffer
ECC Logic
Control/status
register
Flash memory
CIS: Card Information Structure
CCR: Card Configuration Register
ECC: Error Correcting Code
Note: The HITACHI Flash controller recover from 2-bit errors of the data field (512-byte) and 1-bit error of
control field (16-byte) during read operation.
12 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Host access specifications
1. Attribute access specifications
When CIS-ROM region or Configuration register region is accessed, read and write operations are executed
under the condition of -REG = "L" as follows. That region can be accessed by Byte/Word/Odd-byte modes
which are defined by PC card standard specifications.
Attribute Read Access Mode
Mode
-REG
-CE2
-CE1
A0
-OE
-WE
D8 to D15
D0 to D7
Standby mode
×
H
H
×
×
×
High-Z
High-Z
Byte access (8-bit)
L
H
L
L
L
H
High-Z
even byte
L
H
L
H
L
H
High-Z
invalid
Word access (16-bit)
L
L
L
×
L
H
invalid
even byte
Odd byte access (8-bit)
L
L
H
×
L
H
invalid
High-Z
Note: ×: L or H
Attribute Write Access Mode
Mode
-REG
-CE2
-CE1
A0
-OE
-WE
D8 to D15
D0 to D7
Standby mode
×
H
H
×
×
×
Don’t care
Don’t care
Byte access (8-bit)
L
H
L
L
H
L
Don’t care
even byte
L
H
L
H
H
L
Don’t care
Don’t care
Word access (16-bit)
L
L
L
×
H
L
Don’t care
even byte
Odd byte access (8-bit)
L
L
H
×
H
L
Don’t care
Don’t care
Note: ×: L or H
Attribute Access Timing Example
A0 to A10
-REG
-CE2/-CE1
-OE
-WE
D0 to D15
Din
Dout
read cycle
This Material Copyrighted by Its Respective Manufacturer
write cycle
13
HN29W6484AH03TE-1
2. Task File register access specifications
There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address
area. Each case of Task File register read and write operations are executed under the condition as follows. That area can
be accessed by Byte/Word/Odd Byte mode which are defined by PC card standard specifications.
(1) I/O address map
Task File Register Read Access Mode (1)
Mode
-REG -CE2
-CE1
A0
-IORD -IOWR -OE
-WE
D8 to D15 D0 to D7
Standby mode
×
H
H
×
×
×
×
×
High-Z
High-Z
Byte access (8-bit)
L
H
L
L
L
H
H
H
High-Z
even byte
L
H
L
H
L
H
H
H
High-Z
odd byte
L
L
L
×
L
H
H
H
odd byte
even byte
Odd byte access (8-bit) L
L
H
×
L
H
H
H
odd byte
High-Z
Word access (16-bit)
Note: ×: L or H
Task File Register Write Access Mode (1)
Mode
-REG -CE2
-CE1
A0
-IORD -IOWR -OE
-WE
D8 to D15 D0 to D7
Standby mode
×
H
H
×
×
×
×
×
Don’t care Don’t care
Byte access (8-bit)
L
H
L
L
H
L
H
H
Don’t care even byte
L
H
L
H
H
L
H
H
Don’t care odd byte
L
L
L
×
H
L
H
H
odd byte
even byte
Odd byte access (8-bit) L
L
H
×
H
L
H
H
odd byte
Don’t care
Word access (16-bit)
Note: ×: L or H
Task File Register Access Timing Example (1)
A0 to A10
-REG
-CE2/-CE1
-IORD
- IOWR
D0 to D15
Din
Dout
read cycle
14 Material Copyrighted by Its Respective Manufacturer
This
write cycle
HN29W6484AH03TE-1
(2) Memory address map
Task File Register Read Access Mode (2)
Mode
-REG -CE2
-CE1
A0
-OE
-WE
-IORD -IOWR D8 to D15 D0 to D7
Standby mode
×
H
H
×
×
×
×
×
High-Z
High-Z
Byte access (8-bit)
H
H
L
L
L
H
H
H
High-Z
even byte
H
H
L
H
L
H
H
H
High-Z
odd byte
H
L
L
×
L
H
H
H
odd byte
even byte
Odd byte access (8-bit) H
L
H
×
L
H
H
H
odd byte
High-Z
Word access (16-bit)
Note: ×: L or H
Task File Register Write Access Mode (2)
Mode
-REG -CE2
-CE1
A0
-OE
-WE
-IORD -IOWR D8 to D15 D0 to D7
Standby mode
×
H
H
×
×
×
×
×
Don’t care Don’t care
Byte access (8-bit)
H
H
L
L
H
L
H
H
Don’t care even byte
H
H
L
H
H
L
H
H
Don’t care odd byte
H
L
L
×
H
L
H
H
odd byte
even byte
Odd byte access (8-bit) H
L
H
×
H
L
H
H
odd byte
Don’t care
Word access (16-bit)
Note: ×: L or H
Task File Register Access Timing Example (2)
A0 to A10
-REG
-CE2/-CE1
-OE
-WE
D0 to D15
Dout
read cycle
This Material Copyrighted by Its Respective Manufacturer
Din
write cycle
15
HN29W6484AH03TE-1
3. True IDE Mode
The card can be configured in a True IDE mode of operation. This card is configured in this mode only when the -OE
input signal is asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host.
Only I/O operation to the task file and data register are allowed. If this card is configured during power on
sequence, data register are accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set Feature
Command to put the device in 8-bit mode.
True IDE Mode Read I/O Function
Mode
-CE2
-CE1
A0 to A2 -IORD
-IOWR
D8 to D15 D0 to D7
Invalid mode
L
L
×
×
×
High-Z
High-Z
Standby mode
H
H
×
×
×
High-Z
High-Z
Data register access
H
L
0
L
H
odd byte
even byte
Alternate status access
L
H
6H
L
H
High-Z
status out
Other task file access
H
L
1-7H
L
H
High-Z
data
Note: ×: L or H
True IDE Mode Write I/O Function
Mode
-CE2
-CE1
A0 to A2 -IORD
-IOWR
D8 to D15 D0 to D7
Invalid mode
L
L
×
×
×
don’t care
don’t care
Standby mode
H
H
×
×
×
don’t care
don’t care
Data register access
H
L
0
H
L
odd byte
even byte
Control register access
L
H
6H
H
L
don’t care
control in
Other task file access
H
L
1-7H
H
L
don’t care
data
Note: ×: L or H
True IDE Mode I/O Access Timing Example
A0 to A2
-CE
-IORD
-IOWR
-IOIS16
D0 to D15
Dout
read cycle
16 Material Copyrighted by Its Respective Manufacturer
This
Din
write cycle
HN29W6484AH03TE-1
Configuration register specifications
This card supports four Configuration registers for the purpose of the configuration and observation of this
card. These registers can be used in memory card mode and I/O card mode. In True IDE mode, these
registers can not be used.
1. Configuration Option register (Address 200H)
This register is used for the configuration of the card configuration status and for the issuing soft reset to the
card.
bit7
bit6
bit5
SRESET
LevlREQ
INDEX
bit4
bit3
bit2
bit1
bit0
Note: initial value: 00H
Name
R/W
Function
SRESET
(HOST->)
R/W
Setting this bit to "1", places the card in the reset state (Card Hard Reset). This
operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to "0",
places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) .
Card configuration status is reset and the card internal initialized operation starts when
Card Hard Reset is executed, so next access to the card should be the same sequence
as the power on sequence.
LevlREQ
(HOST->)
R/W
This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode
interrupt is selected.
INDEX
(HOST->)
R/W
This bits is used for select operation mode of the card as follows.
When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose
of Memory card interface recognition.
INDEX bit assignment
INDEX bit
5
4
3
2
1
0
Card mode
Task File register address
Mapping mode
0
0
0
0
0
0
Memory card
0H to FH, 400H to 7FFH
memory mapped
0
0
0
0
0
1
I/O card
xx0H to xxFH
contiguous I/O mapped
0
0
0
0
1
0
I/O card
1F0H to 1F7H, 3F6H to 3F7H
primary I/O mapped
0
0
0
0
1
1
I/O card
170H to 177H, 376H to 377H
secondary I/O mapped
This Material Copyrighted by Its Respective Manufacturer
17
HN29W6484AH03TE-1
2. Configuration and Status register (Address 202H)
This register is used for observing the card state.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CHGED
SIGCHG
IOIS8
0
0
PWD
INTR
0
Note: initial value: 00H
Name
R/W
Function
CHGED
(CARD->)
R
This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to "1". When
CHGED bit is set to "1", -STSCHG pin is held "L" at the condition of SIGCHG bit set to
"1" and the card configured for the I/O interface.
SIGCHG
(HOST->)
R/W
This bit is set or reset by the host for enabling and disabling the status-change signal (STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept
"H".
IOIS8
(HOST->)
R/W
The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus
(D7 to D0).
PWD
(HOST->)
R/W
When this bit is set to "1", the card enters sleep state (Power Down mode). When this
bit is reset to "0", the card transfers to idle state (active mode). RRDY/-BSY bit on Pin
Replacement Register becomes BUSY when this bit is changed. RRDY/-BSY will not
become Ready until the power state requested has been entered. This card
automatically powers down when it is idle, and powers back up when it receives a
command.
INTR
(CARD->)
R
This bit indicates the internal state of the interrupt request. This bit state is available
whether I/O card interface has been configured or not. This signal remains true until
the condition which caused the interrupt request has been serviced. If interrupts are
disabled by the -IEN bit in the Device Control Register, this bit is a zero.
18 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
3. Pin Replacement register (Address 204H)
This register is used for providing the signal state of -IREQ signal when the card configured I/O card interface.
bit7
bit6
bit5
bit4
0
0
CRDY/-BSY 0
bit3
bit2
bit1
bit0
1
1
RRDY/-BSY 0
Note: initial value: 0CH
Name
R/W
Function
CRDY/-BSY R/W
(HOST->)
This bit is set to "1" when the RRDY/-BSY bit changes state. This bit may also be
written by the host.
RRDY/-BSY R/W
(HOST->)
When read, this bit indicates +READY pin states. When written, this bit is used for
CRDY/-BSY bit masking.
4. Socket and Copy register (Address 206H)
This register is used for identification of the card from the other cards. Host can read and write this register.
This register should be set by host before this card’s Configuration Option register set.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
DRV#
0
0
0
0
Note: initial value: 00H
Name
R/W
Function
DRV#
(HOST->)
R/W
This fields are used for the configuration of the plural cards. When host configures the
plural cards, written the card’s copy number in this field. In this way, host can perform
the card’s master/slave organization.
This Material Copyrighted by Its Respective Manufacturer
19
HN29W6484AH03TE-1
CIS informations
After the assembled Flash card, CIS information should be programmed into the Flash. For example, CIS
information of HITACHI’s Flash card is defined as follows.
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
000H
01H CISTPL_DEVICE
Device info tuple
Tuple code
002H
04H TPL_LINK
Link length is 4 byte
Link to next tuple
004H
DFH Device type
006H
4AH EXT Speed
mantissa
Speed
exponent
400 ns if no wait
Extended speed
008H
01H 1x
2k units
2k byte of address space
Device size
W Device speed Device type = DH: I/O device Device type, WPS, speed
P
WPS = 1: No WP
S
Device speed = 7: ext speed
00AH
FFH List end marker
End of device
END marker
00CH
1CH CISTPL_DEVICE_OC
Other conditions device info
tuple
Tuple code
00EH
04H TPL_LINK
Link length is 4 bytes
Link to next tuple
010H
02H EXT Reserved
012H
D9H Device type
014H
01H 1x
016H
018H
VCC
MWAIT 3 V, wait is not used
Other conditions info field
W Device speed Device type = DH: I/O device Device type, WPS, speed
P
WPS = 1: No WP
S
Device speed = 1: 250 ns
2k units
2k byte of address space
Device size
FFH List end marker
End of device
END marker
18H CISTPL_JEDEC_C
JEDEC ID common memory
Tuple code
01AH
02H TPL_LINK
Link length is 2 bytes
Link to next tuple
01CH
DFH PCMCIA’s manufacturer’s JEDEC Manufacturer’s ID code
ID code
JEDEC ID of PC Card ATA
01EH
01H PCMCIA JEDEC device code
2nd byte of JEDEC ID
020H
20H CISTPL_MANFID
Manufacturer’s ID code
Tuple code
022H
04H TPL_LINK
Link length is 4 bytes
Link to next tuple
024H
07H Low byte of PCMCIA
manufacturer’s code
HITACHI JEDEC
manufacturer’s ID
Low byte of manufacturer’s
ID code
026H
00H High byte of PCMCIA
manufacturer’s code
Code of 0 because other byte High byte of manufacturer’s
is JEDEC 1 byte
ID code
manufacture’s ID
028H
00H Low byte of product code
HITACHI code for PC CARD Low byte of product code
ATA
02AH
00H High byte of product code
High byte of product code
20 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Address Data 7
Description of contents
CIS function
02CH
15H CISTPL_VERS_1
6
5
4
3
2
1
0
Level 1 version/product info
Tuple code
02EH
15H TPL_LINK
Link length is 15h bytes
Link to next tuple
030H
04H TPPLV1_MAJOR
PCMCIA2.0/JEIDA4.1
Major version
032H
01H TPPLV1_MINOR
PCMCIA2.0/JEIDA4.1
Minor version
034H
48H
‘H’
Info string 1
036H
49H
‘I’
038H
54H
‘T’
03AH
41H
‘A’
03CH
43H
‘C’
03EH
48H
‘H’
040H
49H
‘I’
042H
00H
Null terminator
044H
46H
‘F’
046H
4CH
‘L’
048H
41H
‘A’
04AH
53H
‘S’
04CH
48H
‘H’
04EH
00H
Null terminator
050H
34H
‘4’
052H
2EH
‘.’
Info string 2
Vender specific strings
054H
30H
‘0’
056H
00H
Null terminator
058H
FFH List end marker
End of device
END marker
05AH
21H
Function ID tuple
Tuple code
05CH
02H TPL_LINK
Link length is 2 bytes
Link to next tuple
05EH
04H
Disk function, may be silicon, PC card function code
may be removable
060H
01H Reserved
CISTPL_FUNCID
TPLFID_FUNCTION = 04H
R P
This Material Copyrighted by Its Respective Manufacturer
R = 0: No BIOS ROM
P = 1: Configure card at
power on
System initialization byte
21
HN29W6484AH03TE-1
Address Data 7
6
5
4
3
2
1
0
CISTPL_FUNCE
Description of contents
CIS function
Function extension tuple
Tuple code
Link length is 2 bytes
Link to next tuple
062H
22H
064H
02H TPL_LINK
066H
01H Disk function extension tuple type Disk interface type
Extension tuple type for disk
068H
01H Disk interface type
PC card ATA interface
Interface type
06AH
22H
Function extension tuple
Tuple code
06CH
03H TPL_LINK
06EH
02H Disk function extension tuple type Single drive
Extension tuple type for disk
070H
0CH Reserved
Basic ATA option
parameters byte 1
072H
0FH R
074H
1AH CISTPL_CONFIG
Configuration tuple
Tuple code
076H
05H TPL_LINK
Link length is 5 bytes
Link to next tuple
078H
01H RFS
07AH
03H TPCC_LAST
Entry with config index of
03H is final entry in table
Last entry of config registers
07CH
00H TPCC_RADR (LSB)
Configuration registers are
located at 200H in REG
space
Location of config registers
I: Configuration index
C: Configuration and status
P: Pin replacement
S: Socket and copy
Configuration registers
present mask
TPCC_RMSK
CISTPL_FUNCE
I
Link length is 3 bytes
D U S V
E N P3 P2 P1 P0
RMS
RAS
07EH
02H TPCC_RADR (MSB)
080H
0FH Reserved
S P C I
22 Material Copyrighted by Its Respective Manufacturer
This
No VPP, silicon, single drive
V = 0: No VPP required
S = 1: Silicon
U = 1: Unique serial #
D = 0: Single drive on card
Link to next tuple
P0: Sleep mode supported Basic ATA option
P1: Standby mode
parameters byte 2
supported
P2: Idle mode suppported
P3: Drive auto power control
N: Some config excludes
3X7
E: Index bit is emulated
I: Twin IOIS16# data reg
only
R: Reserved
RFS: Reserved
Size of fields byte TPCC_SZ
RMS: TPCC_RMSK size - 1 =
0
RAS: TPCC_RADR size - 1 = 1
1 byte register mask
2 byte config base address
HN29W6484AH03TE-1
Address Data 7
0
Description of contents
CIS function
082H
1BH CISTPL_CFTABLE_ENTRY
6
5
4
3
2
1
Configuration table entry
tuple
Tuple code
084H
08H TPL_LINK
Link length is 8 bytes
Link to next tuple
086H
C0H I
D Configuration index
Memory mapped I/O
configuration
I = 1: Interface byte follows
D = 1: Default entry
Configuration index = 0
Configuration table index
byte
TPCE_INDX
088H
40H W
R P B Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP used
B = 0: BVD1 and BVD2 not
used
IF type = 0: Memory
interface
Interface description field
TPCE_IF
08AH
A1H M
MS
M = 1: Misc info present
Feature selection byte
MS = 01: Memory space info TPCE_FS
single 2-byte length
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
08CH
01H R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
08EH
55H X
Mantissa
Nominal voltage = 5 V
090H
08H Length in 256 bytes pages (LSB)
092H
00H Length in 256 bytes pages (MSB)
094H
20H X
IR IO T P
Exponent
R P R A T
O
This Material Copyrighted by Its Respective Manufacturer
VCC nominal value
Length of memory space is 2 Memory space description
kB
structures (TPCE_MS)
X = 0: No more misc fields
Miscellaneous features field
R: Reserved
TPCE_MI
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
23
HN29W6484AH03TE-1
Address Data 7
0
Description of contents
CIS function
096H
1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
098H
06H TPL_LINK
Link length is 6 bytes
Link to next tuple
09AH
00H I
D Configuration index
Memory mapped I/O
configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 0
Configuration table index
byte
TPCE_INDX
09CH
01H
MS
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
09EH
21H R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0A0H
B5H X
Mantissa
Nominal voltage = 3.0 V
VCC nominal value
0A2H
1EH X
Extension
+0.3 V
Extension byte
0A4H
4DH X
Mantissa
M
6
5
4
3
2
1
IR IO T P
Exponent
Exponent
24 Material Copyrighted by Its Respective Manufacturer
This
Max average current over 10 Max. average current
msec is 45 mA
HN29W6484AH03TE-1
Address Data 7
0
Description of contents
CIS function
0A6H
1BH CISTPL_CFTABLE_ ENTRY
6
5
4
3
2
1
Configuration table entry
tuple
Tuple code
0A8H
0AH TPL_LINK
Link length is 10 bytes
Link to next tuple
0AAH
C1H I
D Configuration INDEX
Contiguous I/O mapped ATA Configuration table index
registers configuration
byte TPCE_INDX
I = 1: Interface byte follows
D = 1: Default entry
Configuration index = 1
0ACH
41H W
R P B Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
IF type = 1: I/O interface
0AEH
99H M
MS
M = 1: Misc info present
Feature selection byte
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: VCC only info
0B0H
01H R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
Nominal voltage = 5 V
IR IO T P
0B2H
55H X
Mantissa
0B4H
64H R
S E IO AddrLine
Exponent
0B6H
F0H S
P L
M V B I
Interface description field
TPCE_IF
VCC nominal value
S = 1: 16-bit hosts supported I/O space description field
E = 1: 8-bit hosts supported TPCE_IO
IO AddrLine: 4 lines decoded
N
This Material Copyrighted by Its Respective Manufacturer
S = 1: Share logic active
Interrupt request description
P = 1: Pulse mode IRQ
structure
supported
TPCE_IR
L = 1: Level mode IRQ
supported
M = 1: Bit mask of IRQs
present
V = 0: No vender unique IRQ
B = 0: No bus error IRQ
I = 0: No IO check IRQ
N = 0: No NMI
25
HN29W6484AH03TE-1
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0B8H
FFH IRQ IR IR IR IR IR IR IRQ0
7
Q Q Q Q Q Q
6 5 4 3 2 1
IRQ level to be routed 0 to 15 Mask extension byte 1
recommended
TPCE_IR
0BAH
FFH IRQ IR IR IR IR IR IR IRQ8
15 Q Q Q Q Q Q
14 13 12 11 10 9
Recommended routing to any Maskextension byte 2
“normal, maskable” IRQ.
TPCE_IR
0BCH
20H X
X = 0: Nomore misc fields
Miscellaneous features field
R: reserved
TPCE_MI
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
R P R A T
O
26 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Address Data 7
0
Description of contents
CIS function
0BEH
1BH CISTPL_CFTABLE_ENTRY
6
5
4
3
2
1
Configuration table entry
tuple
Tuple code
0C0H
06H TPL_LINK
Link length is 6 bytes
Link to next tuple
0C2H
01H I
D Configuration index
Contiguous I/O mapped ATA Configuration table index
registers configuration
byte
I = 0: No Interface byte
TPCE_INDX
D = 0: No Default entry
Configuration index = 1
0C4H
01H M
MS
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
0C6H
21H R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0C8H
B5H X
Mantissa
Nominal voltage = 3.0 V
VCC nominal value
0CAH
1EH X
Extension
+0.3 V
Extension byte
0CCH
4DH X
Mantissa
IR IO T P
Exponent
Exponent
This Material Copyrighted by Its Respective Manufacturer
Max average current over 10 Max. average current
msec is 45 mA
27
HN29W6484AH03TE-1
Address Data 7
0
Description of contents
CIS function
0CEH
1BH CISTPL_CFTABLE_ENTRY
6
5
4
3
2
1
Configuration table entry
tuple
Tuple code
0D0H
0FH TPL_LINK
Link length is 15 bytes
Link to next tuple
0D2H
C2H I
D Configuration INDEX
ATA primary I/O mapped
configuration
I = 1: Interface byte follows
D = 1: default entry follows
Configuration index = 2
Configuration table index
byte TPCE_INDX
0D4H
41H W
R P B Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
IF type = 1: I/O interface
Interface description field
TPCE_IF
0D6H
99H M
MS
M = 1: misc info present
Feature selection byte
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: VCC only info
0D8H
01H R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0DAH
55H X
Mantissa
Nominal voltage = 5 V
0DCH
EAH R
S E IO AddrLine
0DEH
61H LS
IR IO T P
AS
Exponent
N range
28 Material Copyrighted by Its Respective Manufacturer
This
VCC nominal value
R = 1: Range follows
I/O space description field
S = 1: 16-bit hosts supported TPCE_IO
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded
LS = 1: Size of lengths is 1 I/O range format description
byte
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1
HN29W6484AH03TE-1
Address Data 7
Description of contents
CIS function
0E0H
F0H
6
5
4
3
2
1st I/O base address (LSB)
1st I/O range address
0E2H
01H
1st I/O base address (MSB)
0E4H
07H
1st I/O length - 1
1st I/O range length
0E6H
F6H
2nd I/O base address (LSB)
2nd I/O range address
0E8H
03H
2nd I/O base address (MSB)
0EAH
01H
0ECH
EEH S
P L
0EEH
20H
R P R A T
O
X
1
0
M IRQ level
This Material Copyrighted by Its Respective Manufacturer
2nd I/O length - 1
2nd I/O range length
S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
L = 1: Level mode IRQ
supported
M = 0: Bit mask of IRQs
present
IRQ level is IRQ14
Interrupt request description
structure
TPCE_IR
X = 0: Nomore misc fields
Miscellaneous features field
R: reserved
TPCE_MI
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
29
HN29W6484AH03TE-1
Address Data 7
0
Description of contents
CIS function
0F0H
1BH CISTPL_CFTABLE_ENTRY
6
5
4
3
2
1
Configuration table entry
tuple
Tuple code
0F2H
06H TPL_LINK
Link length is 6 bytes
Link to next tuple
0F4H
02H I
D Configuration index
ATA primary I/O mapped
configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 2
Configuration table index
byte
TPCE_INDX
0F6H
01H M
MS
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
0F8H
21H R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0FAH
B5H X
Mantissa
Nominal voltage = 3.0 V
VCC nominal value
0FCH
1EH X
Extension
+0.3 V
Extension byte
0FEH
4DH X
Mantissa
IR IO T P
Exponent
Exponent
30 Material Copyrighted by Its Respective Manufacturer
This
Max average current over 10 Max. average current
msec is 45 mA
HN29W6484AH03TE-1
Address Data 7
0
Description of contents
CIS function
100H
1BH CISTPL_CFTABLE_ENTRY
6
5
4
3
2
1
Configuration table entry
tuple
Tuple code
102H
0FH TPL_LINK
Link length is 15 bytes
Link to next tuple
104H
C3H I
D Configuration INDEX
ATA secondary I/O mapped
configuration
I = 1: Interface byte follows
D = 1: default entry
Configuration index = 3
Configuration table index
byte TPCE_INDX
106H
41H W
R P B Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
IF type = 1: I/O interface
Interface description field
TPCE_IF
108H
99H M
MS
M = 1: misc info present
Feature selection byte
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: VCC only info
10AH
01H R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
10CH
55H X
Mantissa
Nominal voltage = 5 V
10EH
EAH R
S E IO AddrLine
110H
61H LS
IR IO T P
AS
Exponent
N range
This Material Copyrighted by Its Respective Manufacturer
VCC nominal value
R = 1: Range follows
I/O space description field
S = 1: 16-bit hosts supported TPCE_IO
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded
LS = 1: Size of lengths is 1 I/O range format description
byte
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1
31
HN29W6484AH03TE-1
Address Data 7
Description of contents
CIS function
112H
70H
6
5
4
3
2
1
0
1st I/O base address (LSB)
1st I/O range address
114H
01H
1st I/O base address (MSB)
116H
07H
1st I/O length - 1
1st I/O range length
118H
76H
2nd I/O base address (LSB)
2nd I/O range address
11AH
03H
2nd I/O base address (MSB)
11CH
01H
11EH
EEH S
P L
120H
20H X
R P R A T
O
M IRQ level
32 Material Copyrighted by Its Respective Manufacturer
This
2nd I/O length - 1
2nd I/O range length
S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
L = 1: Level mode IRQ
supported
M = 0: Bit mask of IRQs
present
IRQ level is IRQ14
Interrupt request description
structure
TPCE_IR
X = 0: Nomore misc fields
Miscellaneous features field
R: reserved
TPCE_MI
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
HN29W6484AH03TE-1
Address Data 7
0
Description of contents
CIS function
122H
1BH CISTPL_CFTABLE_ENTRY
6
5
4
3
2
1
Configuration table entry
tuple
Tuple code
124H
06H TPL_LINK
Link length is 6 bytes
Link to next tuple
126H
03H I
D Configuration index
ATA secondary I/O mapped
configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 3
Configuration table index
byte
TPCE_INDX
128H
01H M
MS
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
12AH
21H R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
12CH
B5H X
Mantissa
Nominal voltage = 3.0 V
VCC nominal value
12EH
1EH X
Extension
+0.3 V
Extension byte
130H
4DH X
Mantissa
132H
14H CISTPL_NO_LINK
No link control tuple
Tuple code
134H
00H
Link is 0 bytes
Link to next tuple
136H
FFH CISTPL_END
End of list tuple
Tuple code
IR IO T P
Exponent
Exponent
This Material Copyrighted by Its Respective Manufacturer
Max average current over 10 Max. average current
msec is 45 mA
33
HN29W6484AH03TE-1
Task File register specification
These registers are used for reading and writing the storage data in this card. These registers are mapped five
types by the configuration of INDEX in Configuration Option register. The decoded addresses are shown as
follows.
Memory map (INDEX = 0)
-REG A10
A9 to A4 A3
A2
A1
A0
Offset
-OE = L
-WE = L
1
0
×
0
0
0
0
0H
Data register
Data register
1
0
×
0
0
0
1
1H
Error register
Feature register
1
0
×
0
0
1
0
2H
Sector count register
Sector count register
1
0
×
0
0
1
1
3H
Sector number register Sector number register
1
0
×
0
1
0
0
4H
Cylinder low register
Cylinder low register
1
0
×
0
1
0
1
5H
Cylinder high register
Cylinder high register
1
0
×
0
1
1
0
6H
Drive head register
Drive head register
1
0
×
0
1
1
1
7H
Status register
Command register
1
0
×
1
0
0
0
8H
Dup. even data register Dup. even data register
1
0
×
1
0
0
1
9H
Dup. odd data register
Dup. odd data register
1
0
×
1
1
0
1
DH
Dup. error register
Dup. feature register
1
0
×
1
1
1
0
EH
Alt. status register
Device control register
1
0
×
1
1
1
1
FH
Drive address register
Reserved
1
1
×
×
×
×
0
8H
Even data register
Even data register
1
1
×
×
×
×
1
9H
Odd data register
Odd data register
34 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Contiguous I/O map (INDEX = 1)
-REG A10 to A4 A3
A2
A1
A0
Offset
-IORD = L
-IOWR = L
0
×
0
0
0
0
0H
Data register
Data register
0
×
0
0
0
1
1H
Error register
Feature register
0
×
0
0
1
0
2H
Sector count register
Sector count register
0
×
0
0
1
1
3H
Sector number register
Sector number register
0
×
0
1
0
0
4H
Cylinder low register
Cylinder low register
0
×
0
1
0
1
5H
Cylinder high register
Cylinder high register
0
×
0
1
1
0
6H
Drive head register
Drive head register
0
×
0
1
1
1
7H
Status register
Command register
0
×
1
0
0
0
8H
Dup. even data register Dup. even data register
0
×
1
0
0
1
9H
Dup. odd data register
Dup. odd data register
0
×
1
1
0
1
DH
Dup. error register
Dup. feature register
0
×
1
1
1
0
EH
Alt. status register
Device control register
0
×
1
1
1
1
FH
Drive address register
Reserved
A9 to A4 A3
A2
A1
A0
-IORD = L
-IOWR = L
Data register
Primary I/O map (INDEX = 2)
-REG A10
0
×
1FH
0
0
0
0
Data register
0
×
1FH
0
0
0
1
Error register
Feature register
0
×
1FH
0
0
1
0
Sector count register
Sector count register
0
×
1FH
0
0
1
1
Sector number register
Sector number register
0
×
1FH
0
1
0
0
Cylinder low register
Cylinder low register
0
×
1FH
0
1
0
1
Cylinder high register
Cylinder high register
0
×
1FH
0
1
1
0
Drive head register
Drive head register
0
×
1FH
0
1
1
1
Status register
Command register
0
×
3FH
0
1
1
0
Alt. status register
Device control register
0
×
3FH
0
1
1
1
Drive address register
Reserved
This Material Copyrighted by Its Respective Manufacturer
35
HN29W6484AH03TE-1
Secondary I/O map (INDEX = 3)
-REG A10
A9 to A4 A3
A2
A1
A0
-IORD = L
-IOWR = L
0
×
17H
0
0
0
0
Data register
Data register
0
×
17H
0
0
0
1
Error register
Feature register
0
×
17H
0
0
1
0
Sector count register
Sector count register
0
×
17H
0
0
1
1
Sector number register
Sector number register
0
×
17H
0
1
0
0
Cylinder low register
Cylinder low register
0
×
17H
0
1
0
1
Cylinder high register
Cylinder high register
0
×
17H
0
1
1
0
Drive head register
Drive head register
0
×
17H
0
1
1
1
Status register
Command register
0
×
37H
0
1
1
0
Alt. status register
Device control register
0
×
37H
0
1
1
1
Drive address register
Reserved
True IDE Mode I/O map
-CE2
-CE1
A2
A1
A0
-IORD = L
-IOWR = L
1
0
0
0
0
Data register
Data register
1
0
0
0
1
Error register
Feature register
1
0
0
1
0
Sector count register
Sector count register
1
0
0
1
1
Sector number register
Sector number register
1
0
1
0
0
Cylinder low register
Cylinder low register
1
0
1
0
1
Cylinder high register
Cylinder high register
1
0
1
1
0
Drive head register
Drive head register
1
0
1
1
1
Status register
Command register
0
1
1
1
0
Alt. status register
Device control register
0
1
1
1
1
Drive address register
Reserved
36 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
1. Data register: This register is a 16-bit register that has read/write ability, and it is used for transferring 1
sector data between the card and the host. This register can be accessed in word mode and byte mode. This
register overlaps the Error or Feature register.
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D0 to D15
2. Error register: This register is a read only register, and it is used for analyzing the error content at the card
accessing. This register is valid when the BSY bit in Status register and Alternate Status register are set to
"0" (Ready).
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BBK
UNC
“0”
IDNF
“0”
ABRT
“0”
AMNF
bit
Name
Function
7
BBK (Bad BlocK detected)
This bit is set when a Bad Block is detected in requested ID field.
6
UNC (Data ECC error)
This bit is set when Uncorrectable error is occurred at reading the
card.
4
IDNF (ID Not Found)
The requested sector ID is in error or cannot be found.
2
ABRT (ABoRTed command)
This bit is set if the command has been aborted because of the card
status condition. (Not ready, Write fault, Invalid command, etc.)
0
AMNF (Address Mark Not Found) This bit is set in case of a general error.
3. Feature register: This register is write only register, and provides information regarding features of the
drive which the host wishes to utilize.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Feature byte
4. Sector count register: This register contains the numbers of sectors of data requested to be transferred on
a read or write operation between the host and the card. If the value of this register is zero, a count of 256
sectors is specified. In plural sector transfer, if not successfully completed, the register contains the number of
sectors which need to be transferred in order to complete the request. This register’s initial value is "01H".
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Sector count byte
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HN29W6484AH03TE-1
5. Sector number register: This register contains the starting sector number which is started by following
sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Sector number byte
6. Cylinder low register: This register contains the low 8-bit of the starting cylinder address which is started
by following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Cylinder low byte
7. Cylinder high register: This register contains the high 8-bit of the starting cylinder address which is
started by following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Cylinder high byte
8. Drive head register: This register is used for selecting the Drive number and Head number for the
following command.
bit7
bit6
bit5
bit4
bit3
1
LBA
1
DRV
Head number
bit2
bit1
bit0
bit
Name
Function
7
1
This bit is set to "1".
6
LBA
LBA is a flag to select either Cylinder / Head / Sector (CHS) or
Logical Block Address (LBA) mode. When LBA=0, CHS mode is
selected. When LBA=1, LBA mode is selected. In LBA mode, the
Logical Block Address is interrupted as follows:
LBA07-LBA00 : Sector Number Register D7-D0.
LBA15-LBA08 : Cylinder Low Register D7-D0.
LBA23-LBA16 : Cylinder High Register D7-D0.
LBA27-LBA24 : Drive / Head Register bits HS3-HS0.
5
1
This bit is set to "1".
4
DRV (DRiVe select)
This bit is used for selecting the Master (Card 0) and Slave (Card 1)
in Master/Slave organization. The card is set to be Card 0 or 1 by
using DRV# of the Socket and Copy register.
3 to 0 Head number
This bit is used for selecting the Head number for the following
command. Bit 3 is MSB.
9. Status register: This register is read only register, and it indicates the card status of command execution.
When this register is read in configured I/O card mode (INDEX = 1, 2, 3) and level interrupt mode, -IREQ is
38 Material Copyrighted by Its Respective Manufacturer
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negated. This register should be accessed in byte mode. In word mode, it is recommended that alternate
status register may be used as this register.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BSY
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
bit
Name
Function
7
BSY (BuSY)
This bit is set when the card internal operation is executing. When
this bit is set to "1", other bits in this register are invalid.
6
DRDY (Drive ReaDY)
If this bit and DSC bit are set to "1", the card is capable of receiving
the read or write or seek requests. If this bit is set to "0", the card
prohibits these requests.
5
DWF (Drive Write Fault)
This bit is set if this card indicates the write fault status.
4
DSC (Drive Seek Complete)
This bit is set when the drive seek complete.
3
DRQ (Data ReQuest)
This bit is set when the information can be transferred between the
host and Data register. This bit is cleared when the card receives
the other command.
2
CORR (CORRected data)
This bit is set when a correctable data error has been occurred and
the data has been corrected.
1
IDX (InDeX)
This bit is always set to "0".
0
ERR (ERRor)
This bit is set when the previous command has ended in some type
of error. The error information is set in the other Status register or
Error register. This bit is cleared by the next command.
10. Alternate status register: This register is the same as Status register in physically, so the bit assignment
refers to previous item of Status register. But this register is different from Status register that -IREQ is not
negated when data read.
11. Command register: This register is write only register, and it is used for writing the command at
executing the drive operation. The command code written in the command register, after the parameter is
written in the Task File during the card is Ready state.
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HN29W6484AH03TE-1
Used parameter
Command
Command code
FR
SC
SN
CY
DR
HD
LBA
Check power mode
E5H or 98H
N
N
N
N
Y
N
N
Execute drive diagnostic
90H
N
N
N
N
Y
N
N
Erase sector
C0H
N
Y
Y
Y
Y
Y
Y
Format track
50H
N
Y
N
Y
Y
Y
Y
Identify Drive
ECH
N
N
N
N
Y
N
N
Idle
E3H or 97H
N
Y
N
N
Y
N
N
Idle immediate
E1H or 95H
N
N
N
N
Y
N
N
Initialize drive parameters
91H
N
Y
N
N
Y
Y
N
Read buffer
E4H
N
N
N
N
Y
N
N
Read multiple
C4H
N
Y
Y
Y
Y
Y
Y
Read long sector
22H or 23H
N
N
Y
Y
Y
Y
Y
Read sector
20H or 21H
N
Y
Y
Y
Y
Y
Y
Read verify sector
40H or 41H
N
Y
Y
Y
Y
Y
Y
Recalibrate
1XH
N
N
N
N
Y
N
N
Request sense
03H
N
N
N
N
Y
N
N
Seek
7XH
N
N
Y
Y
Y
Y
Y
Set features
EFH
Y
N
N
N
Y
N
N
Set multiple mode
C6H
N
Y
N
N
Y
N
N
Set sleep mode
E6H or 99H
N
N
N
N
Y
N
N
Stand by
E2H or 96H
N
N
N
N
Y
N
N
Stand by immediate
E0H or 94H
N
N
N
N
Y
N
N
Translate sector
87H
N
Y
Y
Y
Y
Y
Y
Wear level
F5H
N
N
N
N
Y
Y
N
Write buffer
E8H
N
N
N
N
Y
N
N
Write long sector
32H or 33H
N
N
Y
Y
Y
Y
Y
Write multiple
C5H
N
Y
Y
Y
Y
Y
Y
Write multiple w/o erase
CDH
N
Y
Y
Y
Y
Y
Y
Write sector
30H or 31H
N
Y
Y
Y
Y
Y
Y
Write sector w/o erase
38H
N
Y
Y
Y
Y
Y
Y
Write verify
3CH
N
Y
Y
Y
Y
Y
Y
Note: FR: Feature register
SC: Sector Count register
SN: Sector Number register
CY: Cylinder register
DR: DRV bit of Drive Head register
HD: Head Number of Drive Head register
LBA: Logical Block Address Mode Supported
Y: The register contains a valid parameter for this command.
N: The register does not contain a valid parameter for this command.
40 Material Copyrighted by Its Respective Manufacturer
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12. Device control register: This register is write only register, and it is used for controlling the card
interrupt request and issuing an ATA soft reset to the card.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
×
×
×
1
SRST
nIEN
0
bit
Name
Function
7 to 4 ×
don’t care
3
1
This bit is set to "1".
2
SRST (Software ReSeT)
This bit is set to "1" in order to force the card to perform Task File
Reset operation. This does not change the Card Configuration
registers as a Hardware Reset does. The card remains in Reset
until this bit is reset to "0".
1
nIEN (Interrupt ENable)
This bit is used for enabling -IREQ. When this bit is set to "0", IREQ is enabled. When this bit is set to "1", -IREQ is disabled.
0
0
This bit is set to "0".
13. Drive Address register: This register is read only register, and it is used for confirming the drive status.
This register is provides for compatibility with the AT disk drive interface. It is recommended that this
register is not mapped into the host’s I/O space because of potential conflicts on bit7.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
nWTG
nHS3
nHS2
nHS1
nHS0
nDS1
nDS0
bit
Name
Function
7
×
This bit is unknown
6
nWTG (WriTing Gate)
This bit is unknown
5 to 2 nHS3-0 (Head Select3-0)
These bits is the negative value of Head Select bits (bit 3 to 0) in
Drive/Head register.
1
nDS1 (Idrive Select1)
This bit is unknown
0
nDS0 (Idrive Select0)
This bit is unknown
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HN29W6484AH03TE-1
ATA Command specifications
This table summarizes the ATA command set with the paragraphs. Following shows the support commands
and command codes which are written in command registers.
ATA Command Set
No.
Command set
Code
FR
SC
SN
CY
DR
HD
LBA
1
Check power mode
E5H or 98H
—
—
—
—
Y
—
—
2
Execute drive diagnostic
90H
—
—
—
—
Y
—
—
3
Erase sector(s)
C0H
—
Y
Y
Y
Y
Y
Y
4
Format track
50H
—
Y
—
Y
Y
Y
Y
5
Identify Drive
ECH
—
—
—
—
Y
—
—
6
Idle
E3H or 97H
—
Y
—
—
Y
—
—
7
Idle immediate
E1H or 95H
—
—
—
—
Y
—
—
8
Initialize drive parameters
91H
—
Y
—
—
Y
Y
—
9
Read buffer
E4H
—
—
—
—
Y
—
—
10
Read multiple
C4H
—
Y
Y
Y
Y
Y
Y
11
Read long sector
22H, 23H
—
—
Y
Y
Y
Y
Y
12
Read sector (s)
20H, 21H
—
Y
Y
Y
Y
Y
Y
13
Read verify sector (s)
40H, 41H
—
Y
Y
Y
Y
Y
Y
14
Recalibrate
1XH
—
—
—
—
Y
—
—
15
Request sense
03H
—
—
—
—
Y
—
—
16
Seek
7XH
—
—
Y
Y
Y
Y
Y
17
Set features
EFH
Y
—
—
—
Y
—
—
18
Set multiple mode
C6H
—
Y
—
—
Y
—
—
19
Set sleep mode
E6H or 99H
—
—
—
—
Y
—
—
20
Stand by
E2H or 96H
—
—
—
—
Y
—
—
21
Stand by immediate
E0H or 94H
—
—
—
—
Y
—
—
22
Translate sector
87H
—
Y
Y
Y
Y
Y
Y
23
Wear level
F5H
—
—
—
—
Y
Y
—
24
Write buffer
E8H
—
—
—
—
Y
—
—
25
Write long sector
32H or 33H
—
—
Y
Y
Y
Y
Y
26
Write multiple
C5H
—
Y
Y
Y
Y
Y
Y
27
Write multiple w/o erase
CDH
—
Y
Y
Y
Y
Y
Y
28
Write sector
30H or 31H
—
Y
Y
Y
Y
Y
Y
29
Write sector(s) w/o erase
38H
—
Y
Y
Y
Y
Y
Y
30
Write verify
3CH
—
Y
Y
Y
Y
Y
Y
42 Material Copyrighted by Its Respective Manufacturer
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HN29W6484AH03TE-1
Note: FR: Feature Register
SC: Sector Count register
(00H to FFH)
SN: Sector Number register (01H to 20H)
CY: Cylinder Low/High register (to)
DR: Drive bit of Drive/Head register
HD: Head No.(0 to 3) of Drive/Head register
NH: No. of Heads
Y: Set up
—: Not set up
1. Check Power Mode (code: E5H or 98H): This command checks the power mode.
2. Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests implemented
by the Card.
3. Erase Sector(s) (code: C0H): This command is used to erase data sectors.
4. Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive. But
selected sector data is not exchange. This card excepts a sector buffer of data from the host to follow the
command with same protocol as the Write Sector Command.
5. Identify Drive (code: ECH): This command enables the host to receive parameter information from the
Card.
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HN29W6484AH03TE-1
Identify Drive Information
Word address Default value Total bytes
Data field type information
0
848AH
2
General configuration bit-significant information
1
XXXX
2
Default number of cylinders
2
0000H
2
Reserved
3
00XXH
2
Default number of heads
4
0000H
2
Number of unformatted bytes per track
5
XXXX
2
Number of unformatted bytes per sector
6
XXXX
2
Default number of sectors per track
7 to 8
XXXX
4
Number of sectors per card (Word7 = MSW, Word8 = LSW)
9
0000H
2
Reserved
10 to 19
XXXX
20
Reserved
20
0002H
2
Buffer type (dual ported)
21
0002H
2
Buffer size in 512 byte increments
22
0004H
2
# of ECC bytes passed on Read/Write Long Commands
23 to 46
XXXX
48
Firmware revision in ASCII etc.
47
0001H
2
Maximum of 1 sector on Read/Write Multiple command
48
0000H
2
Double Word not supported
49
0200H
2
Capabilities: DMA NOT Supported (bit 8), LBA supported
(bit9)
50
0000H
2
Reserved
51
0100H
2
PIO data transfer cycle timing mode 1
52
0000H
2
DMA data transfer cycle timing mode not Supported
53 to 58
XXXX
12
Reserved
59
010XH
2
Multiple sector setting is valid
60 to 61
XXXX
4
Total number of sectors addressable in LBA Mode
62 to 127
0000H
138
Reserved
128 to 159
XXXXH
64
Reserved vendor unique bytes
160 to 255
0000H
192
Reserved
6. Idle (code: E3H or 97H): This command causes the Card to set BSY, enter the Idle mode, clear BSY and
generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the sector
count is zero, the automatic power down mode is disabled.
7. Idle Immediate (code: E1H or 95H): This command causes the Card to set BSY, enter the Idle (Read)
mode, clear BSY and generate an interrupt.
8. Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors per
track and the number of heads per cylinder.
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9. Read Buffer (code: E4H): This command enables the host to read the current contents of the card’s sector
buffer.
10. Read Multiple (code: C4H): This command performs similarly to the Read Sectors command. Interrupts
are not generated on each sector, but on the transfer of a block which contains the number of sectors defined
by a Set Multiple command.
11. Read Long Sector (code: 22H or 23H): This command performs similarly to the Read Sector(s)
command except that it returns 516 bytes of data instead of 512 bytes.
12. Read Sector(s) (code: 20H, 21H): This command reads from 1 to 256 sectors as specified in the Sector
Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the
Sector Number register.
13. Read Verify Sector(s) (code: 40H or 41H): This command is identical to the Read Sectors command,
except that DRQ is never set and no data is transferred to the host .
14. Recalibrate (code: 1XH): This command is effectively a NOP command to the Card and is provided for
compatibility purposes.
15. Request Sense (code: 03H): This command requests an extended error code after command ends with an
error.
16. Seek (code: 7XH): This command is effectively a NOP command to the Card although it does perform a
range check.
17. Set Features (code: EFH): This command is used by the host to establish or select certain features.
Feature
Operation
01H
Enable 8-bit data transfers.
55H
Disable Read Look Ahead.
66H
Disable Power on Reset (POR) establishment of defaults at Soft Reset.
81H
Disable 8-bit data transfers.
BBH
4 bytes of data apply on Read/Write Long commands.
CCH
Enable Power on Reset (POR) establishment of defaults at Soft Reset.
18. Set Multiple Mode (code: C6H): This command enables the Card to perform Read and Write Multiple
operations and establishes the block count for these commands.
19. Set Sleep Mode (code: E6H or 99H): This command causes the Card to set BSY, enter the Sleep mode,
clear BSY and generate an interrupt.
20. Stand By (code: E2H or 96H): This command causes the Card to set BSY, enter the Sleep mode (which
corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately.
21. Stand By Immediate (code: E0H or 94H): This command causes the Card to set BSY, enter the Sleep
mode(which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately.
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22. Translate Sector (code: 87H): This command allows the host a method of determining the exact number
of times a user sector has been erased and programmed.
23. Wear Level (code: F5H): This command effectively a NOP command and only implemented for
backward compatibility. The Sector Count Register will always be returned with an 00H indicating Wear
Level is not needed.
24. Write Buffer (code: E8H): This command enables the host to overwrite contents of the Card’s sector
buffer with any data pattern desired.
25. Write Long Sector (code: 32H or 33H): This command is provided for compatibility purposes and is
similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes.
26. Write Multiple (code: C5H): This command is similar to the Write Sectors command. Interrupts are not
presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set
Multiple command.
27. Write Multiple without Erase (code: CDH): This command is similar to the Write Multiple command
with the exception that an implied erase before write operation is not performed.
28. Write Sector(s) (code: 30H or 31H): This command writes from 1 to 256 sectors as specified in the
Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified
in the Sector Number register.
29. Write Sector(s) without Erase (code: 38H): This command is similar to the Write Sector(s) command
with the exception that an implied erase before write operation is not performed.
30. Write Verify (code: 3CH): This command is similar to the Write Sector(s) command, except each sector
is verified immediately after being written.
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Sector Transfer Protocol
1. Sector read: 1 sector read procedure after the card configured I/O interface is shown as follows.
Start
I/O Access, INDEX=1
Set the cylinder low / high register
Set the head No. of drive head register
(1)Set the logical sector number
Set the sector number register
Set "01H" in sector count register
Set "20H" in Command register
(2)
Read the status register
(3)
N
"58H"?
Y
Read 256 times the data register
(512 bytes)
(4)Burst data transfer
Read the status register
N
(5)
"50H"?
Y
Wait the command input
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HN29W6484AH03TE-1
(1)
A0 to A10
(2)
4H 5H 6H 3H 2H 7H
(3)
7H
(4)
(5)
7H
0H
0H
58H
Data transfer
7H
7H
-CE1
-CE2
-IOWR
-IORD
D0 to D15
01H20H 80H
-IREQ
48 Material Copyrighted by Its Respective Manufacturer
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50H
HN29W6484AH03TE-1
2. Sector write: 1 sector write procedure after the card configured I/O interface is shown as follows.
Start
I/O Access, INDEX=1
Set the cylinder low / high register
Set the head No. of drive head register
(1) Set the logical sector number
Set the sector number register
Set "01H" in sector count register
Set "30H" in command register
(2)
Read the status register
(3)
N
"58H"?
Y
Write 256 times the data register
(512 bytes)
(4) Burst data transfer
Read the status register
N
(5)
"50H"?
Y
Wait the command input
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HN29W6484AH03TE-1
(1)
A0 to A10
(2)
4H 5H 6H 3H 2H 7H
(3)
7H
(4)
(5)
7H
0H
0H
58H
Data transfer
7H
7H
80H
50H
-CE1
-CE2
-IOWR
-IORD
D0 to D15
01H30H 80H
-IREQ
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Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
All input/output voltages
Vin, Vout
–0.3 to VCC + 0.3
V
1
VCC voltage
VCC
–0.3 to +6.7
V
Operating temperature range
Topr
–40 to +85
•C
Storage temperature range
Tstg
–55 to +125
•C
Note:
1. Vin, Vout min = –2.0 V for pulse width • 20 ns.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Operating temperature
Ta
0
25
70
•C
VCC voltage
VCC
4.5
5.0
5.5
V
3.15
3.3
3.45
V
Capacitance (Ta = 25°C, f = 1MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Note
Input capacitance
Cin
—
—
15
pF
Vin = 0 V
1
Output capacitance
Cout
—
—
15
pF
Vout = 0 V
1
Note:
1. This parameter is sampled and not 100% tested.
Card System performance
Item
Performance
Set up times (Reset to ready)
100 ms (max)
Set up times (Sleep to idle)
2 ms (max)
Data transfer rate to/from host
8 MB/s burst
Controller overhead (Command to DRQ)
2 ms (max)
Data transfer cycle end to ready (Sector write)
1.2 ms (typ)
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HN29W6484AH03TE-1
DC Characteristics-1 (Ta = 0 to +70°C, VCC = 3.3 V ± 5%)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input voltage (CMOS level)
VIHC
0.7 × VCC
—
VCC + 0.3
V
—
VILC
–0.3
—
0.2 × VCC
V
VIHC
2.0
—
VCC + 0.3
V
VILC
–0.3
—
0.6
V
VTC+
(1.6)
—
2.6
V
0.7
—
(1.7)
V
VTC*
(0.3)
—
—
V
VOH
VCC – 0.4
—
—
V
IOH = –2 mA
VOL
—
—
0.4
V
IOL = 2 mA
VOH
VCC – 0.4
—
—
V
IOH = –3 mA
VOL
—
—
0.4
V
IOL = 3 mA
VOH
VCC – 0.4
—
—
V
IOH = –2 mA
VOL
—
—
0.4
V
IOL = 3 mA
VOH
VCC – 0.4
—
—
V
IOH = –1 mA
VOL
—
—
0.4
V
IOL = 2 mA
ILI
—
—
1
µA
—
ILO
—
—
1
µA
VOUT = high impedance
–IPU
15/(230)
80/(41) 230/(13.7) µA/(kΩ) VIN = GND
–IPU
2/(1800)
16/(206) 36/(85)
µA/(kΩ) VIN = GND
ISP1
—
(0.2)
(0.5)
mA
CMOS level (control
signal = VCC – 0.2)
(In Memory card mode
and I/O card mode)
ICCR(DC)
—
(25)
(50)
mA
CMOS level
(control signal = VCC –
0.2)
ICCR(Peak) —
(50)
(80)
mA
ICCW(DC)
—
(25)
(50)
mA
ICCW(Peak) —
(50)
(80)
mA
Input voltage (TTL level)
Schmitt circuit (CMOS level)*
1
VTC–
2
Output voltage (CMOS)
3
(2 mA)*
Output voltage (CMOS)
3
(3 mA)*
Output voltage (CMOS)
3
(2 mA/3 mA)*
Output voltage (CMOS)
3
(1 mA/2 mA)*
4
Input leakage current*
4
Output leakage current*
Pull-up current/(Resistivity)
5
Pull-up current/(Resistivity)*
8
Sleep/standby current*
6, 8
Sector read current*
7, 8
Sector write current*
52 Material Copyrighted by Its Respective Manufacturer
This
—
VCC = 3.3 V
CMOS level
(control signal = VCC –
0.2)
HN29W6484AH03TE-1
DC Characteristics-2 (Ta = 0 to +70°C, VCC = 5 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input voltage (CMOS level)
VIHC
0.7 × VCC
—
VCC + 0.3
V
—
VILC
–0.3
—
0.3 × VCC
V
VIHC
2.4
—
VCC + 0.3
V
VILC
–0.3
—
0.6
V
VTC+
(2.8)
—
4.0
V
1.1
—
(2.4)
V
VTC*
(0.3)
—
—
V
VOH
VCC – 0.4
—
—
V
IOH = –4 mA
VOL
—
—
0.4
V
IOL = 4 mA
VOH
VCC – 0.4
—
—
V
IOH = –8 mA
VOL
—
—
0.4
V
IOL = 8 mA
VOH
VCC – 0.4
—
—
V
IOH = –6 mA
VOL
—
—
0.4
V
IOL = 8 mA
VOH
VCC – 0.4
—
—
V
IOH = –3 mA
VOL
—
—
0.4
V
IOL = 4 mA
ILI
—
—
1
µA
—
ILO
—
—
1
µA
VOUT = high impedance
–IPU
60/(92)
220/(23) 570/(7.9) µA/(kΩ) VIN = GND
–IPU
10/(550)
45/(110) 90/(50)
µA/(kΩ) VIN = GND
ISP1
—
(0.5)
(1.0)
mA
CMOS level (control
signal = VCC – 0.2)
(In Memory card mode
and I/O card mode)
ICCR(DC)
—
(40)
(70)
mA
CMOS level
(control signal = VCC –
0.2)
ICCR(Peak) —
(80)
(120)
mA
ICCW(DC)
—
(45)
(75)
mA
ICCW(Peak) —
(80)
(120)
mA
Input voltage (TTL level)
Schmitt circuit (CMOS level)*
1
VTC–
2
Output voltage (CMOS)
3
(2 mA)*
Output voltage (CMOS)
3
(3 mA)*
Output voltage (CMOS)
3
(2 mA/3 mA)*
Output voltage (CMOS)
3
(1 mA/2 mA)*
4
Input leakage current*
4
Output leakage current*
Pull-up current/(Resistivity)
5
Pull-up current/(Resistivity)*
8
Sleep/standby current*
6, 8
Sector read current*
7, 8
Sector write current*
This Material Copyrighted by Its Respective Manufacturer
—
VCC = 5 V
CMOS level
(control signal = VCC –
0.2)
53
HN29W6484AH03TE-1
Notes : 1.
2.
3.
4.
5.
6.
7.
8.
CMOS schmitt input is measured at VIH = VTC+ max and VIL = VTC– mim. ( ) is reference value.
VTC is reference value.
Measured for static state.
Except pulled up input/output pin.
Pull-up resister is 100 kΩ.
Measured during sector read transfer.
Measured during sector write transfer.
Power dissipation is reference value on the assembled flash card, including the flash memory.
54 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
DC Current Waveform (VCC = 5 V, Ta = 25•C)
Current
Power on Operation (Reference only)
DC
Time
Power on
This Material Copyrighted by Its Respective Manufacturer
55
HN29W6484AH03TE-1
Current
Sector Read
ICCR(Peak)
ICCR(DC)
0
Time
Command write
Complete of sector read
Sector Write
Current
ICCW(Peak)
ICCW(DC)
0
Time
Command write
Complete of sector write
56 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
AC Characteristics (Ta = 0 to +70•C, VCC = 5 V ± 10%, VCC = 3.3 V ±5%)
Attribute Memory Read AC Characteristics
250 ns
Parameter
Symbol
Min
Typ
Max
Unit
Read cycle time
tCR
250
—
—
ns
Address access time
ta(A)
—
—
250
ns
-CE access time
ta(CE)
—
—
250
ns
-OE access time
ta(OE)
—
—
125
ns
Output disable time (-CE)
tdis(CE)
—
—
100
ns
Output disable time (-OE)
tdis(OE)
—
—
100
ns
Output enable time (-CE)
ten(CE)
5
—
—
ns
Output enable time (-OE)
ten(OE)
5
—
—
ns
Data valid time (A)
tv(A)
0
—
—
ns
Address setup time
tsu(A)
30
—
—
ns
Address hold time
th(A)
20
—
—
ns
-CE setup time
tsu(CE)
0
—
—
ns
-CE hold time
th(CE)
20
—
—
ns
Attribute Memory Read Timing
tCR
A0 to A10
-REG
ta(A)
th(A)
tv(A)
ta(CE)
-CE2/-CE1
tsu(CE)
ta(OE)
tsu(A)
th(CE)
tdis(CE)
-OE
ten(OE)
tdis(OE)
ten(CE)
D0 to D15
Valid Output
-WE, -IOWR, -IORD : High Fix
This Material Copyrighted by Its Respective Manufacturer
57
HN29W6484AH03TE-1
Attribute Memory Write AC Characteristics
250 ns
Parameter
Symbol
Min
Typ
Max
Unit
Write cycle time
tCW
250
—
—
ns
Write pulse time
tw(WE)
150
—
—
ns
Address setup time
tsu(A)
30
—
—
ns
Address setup time (-WE)
tsu(A-WEH)
180
—
—
ns
-CE setup time (-WE)
tsu(CE-WEH)
180
—
—
ns
Data setup time (-WE)
tsu(D-WEH)
80
—
—
ns
Data hold time
th(D)
30
—
—
ns
Write recover time
trec(WE)
30
—
—
ns
Output disable time (-WE)
tdis(WE)
—
—
100
ns
Output disable time (-OE)
tdis(OE)
—
—
100
ns
Output enable time (-WE)
ten(WE)
5
—
—
ns
Output enable time (-OE)
ten(OE)
5
—
—
ns
Output enable setup time (-WE)
tsu(OE-WE)
10
—
—
ns
Output enable hold time (-WE)
th(OE-WE)
10
—
—
ns
-CE setup time
tsu(CE)
0
—
—
ns
-CE hold time
th(CE)
20
—
—
ns
Attribute Memory Write Timing
tCW
A0 to A10
-REG
tsu(CE-WEH)
-CE2/-CE1
tsu(A-WEH)
tsu(CE)
th(CE)
-OE
tsu(A)
-WE
tw(WE)
tsu(OE-WE)
tsu(D-WEH)
D0 to D15(Din)
trec(WE)
th(OE-WE)
th(D)
Input Data
tdis(OE)
tdis(WE)
ten(OE)
D0 to D15(Dout)
ten(WE)
-IOWR, -IORD : High Fix
58 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
I/O Access Read AC Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Data delay after -IORD
td(IORD)
—
—
100
ns
Data hold following -IORD
th(IORD)
0
—
—
ns
-IORD pulse width
tw(IORD)
165
—
—
ns
Address setup before -IORD
tsuA(IORD)
70
—
—
ns
Address hold following -IORD
thA(IORD)
20
—
—
ns
-CE setup before -IORD
tsuCE(IORD)
5
—
—
ns
-CE hold following -IORD
thCE(IORD)
20
—
—
ns
-REG setup before -IORD
tsuREG(IORD)
5
—
—
ns
-REG hold following -IORD
thREG(IORD)
0
—
—
ns
-INPACK delay falling from -IORD
tdfINPCAK(IORD) 0
—
45
ns
-INPACK delay rising from -IORD
tdrINPACK(IORD) —
—
45
ns
-IOIS16 delay falling from address
tdfIOIS16(ADR)
—
—
35
ns
-IOIS16 delay rising from address
tdrIOIS16(ADR)
—
—
35
ns
I/O Access Read Timing
A0 to A10
thA(IORD)
tsuREG(IORD)
thREG(IORD)
-REG
tsuCE(IORD)
thCE(IORD)
-CE2/-CE1
tw(IORD)
-IORD
tdrINPACK(IORD)
tsuA(IORD)
-INPACK
tdfIOIS16(ADR)
tdrIOIS16(ADR)
tdfINPACK(IORD)
-IOIS16
th(IORD)
D0 to D15
Valid Output
td(IORD)
-WE, -OE, -IOWR : High Fix
This Material Copyrighted by Its Respective Manufacturer
59
HN29W6484AH03TE-1
I/O Access Write AC Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Data setup before -IOWR
tsu(IOWR)
60
—
—
ns
Data hold following -IOWR
th(IOWR)
30
—
—
ns
-IOWR pulse width
tw(IOWR)
165
—
—
ns
Address setup before -IOWR
tsuA(IOWR)
70
—
—
ns
Address hold following -IOWR
thA(IOWR)
20
—
—
ns
-CE setup before -IOWR
tsuCE(IOWR)
5
—
—
ns
-CE hold following -IOWR
thCE(IOWR)
20
—
—
ns
-REG setup before -IOWR
tsuREG(IOWR)
5
—
—
ns
-REG hold following -IOWR
thREG(IOWR)
0
—
—
ns
-IOIS16 delay falling from address
tdfIOIS16(ADR)
—
—
35
ns
-IOIS16 delay rising from address
tdrIOIS16(ADR)
—
—
35
ns
I/O Access Write Timing
A0 to A10
thA(IOWR)
tsuREG(IOWR)
thREG(IOWR)
-REG
tsuCE(IOWR)
thCE(IOWR)
-CE2/-CE1
tsuA(IOWR)
tw(IOWR)
-IOWR
tdfIOIS16(ADR)
tdrIOIS16(ADR)
-IOIS16
tsu(IOWR)
D0 to D15
th(IOWR)
Data In
-WE, -OE, -IORD : High Fix
60 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Common Memory Access Read AC Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
-OE access time
ta(OE)
—
—
125
ns
Output disable time (-OE)
tdis(OE)
—
—
100
ns
Address setup time
tsu(A)
30
—
—
ns
Address hold time
th(A)
20
—
—
ns
-CE setup time
tsu(CE)
0
—
—
ns
-CE hold time
th(CE)
20
—
—
ns
Common Access Read Timing
A0 to A10
th(A)
tsu(A)
-REG
-CE2/-CE1
tsu(CE)
th(CE)
ta(OE)
-OE
tdis(OE)
D0 to D15
Valid Output
-WE, -IORD, -IOWR : High Fix
This Material Copyrighted by Its Respective Manufacturer
61
HN29W6484AH03TE-1
Common Memory Access Write AC Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Data setup time (-WE)
tsu(D-WEH)
80
—
—
ns
Data hold time
th(D)
30
—
—
ns
Write pulse time
tw(WE)
150
—
—
ns
Address setup time
tsu(A)
30
—
—
ns
-CE setup time
tsu(CE)
0
—
—
ns
Write recover time
trec(WE)
30
—
—
ns
-CE hold following -WE
th(CE)
20
—
—
ns
Common Access Write Timing
A0 to A10
-REG
trec(WE)
tsu(CE)
-CE2/-CE1
tsu(A)
-WE
th(CE)
tw(WE)
tsu(D-WEH)
D0 to D15
th(D)
Data In
-IOWR, -IORD, -OE : High Fix
62 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
True IDE Mode Access Read AC Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
data delay after IORD
td(IORD)
—
—
100
ns
data hold following IORD
th(IORD)
0
—
—
ns
IORD width time
tw(IORD)
165
—
—
ns
address setup before IORD
tsuA(IORD)
70
—
—
ns
address hold following IORD
thA(IORD)
20
—
—
ns
CE setup before IORD
tsuCE(IORD)
5
—
—
ns
CE hold following IORD
thCE(IORD)
20
—
—
ns
IOIS16 delay falling from address
tdfIOIS16(ADR)
—
—
35
ns
IOIS16 delay rising from address
tdfIOIS16(ADR)
—
—
35
ns
True IDE Mode Access Read Timing
A0 to A2
thA(IORD)
thCE(IORD)
tsuA(IORD)
tsuCE(IORD)
-CE2/-CE1
tw(IORD)
-IORD
td(IORD)
tdrlOIS(ADR)
-IOIS16
tdrlOIS(ADR)
th(IORD)
D0 to D15
Valid Output
-IOWR: High Fix, -OE: Low Fix, -WE: High Fix
This Material Copyrighted by Its Respective Manufacturer
63
HN29W6484AH03TE-1
True IDE Mode Access Write AC Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Data setup before IOWR
tsu(IOWR)
60
—
—
ns
data hold following IOWR
th(IOWR)
30
—
—
ns
IORD width time
tw(IOWR)
165
—
—
ns
address setup before IOWR
tsuA(IOWR)
70
—
—
ns
address hold following IOWR
thA(IOWR)
20
—
—
ns
CE setup before IOWR
tsuCE(IOWR)
5
—
—
ns
CE hold following IOWR
thCE(IOWR)
20
—
—
ns
IOIS16 delay falling from address
tdfIOIS16(ADR)
—
—
35
ns
IOIS16 delay rising from address
tdfIOIS16(ADR)
—
—
35
ns
True IDE Mode Access Write Timing
A0 to A2
tsuA(IOWR)
tsuCE(IOWR)
-CE2/-CE1
thA(IOWR)
thCE(IOWR)
tw(IOWR)
-IOWR
tdrlOIS(ADR)
-IOIS16
tdrlOIS(ADR)
D0 to D15
tsu(IOWR) th(IOWR)
Valid Output
-IORD: High Fix, -OE: Low Fix, -WE: High Fix
64 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Flash Memory Interface AC Characteristics
(Ta = 0 to +70°C, VCC = 5 V ± 10%, 3.3 V ± 5%)
Parameter
Symbol
Min
Typ
Max
Unit
Write pulse time
tWP
60
—
—
ns
Write pulse high time
tWPH
40
—
—
ns
F_CDE_ setup time for F_WE_
tCDS
0
—
—
ns
Data setup time
tDS
50
—
—
ns
Data hold time
tDH
10
—
—
ns
Address setup time
tAS
50
—
—
ns
Address hold time
tAH
10
—
—
ns
F_OE_ setup time for F_SC
tOES
0
—
—
ns
F_OE_ low to output low-z
tOEL
0
—
—
ns
F_CDE_ setup time for F_SC
tCDSS
100
—
—
ns
Serial clock cycle time
tSCC
50
—
—
ns
F_SC pulse width
tSP
20
—
—
ns
F_SC pulse low time
tSPL
20
—
—
ns
F_SC to output delay
tSAC
—
—
50
ns
F_SC to output hold
tSH
15
—
—
ns
Data setup time for F_SC
tSDS
0
—
—
ns
Data hold time for F_SC
tSDH
30
—
—
ns
F_OE_ to output delay
tOE
—
—
60
ns
F_OE_ high to output flat
tDF
—
—
40
ns
Time to device busy
tDB
—
—
150
ns
This Material Copyrighted by Its Respective Manufacturer
65
HN29W6484AH03TE-1
Flash Memory Interface timing
tWP
tWPH
tWP
F_WE_
tCDS
F_CDE_
tCDS
tDS
tAS
tDH
tAH
F_D0 to F_D7
Flash Command Write Timing
Flash Address Write Timing
F_OE_
F_CDE_
tOES
tSCC
tSCC
tSP
tSPL
tCDSS
tSCC
tSP
tSPL
F_SC
tOEL
tSAC
tSAC
tSH
tSDH
tSDS
D_D0 to F_D7
Flash Command Write Timing
Flash Command Write Timing
F_OE_
F_CDE_
tOE
tDF
tOE
F_D0 to F_D7
Flash Command Write Timing
Flash Command Write Timing
F_WE_
F_D0 to F_D7
tDB
F_RDY
Flash Command Write Timing
Note: F_OE_ : Connect to F_OEA_ or F_OEB_ .
F_WE_ : Connect to F_WEA_ and F_WEB_ .
F_CDE_ : Connect to F_CDEA_ and F_CDEB_ .
F_SC : Connect to F_SC_1A, F_SC_2A or F_SC_1B, F_SC_2B.
F_D0 to F_D7 : Connect to F_DA_0 to F_DA7 and F_DB_0 to F_DB7 .
F_RDY_ : Connect to F_RDY_1 and F_RDY_2.
66 Material Copyrighted by Its Respective Manufacturer
This
tDF
HN29W6484AH03TE-1
Reset Characteristics (only Memory Card Mode or I/O Card Mode)
Hard Reset Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Reset setup time
tsu(RESET)
100
—
—
ms
-CE recover time
trec(VCC)
1
—
—
µs
VCC rising up time
tpr
0.1
—
100
ms
VCC falling down time
tpf
3
—
300
ms
Reset pulse width
tw(RESET)
10
—
—
µs
th(Hi-ZRESET) 1
—
—
ms
ts(Hi-ZRESET) 0
—
—
ms
Test conditions
Hard Reset Timing
tpf
tpr
90%
Vcc
90%
trec(Vcc)
10%
10%
-CE1, -CE2
th(Hi-ZRESET)
tsu(RESET)
tw(RESET)
RESET
High-Z
Low
This Material Copyrighted by Its Respective Manufacturer
ts(Hi-ZRESET)
High-Z
67
HN29W6484AH03TE-1
Power on Reset Characteristics
Power on reset sequence must need by -PORST at the rising of VCC.
Parameter
Symbol
Min
Typ
Max
Unit
-CE setup time
tsu(VCC)
100
—
—
ms
VCC rising up time
tpr
0.1
—
100
ms
Test conditions
Power on Reset Timing
tpr
Vcc
-PORST
tsu(vcc)
-CE1, -CE2
Attention for Card Use
• In the reset or power off, all register informations are cleared.
• Notice that the card insertion/removal should not be executed during host is active, if the card is used in
True IDE mode.
• After the card hard reset, soft reset, or power on reset, ATA reset, command applied the card cannot access
during +RDY/-BSY pin is "low" level. Flash card can’t be operated in this case.
• Notice that the card removal should be executed after card internal operations completed.
• Before the card insertion VCC can not be supplied to the card. After confirmation that -CD1, -CD2 pins are
inserted, supply VCC to the card.
• -OE must be kept at the VCC level during power on reset in memory card mode and I/O card mode. -OE
must be kept constantly at the GND level in True IDE mode.
68 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Physical Outline
Unit: mm
16.0 ± 0.2
90
0 – 8˚
14
61
60
0.4
16.0 ± 0.2
91
120
31
1.0
0.5 ± 0.1
0.10
*Dimension including the plating thickness
Basematerial dimension
This Material Copyrighted by Its Respective Manufacturer
1.20
1.00
0.07 M
0.10 ± 0.10
*0.17 ± 0.05
0.15 ±0.04
*0.17 ± 0.05
0.15 ± 0.04
30
1.20 Max
1
69
RPWR1
_CSEL
-CE1
-CE2
-WE
-IREQ
-IOIS16
-IORD
-IOWR
-WAIT
-INPACK
-REG
-STSCHG
-SPKR
-OE
-RESET
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
-VS1 D12
-VS2 D13
-CD1 D14
-CD2 D15
114
99
103
112
113
12
104
105
117
2
3
5
4
101
116
7
6
1
120
119
118
110
109
108
107
100
9
10
11
89
90
91
92
98
13
14
15
93
94
95
97
102
18
23
TEST1
70 Material Copyrighted by Its Respective Manufacturer
This
IC1
VCC: 16, 25, 46, 59, 76, 87, 106
GND: 8, 21, 24, 34, 48, 51, 62, 69, 81, 88, 96, 111
PC Card Slot (ATA Card specification)
TEST3
TEST2
45
GND
VCC
VCC
VCC
83
72
84
82
80
79
78
77
75
74
73
60
61
38
26
39
37
36
35
33
32
31
30
29
41
27
28
85
40
57
58
63
64
65
66
67
68
70
71
42
43
44
49
50
52
53
54
55
56
VCC
F_CEB_10
F_CEB_8
F_CEB_6
F_CEB_4
F_CEB_2
F_SC_B2
F_RDY_2
F_CEB_9
F_CEB_7
F_CEB_5
F_CEB_3
F_CEB_1
F_SC_B1
F_RDY_1
C14 to 23
VCC
F_CEA_10
F_CEA_8
F_CEA_6
F_CEA_4
F_CEA_2
F_SC_A2
F_RDY_2
F_CEA_9
F_CEA_7
F_CEA_5
F_CEA_3
F_CEA_1
F_SC_A1
F_RDY_1
C4 to 13
CEN
SC
RDY-BSY
CEN
SC
RDY-BSY
CEN
SC
RDY-BSY
CEN
SC
RDY-BSY
VCC
VSS
IC2 A-10
IC2 A-8
IC2 A-6
IC2 A-4
IC2 A-2
IC2 A-9
IC2 A-7
IC2 A-5
IC2 A-3
IC2 A-1
IC2 B-10
IC2 B-8
IC2 B-6
IC2 B-4
IC2 B-2
IC2 B-9
IC2 B-7
IC2 B-5
IC2 B-3
IC2 B-1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
CDEN
WEN
OEN
RESET
C1 to 3
F_OEA_
F_WEA_
F_CDEA_
F_DA(0)
F_DA(1)
F_DA(2)
F_DA(3)
F_DA(4)
F_DA(5)
F_DA(6)
F_DA(7)
F_SC_A1
F_SC_A2
F_OEB_
F_WEB_
F_CDEB_
F_DB(0)
F_DB(1)
F_DB(2)
F_DB(3)
F_DB(4)
F_DB(5)
F_DB(6)
F_DB(7)
F_RES
F_SC_B1
F_SC_B2
F_RDY_1
F_RDY_2
F_CEA_1
F_CEA_2
F_CEA_3
F_CEA_4
F_CEA_5
F_CEA_6
F_CEA_7
F_CEA_8
F_CEA_9
F_CEA_10
F_CEB_1
F_CEB_2
F_CEB_3
F_CEB_4
F_CEB_5
F_CEB_6
F_CEB_7
F_CEB_8
F_CEB_9
F_CEB_10
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
CDEN
WEN
OEN
RESET
VCC
CSEL_
H_CE_1
H_CE_2
H_WE_
H_IREQ_
H_IOIS16_
H_IORD_
H_IOWR_
H_WAIT_
H_INPACK_
H_REG_
H_STSCHG_
DASP_
H_OE_
H_RESET
H_A(0)
H_A(1)
H_A(2)
H_A(3)
H_A(4)
H_A(5)
H_A(6)
H_A(7)
H_A(8)
H_A(9)
H_A(10)
H_D(0)
H_D(1)
H_D(2)
H_D(3)
H_D(4)
H_D(5)
H_D(6)
H_D(7)
H_D(8)
H_D(9)
H_D(10)
H_D(11)
H_D(12)
H_D(13)
H_D(14)
H_D(15)
PORST_
XOUT
XIN
120 pin TQFP
F_DB(7)
F_DB(6)
F_DB(5)
F_DB(4)
F_DB(3)
F_DB(2)
F_DB(1)
F_DB(0)
F_CDEB_
F_WEB_
F_OEB_
F_RES
VCC
22
VCC
VSS
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
CDEN
WEN
OEN
RESET
VCC
RHDD0 to 15
CPWR2
3
1
X’tal 20MHz
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
CDEN
WEN
OEN
RESET
C0
VSS
CX0
2, 4
CX1
F_DA(7)
F_DA(6)
F_DA(5)
F_DA(4)
F_DA(3)
F_DA(2)
F_DA(1)
F_DA(0)
F_CDEA_
F_WEA_
F_OEA_
F_RES
CPWR1
Reset IC
VCC
4
NC
5 NC
2 VDD
OUT 1
RXTAL
3
VCC
HN29W6484AH03TE-1
Schematic Flash Card (Reference only)
RRCEB10
RRCEB9
RRCEB8
RRCEB7
RRCEB6
RRCEB5
RRCEB4
RRCEB3
RRCEB2
RRCEB1
GND
VCC
20
19
REMODE
RPWR2
RRST
ROE
HN29W6484AH03TE-1
Card density for HN29W6411A
Card
density
Pieces
of flash
memory
Used
flash
memory
160M byte
20
A-1 to A-10,
(135M byte)
18
PC card slot pin
Number Number Number of Number
of
of
sectors
of
cylinders heads
/track
sectors
615
16
32
314,880
738
8
48
283,392
984
8
32
251,904
861
8
32
220,416
738
8
32
188,928
B-1 to B-10
A-1 to A-10,
B-1 to B-8
(144M byte)
16
A-1 to A-10,
CompactFlashTM
card specification
ATA card
specification
B-1 to B-6
(112M byte)
14
A-1 to A-10,
B-1 to B-4
106M byte
12
A-1 to A10,
B-1 to B-2
80M byte
10
A-1 to A-10
615
8
32
157,440
64M byte
8
A-1 to A-8
984
4
32
125,952
48M byte
6
A-1 to A-6
738
4
32
94,464
32M byte
4
A-1 to A-4
492
4
32
62,976
16M byte
2
A-1 to A-2
246
4
32
31,488
8M byte
1
A-1
246
2
32
15,744
48M byte
6
A-1 to A-6
738
4
32
94,464
32M byte
4
A-1 to A-4
492
4
32
62,976
16M byte
2
A-1 to A-2
246
4
32
31,488
8M byte
1
A-1
246
2
32
15,744
Card
density
Pieces
of flash
memory
Used
flash
memory
ATA card
specification
20M byte
2
A-1 to A-2
320
4
32
40,960
10M byte
1
A-1
320
2
32
20,480
CompactFlashTM
card specification
Card density for HN29W8411
20M byte
2
A-1 to A-2
320
4
32
40,960
10M byte
1
A-1
320
2
32
20,480
Number Number Number of Number
of
of
sectors
of
cylinders heads
/track
sectors
Sample bill of materials
Item
IC1
IC2
Reset IC
X'tal
RRST
RPWR1
RPWR2
RXTAL
REMODE
ROE
RRCEB1 to RRCEB10
RHDD0 to RHDD15
CPWR1
CPWR2
CX0 to CX1
C0
C1 to C23
Specification
Controller
Flash memory
—
20 MHz
100 kΩ
2 kΩ
100 kΩ
1 MΩ
2 kΩ
100 kΩ
100 kΩ
0Ω
1 µF
0.1 µF
10 pF
1 µF
0.1 µF
This Material Copyrighted by Its Respective Manufacturer
ATA card CompactFlashTM
Signal name
(I/O card mode) specification card specification
VCC
-SPKR
-CSEL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
-CE1
-OE
-WE
-IREQ
-IOIS16
-CE2
-IORD
-IOWR
RESET
-WAIT
-INPACK
-REG
-STSCHG
GND
-CD1
-CD2
-VS1
-VS2
17, 51
62
56
29
28
27
26
25
24
23
22
12
11
8
30
31
32
2
3
4
5
6
64
65
66
37
38
39
40
41
7
9
15
16
33
42
44
45
58
59
60
61
63
1, 34, 35, 68
36
67
43
57
13, 38
45
39
20
19
18
17
16
15
14
12
11
10
8
21
22
23
2
3
4
5
6
47
48
49
27
28
29
30
31
7
9
36
37
24
32
34
35
41
42
43
44
46
1, 50
26
25
33
40
71
HN29W6484AH03TE-1
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright,
trademark, or other intellectual property rights for information contained in this document. Hitachi bears
no responsibility for problems that may arise with third party’s rights, including intellectual property
rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact
Hitachi’s sales office before using the product in an application that demands especially high quality and
reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily
injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety
equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
: http:semiconductor.hitachi.com/
Europe
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan)
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
72 Material Copyrighted by Its Respective Manufacturer
This
HN29W6484AH03TE-1
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
0.0
Nov. 27, 1998
Initial issue
M. Shirai
T. Totsuka
1.0
Apr. 16, 1999
Correct errors: Change of figures for Flash memory
interface timing and Schematic flash card
4. Socket and copy register (Address 206H)
Addition of table for DRV#
9. Status register: Addition of description
CIS information
Change of Address 0A2H, 0CAH, 0FCH and 12EH
Change of description for 4. Sector count register
Change of description for 17. Set features 81H:
Enable 8-bit... to Disable 8-bit...
Change of Identify drive information: Word address
“60 to 255” to “62 to 127”, “128 to 159” and “160 to 255”
Addition of description for 23. Wear level
DC Characteristics
ISP1 max: TBD to 0.5 mA
Addition of ISP1 test conditions:
CMOS level (control signal = VCC – 0.2 V)
In Memory card mode and I/O card mode
DC Current Waveform
Change of figures: Sector read and sector write
Addition of figure for Power on operation
Power on Reset Characteristics
Change of description and figure
Attention for Card Use (Notes For Host Interface Design)
Change of title and description
This Material Copyrighted by Its Respective Manufacturer
73