HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM DESCRIPTION The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs The Hynix HY5W2A2F series is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5W2A2F series is organized as 4banks of 1,048,576x32. The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM also provides for special programmable options including Partial Array Self Refresh of 1bank, 2banks, or all banks, Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum power reduction by removing power to the memory array within each SDRAM. By using this feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. FEATURES • • • • • • • • Standard SDRAM Protocol Internal 4bank operation Voltage : VDD = 2.5V, VDDQ = 1.8V & 2.5V LVTTL compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features ( HY5W22F / HY57W283220T series can’t support these features) - PASR(Partial Array Self Refresh) - TCSR(Temperature Compensated Self Refresh) - Deep Power Down Mode Packages : 90ball, 0.8mm pitch FBGA / 86pin, TSOP -25 ~ 85C Operation ORDERING INFORMATION Part No. Clock Frequency CAS Latench Organization Interface HY57W2A3220(L/S)T-H HY5W2A2(L/S)F-H 133MHz CL 3 4Banks x 1Mbits x32 LVTTL HY57W2A3220(L/S)T-8 HY5W2A2(L/S)F-8 125MHz CL 3 4Banks x 1Mbits x32 LVTTL HY57W2A3220(L/S)T-P HY5W2A2(L/S)F-P 100MHz CL 2 4Banks x 1Mbits x32 LVTTL HY57W2A3220(L/S)T-S HY5W2A2(L/S)F-S 100MHz CL 3 4Banks x 1Mbits x32 LVTTL HY57W2A3220(L/S)T-B HY5W2A2(L/S)F-B 66MHz CL 2 4Banks x 1Mbits x32 LVTTL Package 90balls FBGA (HY5xxxxxxF) 86pin TSOP-II (HY5xxxxxxT) This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM PIN CONFIGURATION ( HY57W2A3220T Series) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /W E /C A S /R A S /C S A11 BA0 BA1 A 1 0 /A P A0 A1 A2 DQM2 VDD NC D Q 16 VSSQ D Q 17 D Q 18 VDDQ D Q 19 D Q 20 VSSQ D Q 21 D Q 22 VDDQ D Q 23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 8 6 p in T S O P II 4 0 0 m il x 8 7 5 m il 0 .5 m m p in p itc h 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS D Q 15 VSSQ D Q 14 D Q 13 VDDQ D Q 12 D Q 11 VSSQ D Q 10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC C LK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC D Q 31 VDDQ D Q 30 D Q 29 VSSQ D Q 28 D Q 27 VDDQ D Q 26 D Q 25 VSSQ D Q 24 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.4/Oct. 02 3 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM Ball CONFIGURATION ( HY5W2A2F Series) 1 2 3 4 5 6 7 8 9 D Q 26 D Q 24 VSS VDD D Q 23 D Q 21 D Q 28 VDDQ VSSQ VDDQ VSSQ D Q 19 VSSQ D Q 27 D Q 25 D Q 22 D Q 20 VDDQ VSSQ D Q 29 D Q 30 D Q 17 D Q 18 VDDQ VDDQ D Q 31 NC NC D Q 16 VSSQ VSS DQM3 A3 A2 DQM2 VDD A4 A5 A6 A 10 A0 A1 A B C D E F G T o p V ie w H A7 A8 NC NC BA1 A 11 C LK CKE A9 BA0 /C S /R A S DQM1 NC NC /C A S /W E DQM0 VDDQ DQ8 VSS VDD DQ7 VSSQ VSSQ D Q 10 DQ9 DQ6 DQ5 VDDQ VSSQ D Q 12 D Q 14 DQ1 DQ3 VDDQ D Q 11 VDDQ VSSQ VDDQ VSSQ DQ4 D Q 13 D Q 15 VSS VDD DQ0 J K L M N P R DQ2 Ball DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.4/Oct. 02 4 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 32 I/O Synchronous DRAM TCSR, PASR Extended Mode Register Self refresh logic & timer Internal Row Counter DQM0 DQM1 DQM2 DQM3 BA1 BA0 Rev. 0.4/Oct. 02 Address Registers Burst Counter Burst Length A11 Address buffers A1 DQ31 Column Add Counter bank select A0 Column decoders DQ0 I/O Buffer & Logic Column pre Decoders Memory Cell Array Sense AMP & I/O Gate WE Column Active Row decoders CAS refresh Row decoders RAS State Machine CS 1Mx32 Bank3 1Mx32 Bank2 1Mx32 Bank1 1Mx32 Bank0 Row decoders CKE Row Pre Decoders Row decoders Row Active CLK Mode Register CAS Latency Data Out Control 5 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 0 0 A11 A10 A9 A8 A7 0 0 0 0 0 A6 A5 A4 A3 CAS Latency BT A2 A1 A0 Burst Length CAS Latency A6 A5 A4 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved CAS Latency Reserved Burst Type A3 Burst Type 0 Sequential 1 Interleave Burst Length A2 A1 0 0 0 A0 Burst Length A3 = 0 A3=1 0 1 1 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM BASIC FUNCTIONAL DESCRIPTION (Continued) Extended Mode Register BA1 BA0 1 0 A11 A10 A9 A8 A7 A6 A5 0 0 0 0 0 0 0 A4 A3 TCSR A2 A1 A0 PASR TCSR (Temperature Compensated Self Refresh) A4 A3 Temperature o C 0 0 70 0 1 45 1 0 15 1 1 85 PASR (Partial Array Self Refresh) A2 A1 A0 Self Refresh Coverage 0 0 0 All Banks 0 0 1 Half of Total Bank (BA1=0) 0 1 0 Quarter of Total Bank (BA1=BA0=0) 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM Power Up and Initialization Like a Synchronous DRAM, Low Power SDRAM must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial pause of 200 µsec is required. And a precharge all command will be issued to the LP SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR & TCSR). The following these cycles, the LP SDRAM is ready for normal opeartion. Programming the registers Mode Register The mode register contains the specific mode of operation of the LP SDRAM. This register includes the selection of a burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2, or 3), a burst type, an opearting mode to differentiate between normal mode and a special burst read and single write mode. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. Extended Mode Register The extended mode register contains the specific features of self refresh opeartion of the LP SDRAM. This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.), tempearture range of the device(85, 70, 45, 15) for reducing current consumption during self refresh. The extended mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set command. Bank(Row) Active The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and the value on the A0-A11 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write opeartions can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command. Read The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the sarting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.The length of burst and the CAS latency will be determined by the values programmed during the MRS command. Write The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM Precharge The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the precharge command is issued. Auto Precharge The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated. Burst Termination The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open. Data Mask The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is issued, data ouputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command is issued, data inputs can’t be written with no clock delay. Clock Suspend The Clock Suspend command is used to suspend the internal clock of DRAM. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations. Power Down The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all of the input buffer except CKE are gated off. Auto Refresh The Auto Refresh command is used during normal operation and is similar to CBR refresh in Coventional DRAMs. This command must be issued each time a refresh is required. When an Auto Refresh command is issued , the address bits is “Don’t care”, because the specific address bits is generated by internal refresh address counter. Self Refresh The Self Refresh command is used to retain cell data in the Low Power SDRAM. In the Self Refresh mode, the Low Power SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Low Power SDRAM can accomplish an special Self Refresh operation by the specific modes(TCSR, PASR) programmed in extended mode registers. The Low Power SDRAM can control the refresh rate by the temperature value of TCSR (Temperature Compensated Self Refresh) and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Low Power SDRAM can reduce the self refresh current(IDD6) by using these two modes. Deep Power Down The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. For more information, see the special operation for Low Power consumption of this data sheet. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM COMMAND TRUTH TABLE Function A10/ AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X Op Code 2 Extended Mode Register Set H X L L L L X Op Code 2 No Operation H X L H H H X X Device Deselect H X H X X X X X Bank Active H X L L H H X Read H X L H L H Read with Autoprecharge H X L H L H Write H X L H L Write with Autoprecharge H X L H Precharge All Banks H X L Precharge selected Bank H X Burst stop H X Data Write/Output Enable H X Data Mask/Output Disable H X Auto Refresh H H L L L Self Refresh Entry H L L L Self Refresh Exit L H H Precharge Power Down Entry H Precharge Power Down Exit L Clock Suspend Entry H L H L Clock Suspend Exit L H Deep Power Down Entry H L Deep Power Down Exit L H ADDR Row Address BA V Column L V X Column H V L X Column L V L L X Column H V L H L X X H X L L H L X X L V L H H L X X X X X X V X H X X L H X X X X X X X L H H H H X X X X X L H H H H X X X X X L H H H H X X X X X L V V V X X X X X X X L H H X L Note 1 Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM CURRENT STATE TRUTH TABLE (Sheet 1 of 3) Current State idle Row Active Read Write Command CS RAS CAS WE BA0,BA1 A11-A0 Action Description L L L L L L L L L L H H L H L H Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X Row Add. Bank Activate BA L H L L BA L H L H L H L L L L L H X L L L L H H X L L H H L H X L H L H L L H L H L H L L L H X L L L H X L L H H X L H L Col Add. Write/WriteAP A10 Col Add. Read/ReadAP BA A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X L L L H H L H L BA BA L H L H L H L L L H X L L L H X L L H H X L H L Row Add. Bank Activate Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X L L L H H L H L BA BA L H L H BA L H H X H X H X X X Row Add. Bank Activate Col Add. Write/WriteAP A10 Col Add. Read/ReadAP A10 No Operation X Device Deselect X Set the Mode Register Start Auto or Self Refresh Notes 14 5 No Operation Activate the specified bank and row ILLEGAL 4 ILLEGAL 4 No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : optional AP(A10=H) Start Read : optional AP(A10=H) 3 3 13,14 13 7 4 6 6 No Operation No Operation ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) 13,14 13 4 8,9 8 Continue the Burst Continue the Burst ILLEGAL ILLEGAL Termination Burst: Start the Precharge 13,14 13 10 ILLEGAL Termination Burst: Start Write(optional AP) 4 8 Termination Burst: Start Read(optional AP) 8,9 Continue the Burst Continue the Burst This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM CURRENT STATE TRUTH TABLE (Sheet 2 of 3) Current State Read with Auto Precharge Write with Auto Precharge Precharging Row Activating Command CS RAS CAS WE BA0,BA1 A11-A0 L L L L L L L L L H L L H H L L H L H L L H L H L H L L L L L H X L L L L H H X L L H H L H X L H L H L L H L H L H L L L H X L L L H X L L H H X L H L Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X Bank Activate Row Add. BA Col Add. Write/WriteAP BA A10 Col Add. Read/ReadAP BA A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X L L L H H L H L BA BA L H L H BA L H H H X H X X X X L L L L L L L L L H L L H H L L H L H L L H L H L H H H H X X X Row Add. Bank Activate Col Add. Write/WriteAP A10 Col Add. Read/ReadAP A10 No Operation X X Device Deselect Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X X X Action Description Device Deselect ILLEGAL Notes ILLEGAL 13,14 13 4,12 4,12 12 ILLEGAL 12 ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL 13,14 13 4,12 4,12 12 ILLEGAL 12 ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP ILLEGAL 13,14 13 ILLEGAL 4,12 4,12 ILLEGAL 4,12 No Operation: Bank(s) idle after tRP No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL 13,14 13 4,12 ILLEGAL ILLEGAL 4,11,12 4,12 ILLEGAL 4,12 No Operation: Row Active after tRCD No Operation: Row Active after tRCD This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM CURRENT STATE TRUTH TABLE (Sheet 3 of 3) Current State Write Recovering Write Recovering with Auto Precharge Refreshing Mode Register Accessing Command CS RAS CAS WE BA0,BA1 L L L L L L L L L H L L H H L L H L H L L H L H L H H H H X X X L L L L L L L L L H L L H H L L H L H L L H L H L H H H H X X X L L L L L L L L L H L L H H L L H L H L L H L H L H L L L L L H X L L L L H H X L L H H L H X L H L H L L H L H L H H H H X X X A11-A0 Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X Row Add. Bank Activate BA Col Add. Write/WriteAP BA A10 Col Add. Read/ReadAP BA A10 No Operation X X X X Device Deselect Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X X X Device Deselect Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X Row Add. Bank Activate BA Col Add. Write/WriteAP BA A10 BA Col Add. Read/ReadAP A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X X X Action Description Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes 13,14 13 4,13 4,12 Start Write: Optional AP(A10=H) Start Read: Optional AP(A10=H) No Operation: Row Active after tDPL No Operation: Row Active after tDPL ILLEGAL 9 ILLEGAL 13,14 13 4,13 4,12 4,12 ILLEGAL 4,9,12 ILLEGAL ILLEGAL ILLEGAL No Operation: Precharge after tDPL No Operation: Precharge after tDPL ILLEGAL ILLEGAL 13,14 13 13 13 13 ILLEGAL 13 ILLEGAL ILLEGAL ILLEGAL No Operation: idle after tRC No Operation: idle after tRC ILLEGAL ILLEGAL 13,14 13 13 13 13 ILLEGAL 13 ILLEGAL ILLEGAL ILLEGAL No Operation: idle after 2 clock cycles No Operation: idle after 2 clock cycles This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM Note : 1. H: Logic High, L: Logic Low, X: Don’t care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don’t satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM CKE Enable(CKE) Truth TABLE CKE Current State Previous Current CS Cycle Cycle Self Refresh Power Down Deep Power Down All Banks Idle Any State other than listed above Command RAS CAS WE Action BA0, A11BA1 A0 H L X H X H X X X X X X X X X X L H L H H H X X L L L L H L H H H L X H L L L X X H H H L X X X H L X X X X L X X X X X X X X X X X X X X X X X L L H L L H L X H L L X X X X X X X X X X X X X X X X X X X X X X X X X X X X X H H H H H H H H H H L H H H H H H L L L L L X H H L L L L H L L L L X X X H L L L X H L L L X X X X H L L X X H L L X X X X X H L X X X H L X X H L L L H L X X X X X X X X X X X X Notes INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL INVALID Power Down mode exit, all banks idle ILLEGAL X X X 2 2 2 1 2 2 Maintain Power Down Mode INVALID Deep Power Down mode exit Maintain Deep Power Down Mode Refer to the idle State section of the Current State Truth Table Refer to the idle State section of the Current State Truth Table X X X 2 Maintain Self Refresh X X Auto Refresh Op Code Mode Register Set X X Op Code X X X X 1 2 Entry Self Refresh 1 5 3 3 3 4 3 3 3 4 Mode Register Set Power Down 4 Refer to operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200µsec. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA -25 ~ 80 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 3.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=-25 to 85°C) Parameter Symbol Min Typ. Max Unit Note 2.3 2.5 2.7 V 1 Power Supply Voltage VDD Power Supply Voltage VDDQ 1.65 - 2.7 V 1, 2 Input High Voltage VIH 1.40 - VDDQ+0.3 V 1, 2, 3 Input Low Voltage VIL -0.3 - V 1, 2, 3 0.55 Note : 1. All Voltages are referenced to VSS = 0V 2. VDDQ must not exceed the level of VDD 3. Internal VREF = 0.9V AC OPERATING CONDITION (TA=-25 to 85°C, 2.3V ≤VDD ≤2.7V, VSS=0V ) Parameter Symbol AC Input High/Low Level Voltage VIH / VIL Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Vtrip tR / tF Value Unit 0.9*VDDQ/0.2 V 0.5*VDDQ V 1 Note ns Output Timing Measurement Reference Level Voltage Voutref 0.5*VDDQ V Output Load Capacitance for Access Time Measurement CL Note 1 pF 1 Note : 1. Out Put Load Circuit : See the next page Rev. 0.4/Oct. 02 16 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM OUTPUT LOAD CIRCUIT Vtt=0.5*VDDQ Output Zo = 50Ω RT=50Ω 30pF This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM CAPACITANCE (TA=25 C, f=1MHz, HY5xxxxxxF Seires) Parameter Pin Input capacitance Symbol -H -/8/P/S/B Min Max Min Max Unit CLK CI1 TBD TBD 2.5 4.0 pF A0~A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 CI2 TBD TBD 2.5 4.0 pF CI/O TBD TBD 4.0 6.5 pF Data input/output capacitance DQ0 ~ DQ31 DC CHARACTERISTICS I (TA= -25 to 85C) Parameter Input Leakage Current Symbol ILI Output Leakage Current ILO Min Max Unit Note -1 1 µA 1 -1 1 µA 2 Output High Voltage VOH VDDQ - 0.2 - V 3 Output Low Voltage VOL - 0.2 V 4 Note : 1. VIN ≤ VDDQ. All other pins are not tested under VIN=0V. 2. DOUT is disabled. 0 ≤ VOUT ≤ VDDQ 3. IOUT = - 0.1mA 4. IOUT = + 0.1mA Rev. 0.4/Oct. 02 18 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM DC CHARACTERISTICS II (TA= -25 to 85C) Speed Parameter Symbol Test Condition -H -8 -P -S -B TB D 90 75 75 75 Unit Note mA 1 Operating Current IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA Precharge Standby Current in power down mode IDD2P CKE ≤ VIL(max), tCK = 15ns 1.5 IDD2PS CKE ≤ VIL(max), tCK = ∞ 0.6 IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 8 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 5 IDD3P CKE ≤ VIL(max), tCK = 15ns 5 IDD3PS CKE ≤ VIL(max), tCK = ∞ 5 IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 15 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 15 Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active TB D 150 130 130 130 mA 1 Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active TB D 155 155 125 125 mA 2 Self Refresh Current IDD6 CKE ≤ 0.2V See the next page table mA 3 Standby Current in Deep Power Down Mode TBD TBD µA Precharge Standby Current in non power down mode Active Standby Current in power down mode Active Standby Current in non power down mode TBD mA mA mA mA Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II. 3. See the tables of next page for more specific IDD6 current values. - Normal Power : HY5W2A2F / HY57W2A3220T Series - Low Power : HY5W2A2LF / HY57W2A3220LT Series - Super Low Power : HY5W2A2SF / HY57W2A3220ST Series - Standard Part : HY5W22F / HY57W283220T Series Rev. 0.4/Oct. 02 19 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM DC CHARACTERISTICS III - Normal (IDD6) (VDD=2.5V, VDDQ=1.8V & 2.5V, VSS=0V) Temp. ( oC) 85 70 -25~45 Memory Array 4 Banks 700 600 400 Unit 2 Banks 1 Bank 520 440 µA 380 330 µA 310 270 µA DC CHARACTERISTICS III - Low Power (IDD6) (VDD=2.5V, VDDQ=1.8V & 2.5V, VSS=0V) Temp. ( oC) 85 70 -25~45 Memory Array Unit 4 Banks 2 Banks 1 Bank 550 430 450 320 µA 330 280 µA 350 280 250 µA DC CHARACTERISTICS III - Super Low Power (IDD6) (VDD=2.5V, VDDQ=1.8V & 2.5V, VSS=0V) Memory Array Temp. ( oC) 4 Banks 2 Banks 1 Bank 85 370 TBD TBD µA 70 TBD TBD TBD µA TBD TBD TBD µA -25~45 Unit DC CHARACTERISTICS III - Standard part (IDD6) (VDD=2.5V, VDDQ=1.8V & 2.5V, VSS=0V) Temp. ( oC) Memory Array -25~85 < 700 4 Banks Unit µA This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Oct. 02 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Parameter System Clock Cycle Time Symbol H 8 P S B Min Max Min Max Min Max Min Max Min Max CAS Latency=3 tCK3 7.5 1000 8 1000 10 1000 10 1000 15 1000 CAS Latency=2 tCK2 10 10 10 12 15 Unit Note ns ns Clock High Pulse Width tCHW 2.5 - 3 - 3 - 3 - 3.5 - ns 1 Clock Low Pulse Width tCLW 2.5 - 3 - 3 - 3 - 3.5 - ns 1 - 5.4 - 6 - 7 - 7 - 9 ns 2 - 7 - 7 - 7 - 8 - 9 ns Access Time From CAS Latency=3 tAC3 Clock CAS Latency=2 tAC2 Data-out Hold Time tOH 1.5 - 2.0 - 3 - 3 - 3 - ns Data-Input Setup Time tDS 1.5 - 2.0 - 2 - 2 - 2 - ns 1 Data-Input Hold Time tDH 0.8 - 1.0 - 1 - 1 - 1 - ns 1 Address Setup Time tAS 1.5 - 2.0 - 2 - 2 - 2 - ns 1 Address Hold Time tAH 0.8 - 1.0 - 1 - 1 - 1 - ns 1 CKE Setup Time tCKS 1.5 - 2.0 - 2 - 2 - 2 - ns 1 CKE Hold Time tCKH 0.8 - 1.0 - 1 - 1 - 1 - ns 1 Command Setup Time tCS 1.5 - - 2 - 2 - 2 - ns 1 Command Hold Time tCH 0.8 - 2.0 1.0 - 1 - 1 - 1 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1 - 1 - 1 - 1 - 1 - ns 2.7 5.4 2.5 6 3 6 3 6 3 9 ns 2.7 7 2.5 7 3 6 3 6 3 9 ns CLK to Data Output CAS Latency=3 tOHZ3 in High-Z Time CAS Latency=2 tOHZ2 Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1v/ns edge rate, from 0.8v to 0.2v. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev. 0.4/Oct. 02 21 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Symbol H 8 Min Max P S B Min Max Min Max Min Max Min Max Unit RAS Cycle Time tRC 65 - 68 - 70 - 70 - 90 - ns RAS to CAS Delay tRCD 20 - 20 - 20 - 30 - 30 - ns RAS Active Time tRAS 45 RAS Precharge Time tRP 20 - 20 - 20 - 30 - 30 - ns RAS to RAS Bank Active Delay tRRD 15 - 20 - 20 - 20 - 20 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - 1 - tCK Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - 0 - tCK Data-in to Precharge Command tDPL 2 - 1 - 1 - 1 - 1 - tCK Data-In to Active Command tDAL 5 - 3 - 3 - 3 - 3 - tCK DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - tCK DQM to Data-In Mask tDQM 0 - 0 - 0 - 0 - 0 - tCK MRS to New Command tMRD 2 - 2 - 2 - 2 - 2 - tCK Precharge to Data Output High-Z CAS Latency=3 tPROZ3 3 - 3 - 3 - 3 - 3 - tCK CAS Latency=2 tPROZ2 2 Power Down Exit Time tDPE 1 - 1 - 1 - 1 - 1 - tCK Self Refresh Exit Time tSRE 1 - 1 - 1 - 1 - 1 - tCK Refresh Time tREF - 64 - 64 - 64 - 64 - 64 ns 100K 48 100K 2 50 100K 2 50 100K 2 60 100K 2 No te ns tCK 1 Note : 1. A new command can be given tRRC after self refresh exit. Rev. 0.4/Oct. 02 22 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM Special Operation for Low Power Consumption Deep Power Down Mode Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. Full initialization is required when the device exits from Deep Power Down Mode. Truth Table Current State Command CKEn-1 CKEn CS RAS CAS WE Idle Deep Power Down Entry H L L H H L Deep Power Down Deep Power Down Exit L H X X X X Deep Power Down Mode Entry The Deep Power Down Mode is entered by having /CS and /WE held low with /RAS and /CAS high at the rising edge of the clock, while CKE is low. The following diagram illustrates deep power down mode entry. CLK CKE CS RAS CAS WE tRP Precharge if needed Rev. 0.4/Oct. 02 Deep Power Down Entry 23 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM Deep Power Down Mode (Continued) Deep Power Down Mode Exit Sequence The Deep Power Down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command. 1. Maintain NOP input conditions for a minimum of 200µsec 2. Issue precharge commands for all banks of the device 3. Issue 8 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register The following timing diagram illustrates deep power down mode exit sequence. Rev. 0.4/Oct. 02 24 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM PACKAGE INFORMATION (HY57W2A3220T Series) 400mil 86pin Thin Small Outline Package Unit : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 0.50(0.0197) Rev. 0.4/Oct. 02 0.21(0.008) 0.18(0.007) 1.194(0.0470) 0.991(0.0390) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 25 HY5W2A2(L/S)F / HY57W2A3220(L/S)T HY5W22CF / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM PACKAGE INFORMATION (HY5W2A2F Series) 90Ball FBGA with 0.8mm of pin pitch 8.00±.10 Rev. 0.4/Oct. 02 26