16Mx72bits PC100 SDRAM SO DIMM based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh HYM71V16M755HC(L)T8 Series DESCRIPTION The HYM71V16M755HC(L)T8 Series are 16Mx72bits Synchronous DRAM Modules. The modules are composed of nine 16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. The HYM71V16M755HC(L)T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The HYM71V16M755HC(L)T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FEATURES • PC100MHz support • Module bank : one physical bank • 144pin SDRAM SO DIMM • Auto refresh and self refresh • Serial Presence Detect with EEPROM • 4096 refresh cycles / 64ms • 1.25” Height PCB with single sided components • Programmable Burst Length and Burst Type • Single 3.3±0.3V power supply - 1, 2, 4 or 8 or Full page for Sequential Burst • All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Interleave Burst • Data mask function by DQM • SDRAM internal banks : four banks • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HYM71V16M755HCT8-8 125MHz HYM71V16M755HCT8-P 100MHz HYM71V16M755HCT8-S 100MHz HYM71V16M755HCLT8-8 125MHz HYM71V16M755HCLT8-P 100MHz HYM71V16M755HCLT8-S 100MHz Internal Bank Ref. Power SDRAM Package Plating TSOP-II Gold Normal 4 Banks 4K Low Power This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/May. 02 1 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series PIN DESCRIPTION PIN PIN NAME DESCRIPTION CK0, CK1 Clock Inputs The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE0 Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh /S0 Chip Select Enables or disables all inputs except CK, CKE and DQM BA0, BA1 SDRAM Bank Address Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 /RAS, /CAS, /WE Row Address Strobe, Column Address Strobe, Write Enable /RAS, /CAS and /WE define the operation Refer function truth table for details DQM0~DQM7 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ63 Data Input/Output Multiplexed data input / output pin VCC Power Supply (3.3V) Power supply for internal circuits and input buffers VSS Ground Ground SCL SPD Clock Input Serial Presence Detect Clock input SDA SPD Data Input/Output Serial Presence Detect Data input/output SA0~2 SPD Address Input Serial Presence Detect Address Input NC No Connection No connection Rev. 0.1/May. 02 2 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series PIN ASSIGNMENTS FRONT SIDE BACK SIDE FRONT SIDE BACK SIDE PIN NO. NAME PIN NO. NAME PIN NO. NAME PIN NO. 1 VSS 2 VSS 71 NC 72 NAME NC 3 DQ0 4 DQ32 73 NC 74 CK1 5 DQ1 6 DQ33 75 VSS 76 VSS 7 DQ2 8 DQ34 77 NC 78 NC 9 DQ3 10 DQ35 79 NC 80 NC 11 VCC 12 VCC 81 VCC 82 VCC 13 DQ4 14 DQ36 83 DQ16 84 DQ48 15 DQ5 16 DQ37 85 DQ17 86 DQ49 17 DQ6 18 DQ38 87 DQ18 88 DQ50 19 DQ7 20 DQ39 89 DQ19 90 DQ51 21 VSS 22 VSS 91 VSS 92 VSS 23 DQM0 24 DQM4 93 DQ20 94 DQ52 25 DQM1 26 DQM5 95 DQ21 96 DQ53 27 VCC 28 VCC 97 DQ22 98 DQ54 29 A0 30 A3 99 DQ23 100 DQ55 31 A1 32 A4 101 VCC 102 VCC 33 A2 34 A5 103 A6 104 A7 35 VSS 36 VSS 105 A8 106 BA0 37 DQ8 38 DQ40 107 VSS 108 VSS 39 DQ9 40 DQ41 109 A9 110 BA1 41 DQ10 42 DQ42 111 A10/AP 112 A11 43 DQ11 44 DQ43 113 VCC 114 VCC 45 VCC 46 VCC 115 DQM2 116 DQM6 47 DQ12 48 DQ44 117 DQM3 118 DQM7 49 DQ13 50 DQ45 119 VSS 120 VSS 51 DQ14 52 DQ46 121 DQ24 122 DQ56 53 DQ15 54 DQ47 123 DQ25 124 DQ57 55 VSS 56 VSS 125 DQ26 126 DQ58 57 NC 58 NC 127 DQ27 128 DQ59 59 NC 60 NC Voltage Key 61 CK0 62 CKE0 129 VCC 130 VCC 131 DQ28 132 DQ60 133 DQ29 134 DQ61 135 DQ30 136 DQ62 63 VCC 64 VCC 137 DQ31 138 DQ63 65 /RAS 66 /CAS 139 VSS 140 VSS 67 /WE 68 NC 141 SDA 142 SCL 69 /S0 70 NC 143 VCC 144 VCC Rev. 0.1/May. 02 3 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series BLOCK DIAGRAM /S0 DM0 DM4 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 U0 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS U8 DM1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS U4 DM5 /CS U1 DM2 /CS U5 DM6 /CS U2 DM3 /CS U6 DM7 /CS U3 /CS U7 Serial PD BA0-BA1 SCL SDA WP A0 A1 A2 SA0 SA1 SA2 A0 - A12 /RAS /CAS 10 Ohm CLK0/1 10 Ohm U0/U4 A0 - A12 : SDRAMs U0 - U8 /RAS : SDRAMs U0 - U8 /CAS : SDRAMs U0 - U8 CKE0 CKE : SDRAMs U0 - U8 /WE /WE : SDRAMs U0 - U8 VDD U1, U8/U5 Two 0.1uF Capacitors U2/U6 per each SDRAM U3/U7 Rev. 0.1/May. 02 BA0-BA1 : SDRAMs U0 - U8 To all SDRAMs VSS 4 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series SERIAL PRESENCE DETECT BYTE NUMBER FUNCTION DESCRIPTION FUNCTION -8 -P VALUE -S -8 -P # of Bytes Written into Serial Memory at Module Manufacturer 128 Bytes BYTE1 Total # of Bytes of SPD Memory Device 256 Bytes 08h BYTE2 Fundamental Memory Type SDRAM 04h BYTE0 -S 80h BYTE3 # of Row Addresses on This Assembly 12 0Ch BYTE4 # of Column Addresses on This Assembly 10 0Ah BYTE5 # of Module Banks on This Assembly 1 Bank 01h BYTE6 Data Width of This Assembly 72 Bits 48h BYTE7 Data Width of This Assembly (Continued) - 00h BYTE8 Voltage Interface Standard of This Assembly BYTE9 SDRAM Cycle Time @/CAS Latency=3 8ns 10ns 10ns 80h A0h A0h BYTE10 Access Time from Clock @/CAS Latency=3 6ns 6ns 6ns 60h 60h 60h BYTE11 DIMM Configuration Type BYTE12 Refresh Rate/Type LVTTL 1 01h ECC 02h 15.625us / Self Refresh Supported 80h BYTE13 Primary SDRAM Width x8 08h BYTE14 Error Checking SDRAM Width x8 08h BYTE15 Minimum Clock Delay Back to Back Random Column Address BYTE16 Burst Lenth Supported BYTE17 # of Banks on Each SDRAM Device BYTE18 SDRAM Device Attributes, /CAS Lataency BYTE19 SDRAM Device Attributes, /CS Lataency tCCD = 1 CLK 01h 1,2,4,8,Full Page 8Fh 4 Banks 04h /CAS Latency=2,3 06h /CS Latency=0 01h 2 BYTE20 SDRAM Device Attributes, /WE Lataency /WE Latency=0 01h BYTE21 SDRAM Module Attributes Neither Buffered nor Registered 00h BYTE22 SDRAM Device Attributes, General +/- 10% voltage tolerence, Burst Read Single Bit Write, Precharge All, Auto Precharge, Early RAS Precharge 0Eh BYTE23 SDRAM Cycle Time @/CAS Latency=2 8ns 10ns 12ns A0h A0h BYTE24 Access Time from Clock @/CAS Latency=2 6ns 6ns 6ns 60h 60h 60h BYTE25 SDRAM Cycle Time @/CAS Latency=1 - - - 00h 00h 00h BYTE26 Access Time from Clock @/CAS Latency=1 - - - 00h 00h 00h BYTE27 Minimum Row Precharge Time (tRP) 20ns 20ns 20ns 14h 14h 14h BYTE28 Minimum Row Active to Row Active Delay (tRRD) 16ns 20ns 20ns 10h 14h 14h C0h BYTE29 Minimum /RAS to /CAS Delay (tRCD) 20ns 20ns 20ns 14h 14h 14h BYTE30 Minimum /RAS Pulse Width (tRAS) 48ns 50ns 50ns 30h 32h 32h BYTE31 Module Bank Density BYTE32 Command and Address Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h BYTE33 Command and Address Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h BYTE34 Data Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h BYTE35 Data Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h BYTE36 ~61 Superset Information (may be used in future) BYTE62 SPD Revision BYTE63 Checksum for Byte 0~62 BYTE64 Manufacturer JEDEC ID Code BYTE65 ~71 ....Manufacturer JEDEC ID Code BYTE72 Manufacturing Location Rev. 0.1/May. 02 NOTE 128MB 20h - 00h Intel SPD 1.2B 12h - E2h 28h Hynix JEDED ID ADh Unused FFh HSI(Korea Area) HSA (United States Area) HSE (Europe Area) HSJ (Japan Area) HSS(Singapore) Asia Area 0*h 1*h 2*h 3*h 4*h 5*h 3, 8 38h 9 5 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series Continued BYTE NUMBER FUNCTION DESCRIPTION BYTE73 Manufacturer’s Part Number (Component) BYTE74 Manufacturer’s Part Number (128Mb based) BYTE75 Manufacturer’s Part Number (Voltage Interface) BYTE76 Manufacturer’s Part Number (Memory Width) BYTE77 ....Manufacturer’s Part Number (Memory Width) BYTE78 Manufacturer’s Part Number (Module Type) BYTE79 Manufacturer’s Part Number (Data Width) BYTE80 ....Manufacturer’s Part Number (Data Width) BYTE81 Manufacturer’s Part Number (Refresh, SDRAM Bank) FUNCTION -8 -P VALUE -S -8 -P -S NOTE 7 (SDRAM) 37h 4, 5 1 31h 4, 5 V (3.3V, LVTTL) 56h 4, 5 1 31h 4, 5 6 36h 4, 5 M (SO DIMM) 4Dh 4, 5 7 37h 4, 5 5 35h 4, 5 5 (4K Refresh, 4Banks) 35h 4, 5 BYTE82 Manufacturer’s Part Number (Manufacturing Site) H 48h 4, 5 BYTE83 Manufacturer’s Part Number (Generation) C 43h 4, 5 BYTE84 Manufacturer’s Part Number (Package Type) BYTE85 Manufacturer’s Part Number (Component Configuration) BYTE86 Manufacturer’s Part Number (Hyphent) BYTE87 Manufacturer’s Part Number (Min. Cycle Time) BYTE88 ~90 Manufacturer’s Part Number T 54h 4, 5 8 (x8 based) 48h 4, 5 - (Hyphen) 8 2Dh P S 38h 4, 5 50h 53h 4, 5 Blanks 20h 4, 5 BYTE91 Revision Code (for Component) Process Code - 4, 6 BYTE92 ....Revision Code (for PCB) Process Code - 4, 6 BYTE93 Manufacturing Date BYTE94 ....Manufacturing Date BYTE95 ~98 BYTE99 ~125 Assembly Serial Number Manufacturer Specific Data (may be used in future) BYTE126 System Frequency Support BYTE127 Intel Specification Details for 100MHz Support BYTE128 ~256 Unused Storage Locations Year - 3, 6 Work Week - 3, 6 Serial Number - 6 None 00h 100MHz 64h CFh Refer to Note7 7, 8 CFh - CDh 7, 8 00h Note 1. The : bank address is excluded 2. 1, 2, 4, 8 for Interleave Burst Type 3. BCD adopted 4. ASCII adopted 5. Basically Hynix writes Part No. except for ‘HYM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. Not fixed but dependent 7. CK0, CK1 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support 8. Refer to Intel SPD Specification 1.2B 9. Refer to HSI Web site Byte 84~88 for L-Part BYTE NUMBER FUNCTION DESCRIPTION BYTE84 Manufacturer’s Part Number (Power) BYTE85 Manufacturer’s Part Number (Package Type) BYTE86 Manufacturer’s Part Number (Component Configuration) BYTE87 Manufacturer’s Part Number (Hyphent) BYTE88 Manufacturer’s Part Number (Min. Cycle Time) Rev. 0.1/May. 02 FUNCTION -8 -P VALUE -S -8 L -S 4Ch NOTE 4, 5 T 54h 4, 5 8 (x8 based) 38h 4, 5 - (Hyphen) 8 -P P 2Dh S 38h 50h 4, 5 53h 4, 5 6 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 8 W Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITION (TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1 Input High voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2 Input Low voltage VIL -0.3 0 0.8 V 1,3 Note Note : 1.All voltages are referenced to VSS = 0V 2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration. AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V) Parameter Symbol Value Unit AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 1.4 V CL 50 pF Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement 1 Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit Rev. 0.1/May. 02 7 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series CAPACITANCE (TA=25°C, f=1MHz) -8/P/S Parameter Input Capacitance Data Input / Output Capacitance Pin Symbol Unit Min Max CK0, CK2 CI1 25 45 pF CKE0 CI2 35 55 pF /S0, /S2 CI3 25 40 pF A0~11, BA0, BA1 CI4 40 60 pF /RAS, /CAS, /WE CI5 40 60 pF DQM0~DQM7 CI6 5 20 pF DQ0 ~ DQ63 CI/O 5 20 pF OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF DC Output Load Circuit Rev. 0.1/May. 02 50pF AC Output Load Circuit 8 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V) Parameter Symbol Min. Max Unit Note -8 8 uA 1 Input Leakage Current ILI Output Leakage Current ILO -1 1 uA Output High Voltage VOH 2.4 - V IOH = -2mA Output Low Voltage VOL - 0.4 V IOL = +2mA 2 Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6 DC CHARACTERISTICS II Parameter Operating Current Symbol IDD1 Speed Test Condition Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA -8 -P -S 800 800 800 CKE ≤ VIL(max), tCK = min 16 CKE ≤ VIL(max), tCK = ∞ 16 CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 160 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 80 IDD3P CKE ≤ VIL(max), tCK = min 56 IDD3PS CKE ≤ VIL(max), tCK = ∞ 56 IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 320 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 320 Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V IDD2P Precharge Standby Current in Power Down Mode IDD2PS IDD2N Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Unit Note mA 1 mA mA mA mA CL=3 880 800 800 CL=2 800 800 800 mA 1 1600 mA 2 16 mA 3 8 mA 4 Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HYM71V16M755HCT8-8/P/S 4. HYM71V16M755HCLT8-8/P/S Rev. 0.1/May. 02 9 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -8 Parameter CAS Latency = 3 tCK3 Max 8 Min Max 10 1000 Min 10 1000 ns 1000 10 Clock High Pulse Width tCHW 3 - 3 - 3 - ns 1 Clock Low Pulse Width tCLW 3 - 3 - 3 - ns 1 CAS Latency = 3 tAC3 - 6 - 6 - 6 ns CAS Latency = 2 tAC2 - 6 - 6 - 6 ns Data-Out Hold Time tOH 3 - 3 - 3 - ns Data-Input Setup Time tDS 2 - 2 - 2 - ns 1 Data-Input Hold Time tDH 1 - 1 - 1 - ns 1 Address Setup Time tAS 2 - 2 - 2 - ns 1 Address Hold Time tAH 1 - 1 - 1 - ns 1 CKE Setup Time tCKS 2 - 2 - 2 - ns 1 CKE Hold Time tCKH 1 - 1 - 1 - ns 1 Command Setup Time tCS 2 - 2 - 2 - ns 1 Command Hold Time tCH 1 - 1 - 1 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1 - 1 - 1 - ns CAS Latency = 3 tOHZ3 3 6 3 6 3 6 ns CAS Latency = 2 tOHZ2 3 6 3 6 3 6 ns CLK to Data Output in High-Z Time 10 Note Max tCK2 Access Time From Clock CAS Latency = 2 -S Unit Min System Clock Cycle Time -P Symbol 12 ns 2 Note : 1.Assume tR / tF (input rise and fall time ) is 1ns If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter Rev. 0.1/May. 02 10 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series AC CHARACTERISTICS II -8 Parameter -P -S Symbol Unit Min Max Min Max Min Max Operation tRC 68 - 70 - 70 - ns Auto Refresh tRRC 68 - 70 - 70 - ns RAS to CAS Delay tRCD 20 - 20 - 20 - ns RAS Active Time tRAS 48 100K 50 100K 50 100K ns RAS Precharge Time tRP 20 - 20 - 20 - ns RAS to RAS Bank Active Delay tRRD 16 - 20 - 20 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - 0 - CLK Data-In to Precharge Command tDPL 1 - 1 - 1 - CLK Data-In to Active Command tDAL 4 - 3 - 3 - CLK DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - CLK CAS Latency = 3 tPROZ3 3 - 3 - 3 - CLK CAS Latency = 2 tPROZ2 2 - 2 - 2 - CLK Power Down Exit Time tPDE 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 ms Note RAS Cycle Time Precharge to Data Output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.1/May. 02 11 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series DEVICE OPERATING OPTION TABLE HYM71V16M755HC(L)T8-8 CAS Latency tRCD tRAS tRC tRP tAC tOH 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns HYM71V16M755HC(L)T8-P CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns HYM71V16M755HC(L)T8-S CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns Rev. 0.1/May. 02 12 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series COMMAND TRUTH TABLE CKEn-1 CKE n CS RAS CAS WE DQ M Mode Register Set H X L L L L X OP code No Operation H X H X X X L H H H X X Bank Active H X L L H H X H X L H L H X CA H X L H L L X CA H X L L H L X X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L L H X X Burst-Read-Single-WRITE H X L L L L X A9 Pin High (Other Pins OP code) Entry H L L L L H X Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H H X X X L V V V Command Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Self Refresh X 1 Precharge power down Clock Suspend Exit L H Entry H L Exit L H X X A10/ AP ADDR RA BA Note V L H L H V V H X L V MRS Mode X X X X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation 3. The burst read sigle write mode is entered by programming the Write burst mode bit (A9) in the mode register to a logic 1. Rev. 0.1/May. 02 13 PC100 SDRAM SO DIMM HYM71V16M755HC(L)T8 Series PACKAGE DEMENSION 2.66 2.50 2-R 0.078 Min 0.24 0.13 . . 0.91 . 0.790 . . 1.250 0.16±0.039 1.29 2 - 0.07 0.18 0.083 0.10 Z Y . 0.15 . . . 0.01±Max 0.16±0.0039 0.06±0.0039 0 .157 Min 0 .024±0.001 0 .125 Min 0 .10 0.150 Max 0.030 TYP 0.04±0.0039 Detail Z Tolerances : ±0.005 unless otherwise specified Rev. 0.1/May. 02 Detail Y Units : Inches 14