16x64 bits PC133 SDRAM SO DIMM based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh HYM71V63M1601 X-Series DESCRIPTION The Hyundai HYM71V63M1601 X-Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 8Mx16bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB. The HYM71V63M1601 X-Series are Small Outline Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The HYM71V63M1601 X-Series are offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FEATURES • PC133/PC100MHz support • SDRAM internal banks : four banks • 144pin SDRAM SO DIMM • Module bank : two physical bank • Serial Presence Detect with EEPROM • Auto refresh and self refresh • 1.25” (31.75mm) Height PCB with Double Sided components • 4096 refresh cycles / 64ms • Single 3.3 ± 0.3V power supply • All devices pins are compatible with LVTTL interface • Data mask function by DQM • Programmable Burst Length and Burst Type -. 1, 2, 4, 8 or Full Page for Sequential Burst -. 1, 2, 4 or 8 for Interleave Burst • Programmable /CAS Latency -. 2, 3 Clocks ORDERING INFORMATION PART NO. MAX. FREQUENCY HYM71V63M1601TX-75 133MHz HYM71V63M1601LTX-75 133MHz INTERNAL BANK REF. 4 Banks 4K POWER Normal SDRAM PACKAGE PLATING TSOP-II Gold Low Power This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/Dec.99 1999 Hyundai MicroElectronics PC133 SDRAM SO DIMM HYM71V63M1601 X-Series PIN DESCRIPTION PIN NAME DESCRIPTION CK0, CK1 Clock Inputs The System Clock Input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE0, CKE1 Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. /S0, /S1 Chip Select Enables or disables all inputs except CK, CKE and DQM. BA0, BA1 SDRAM Bank Address A0~A11 Address Inputs /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DQM0~DQM7 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode. DQ0~DQ63 Data Input/Output Multiplexed data input/output pins VCC Power Supply (3.3V) Power supply for internal circuits and input/output buffers VSS Ground Ground SCL SPD Clock Input Serial Presence Detect Clock Input SDA SPD Data Input/Output Serial Presence Detect Data input/output NC No Connect No Connect or Don’ t Use Rev. 1.1/Dec.99 Select bank to be activated during /RAS activity. Select bank to be read/written during /CAS activity Row address : RA0~RA11, Column address : CA0~CA8 Auto-precharge flag : A10 /RAS define the operation. Refer to the function truth table for details. /CAS define the operation. Refer to the function truth table for details. /WE define the operation. Refer to the function truth table for details. 2 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series PIN ASSIGNMENTS FRONT SIDE BACK SIDE FRONT SIDE BACK SIDE PIN NO. NAME PIN NO. NAME PIN NO. NAME PIN NO. 1 VSS 2 VSS 71 /S1 72 NC 3 5 DQ0 DQ1 4 6 DQ32 DQ33 73 75 NC VSS 74 76 CK1 VSS 7 DQ2 8 DQ34 77 NC 78 NC 9 DQ3 10 DQ35 79 NC 80 NC 11 VCC 12 VCC 81 VCC 82 VCC 13 15 DQ4 DQ5 14 16 DQ36 DQ37 83 85 DQ16 DQ17 84 86 DQ48 DQ49 17 DQ6 18 DQ38 87 DQ18 88 DQ50 19 DQ7 20 DQ39 89 DQ19 90 DQ51 21 VSS 22 VSS 91 VSS 92 VSS 23 25 DQM0 DQM1 24 26 DQM4 DQM5 93 95 DQ20 DQ21 94 96 DQ52 DQ53 27 VCC 28 VCC 97 DQ22 98 DQ54 29 A0 30 A3 99 DQ23 100 DQ55 31 A1 32 A4 101 VCC 102 VCC 33 35 A2 VSS 34 36 A5 VSS 103 105 A6 A8 104 106 A7 BA0 37 DQ8 38 DQ40 107 VSS 108 VSS 39 DQ9 40 DQ41 109 A9 110 BA1 41 DQ10 42 DQ42 111 A10/AP 112 A11 43 45 DQ11 VCC 44 46 DQ43 VCC 113 115 VCC DQM2 114 116 VCC DQM6 47 DQ12 48 DQ44 117 DQM3 118 DQM7 49 DQ13 50 DQ45 119 VSS 120 VSS 51 53 DQ14 DQ15 52 54 DQ46 DQ47 121 123 DQ24 DQ25 122 124 DQ56 DQ57 55 VSS 56 VSS 125 DQ26 126 DQ58 57 NC 58 NC 127 DQ27 128 DQ59 59 NC 60 NC 129 VCC 130 VCC 131 133 DQ28 DQ29 132 134 DQ60 DQ61 Voltage Key NAME 61 CK0 62 CKE0 135 DQ30 136 DQ62 63 VCC 64 VCC 137 DQ31 138 DQ63 65 /RAS 66 /CAS 139 VSS 140 VSS 67 69 /WE /S0 68 70 CKE1 NC 141 143 SDA VCC 142 144 SCL VCC Rev. 1.1/Dec.99 3 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series BLOCK DIAGRAM Note : 1. The serial resistor values of DQs are 10 Ohms. Rev. 1.1/Dec.99 4 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series SERIAL PRESENCE DETECT BYTE FUNCTION FUNCTION VALUE NUMBER DESCRIBED -75 -75 BYTE0 # of Bytes Written into Serial Memory at Module Manufacturer 128 Bytes 80h BYTE1 Total # of Bytes of SPD Memory Device 256 Bytes 08h BYTE2 Fundamental Memory Type BYTE3 SDRAM 04h # of Row Addresses on This Assembly 12 0Ch BYTE4 # of Column Addresses on This Assembly 9 09h BYTE5 # of Module Banks on This Assembly 2 Banks 02h BYTE6 Data Width of This Assembly 64 Bits 40h BYTE7 Data Width of This Assembly (Continued) - 00h BYTE8 Voltage Interface Standard of This Assembly LVTTL 01h BYTE9 SDRAM Cycle Time @ /CAS Latency=3 7.5ns 75h BYTE10 Access Time from Clock @ /CAS Latency=3 5.4ns 54h BYTE11 DIMM Configuration Type None 00h 15.625µs / Self Refresh Supported 80h BYTE12 Refresh Rate/Type BYTE13 Primary SDRAM Width BYTE14 Error Checking SDRAM Width BYTE15 Minimum Clock Delay Back to Back Random Column Address BYTE16 Burst Lengths Supported BYTE17 # of Banks on Each SDRAM Device BYTE18 SDRAM Device Attributes, CAS # Latency BYTE19 SDRAM Device Attributes, CS # Latency BYTE20 SDRAM Device Attributes, Write Latency BYTE21 SDRAM Module Attributes x16 10h None 00h tCCD = 1 CLK 01h 1,2,4,8,Full Page 8Fh 4 Banks 04h /CAS Latency=2,3 06h /CS Latency=0 01h /WE Latency=0 01h Neither Buffered nor Registered 00h +/-10% voltage tolerance, Burst Read Single bit Write, Precharge All, Auto Precharge, Early RAS Precharge 0Eh BYTE22 SDRAM Device Attributes, General BYTE23 SDRAM Cycle Time @ /CAS Latency=2 10ns A0h BYTE24 Access Time from Clock @ /CAS Latency=2 6ns 60h BYTE25 SDRAM Cycle Time @ /CAS Latency=1 - 00h BYTE26 Access Time from Clock @ /CAS Latency=1 - 00h BYTE27 Minimum Row Precharge Time (tRP) 20ns 14h BYTE28 Minimum Row Active to Row Active Delay (tRRD) 15ns 0Fh BYTE29 Minimum /RAS to /CAS Delay (tRCD) 20ns 14h BYTE30 Minimum /RAS Pulse width (tRAS) 45ns 2Dh BYTE31 Module Bank Density 64MB 10h BYTE32 Command and Address Signal Input Setup Time 1.5ns 15h BYTE33 Command and Address Signal Input Hold Time 0.8ns 08h BYTE34 Data Signal Input Setup Time 1.5ns 15h BYTE35 Data Signal Input Hold Time 0.8ns 08h BYTE36 –61 Superset Information (may be used in future) - 00h BYTE62 SPD Revision BYTE63 Checksum for Bytes 0~62 BYTE64 Manufacturer JEDEC ID Code BYTE65 ~71 ....Manufacturer JEDEC ID Code BYTE72 Manufacturing Location Rev. 1.1/Dec.99 Intel SPD 1.2 12h - E7h Hyundai JEDEC ID ADh Unused FFh HEI (Korea) HEA (United States) HEU (Europe) NOTE 1 2 3, 8 01h 02h 03h 5 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series Continued BYTE FUNCTION FUNCTION VALUE NUMBER DESCRIBED -75 -75 7 (SDRAM) 37h 4, 5 1 31h 4, 5 V (3.3V, LVTTL) 56h 4, 5 NOTE BYTE73 Manufacturer’ s Part Number (Component) BYTE74 Manufacturer’ s Part Number (128Mb based) BYTE75 Manufacturer’ s Part Number (Voltage Interface) BYTE76 Manufacturer’ s Part Number (Data Width) 6 36h 4, 5 BYTE77 ....Manufacturer’ s Part Number (Data Width) 3 33h 4, 5 BYTE78 Manufacturer’ s Part Number (Module Type) M 4Dh 4, 5 BYTE79 Manufacturer’ s Part Number (Memory Depth) 1 31h 4, 5 BYTE80 … .Manufacturer’ s Part Number (Memory Depth) 6 36h 4, 5 BYTE81 Manufacturer’ s Part Number (Refresh) 0 (4K Refresh) 30h 4, 5 BYTE82 Manufacturer’ s Part Number (Internal Banks) 1 (4 Banks) 31h 4, 5 BYTE83 Manufacturer’ s Part Number (Package Type) T (TSOPII) 54h 4, 5 BYTE84 Manufacturer’ s Part Number (Module Type) X (x16 based) 58h 4, 5 BYTE85 Manufacturer’ s Part Number (Hyphen) - (Hyphen) 2Dh 4, 5 BYTE86 Manufacturer’ s Part Number (Min. Cycle Time) 7 37h 4, 5 BYTE87 ....Manufacturer’ s Part Number (Min. Cycle Time) 5 35h 4, 5 BYTE88 ~90 Manufacturer’ s Part Number Blanks 20h 4, 5 BYTE91 Revision Code (for Component) Process Code - 4, 6 BYTE92 ....Revision Code (for PCB) Process Code - 4, 6 BYTE93 Manufacturing Date Work Week - 3, 6 BYTE94 ....Manufacturing Date Year - 3, 6 BYTE95 ~98 Assembly Serial Number Serial Number - 6 BYTE99 ~125 Manufacturer Specific Data (may be used in future) None 00h BYTE126 Reserved Refer to Note9 64h 8, 9 BYTE127 Reserved Refer to Note9 C7h 7, 8, 9 BYTE128 ~256 Unused Storage Locations - 00h Note: 1. The bank address is excluded. 2. 1,2,4,8 for Interleave Burst Type 3. BCD adopted. 4. ASCII adopted. 5. Basically HYUNDAI writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently. 6. Not fixed but dependent. 7. CLK0, CLK1 connected on the DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support 8. Refer to most recent version Intel and JEDEC SPD Specification. 9. These values are applied to PC100 applicationsonly per Intel PC SDRAM specification BYTE83~88 for L-Part (HYM71V63M1601LTX) BYTE FUNCTION FUNCTION VALUE NUMBER DESCRIBED -75 -75 L (Low Power) 4Ch T (TSOPII) 54h 4, 5 X (x16 based) 58h 4, 5 4, 5 NOTE BYTE83 Manufacturer’ s Part Number (Power) BYTE84 Manufacturer’ s Part Number (Package Type) BYTE85 Manufacturer’ s Part Number (Module Type) BYTE86 Manufacturer’ s Part Number (Hyphen) - (Hyphen) 2Dh BYTE87 Manufacturer’ s Part Number (Min. Cycle Time) 7 37h 4, 5 BYTE88 ....Manufacturer’ s Part Number (Min. Cycle Time) 5 35h 4, 5 Rev. 1.1/Dec.99 4, 5 6 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT 0 ~ 70 °C Ambient Temperature TA Storage Temperature TSTG -55 ~ 125 °C Voltage on any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 MA Power Dissipation PD 4 W Soldering Temperature · Time TSOLDER 260 · 10 °C · Sec Note : Operation at above absolute maximum can adversely affect device reliability. DC OPERATING CONDITION (TA = 0 to 70°C) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Power Supply Voltage VCC 3.0 3.3 3.6 V 1 Input High Voltage VIH 2.0 3.0 VCC + 0.3 V 1, 2 Input Low Voltage VIL – 0.3 0 0.8 V 1, 3 Note : 1. All voltage are referenced to VSS = 0V. 2. VIH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration. 3. VIL (min) is acceptable –2.0V AC pulse width with ≤ 3ns of duration. AC OPERATING CONDITION (TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V) PARAMETER SYMBOL VALUE UNIT 2.4 / 0.4 V 1.4 V AC Input High / Low Level Voltage VIH / VIL Input Timing Measurement Reference Level Voltage Vtrip Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 1.4 V Output Load Capacitance for Access Time Measurement CL *Note pF Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output circuit. Rev. 1.1/Dec.99 7 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series CAPACITANCE (TA = 25°C, f = 1MHz) PARAMETER Input Capacitance Data Input/Output Capacitance PIN SYMBOL MIN MAX TYP. UNIT CK0, CK1 CIN1 20 35 - pF CKE0, CKE1 CIN2 20 30 - pF /S0, /S1 CIN3 20 35 - pF A0~A11, BA0, BA1 CIN4 30 50 - pF /RAS, /CAS, /WE CIN5 30 50 - pF DQM0~DQM7 CIN6 15 20 - pF DQ0~DQ63 CI/O 15 20 - pF OUTPUT LOAD CIRCUIT Rev. 1.1/Dec.99 8 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series DC CHARACTERISTICS I (TA = 0 to 70°C, VDD = 3.3 ± 0.3V) PARAMETER SYMBOL MIN MAX UNIT NOTE Input Leakage Current ILI -8 8 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -4mA Output Low Voltage VOL - 0.4 V IOL = +4mA Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V. 2. DOUT is disabled. VOUT = 0 to 3.6V. DC CHARACTERISTICS II (TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V) SPEED PARAMETER SYMBOL TEST CONDITION UNIT NOTE 1040 mA 1 -75 Operating Current Precharge Standby Current in Power Down Mode IDD1 Burst Length = 1, One bank active tRC ≥ tRC(min), IOL = 0mA IDD2P CKE ≤ VIL(max), tCK = min 16 mA IDD2PS CKE ≤ VIL(max), tCK = ∞ 12 mA IDD2N CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V 160 mA IDD2NS CKE ≥ VIH(max), tCK = ∞ Input signals are stable. 80 mA IDD3P CKE ≤ VIL(max), tCK = min 56 mA IDD3PS CKE ≤ VIL(max), tCK = ∞ 56 mA IDD3N CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V 320 mA IDD3NS CKE ≥ VIH(max), tCK = ∞ Input signals are stable. 320 mA Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode tCK ≥ tCK(min), IOL = 0mA Burst Mode Operating Current IDD4 Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V All banks active CL = 3 1280 CL = 2 880 mA 1 2400 mA 2 16 mA 3 6.4 mA 4 Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II. 3. HYM71V63M1601TX-75 4. HYM71V63M1601LTX-75 Rev. 1.1/Dec.99 9 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -75 PARAMETER SYMBOL UNIT MIN /CAS Latency = 3 tCK3 7.5 /CAS Latency = 2 tCK2 10 Clock High Pulse Width tCHW Clock Low Pulse Width System Clock Cycle Time NOTE MAX 1000 ns 2.5 - ns I tCLW 2.5 - ns I /CAS Latency = 3 tAC3 - 5.4 ns 2 /CAS Latency = 2 tAC2 - 6 Data-Out Hold Time tOH 2.7 - ns Data-Input Setup Time tDS 1.5 - ns 1 Data-Input Hold Time tDH 0.8 - ns 1 Address Setup Time tAS 1.5 - ns 1 Address Hold Time tAH 0.8 - ns 1 CKE Setup Time tCKS 1.5 - ns 1 CKE Hold Time tCKH 0.8 - ns 1 Command Setup Time tCS 1.5 - ns 1 Command Hold Time tCH 0.8 - ns 1 Access Time from Clock CLK to Data Output in Low-Z time tOLZ 1 - ns CLK to Data Output in High-Z time /CAS Latency = 3 tOHZ3 2.7 5.4 ns /CAS Latency = 2 tOHZ2 3 6 ns Note : Assume tR / tF (input rise and fall time ) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2. Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter Rev. 1.1/Dec.99 10 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series AC CHARACTERISTICS II -75 PARAMETER SYMBOL UNIT MIN Operation tRC 65 Auto Refresh tRRC 65 /RAS to /CAS Delay tRCD /RAS Active Time /RAS Time Cycle - ns 20 - ns tRAS 45 100K ns /RAS Precharge Time tRP 20 - ns /RAS to /RAS Bank Active Delay tRRD 15 - ns /CAS to /CAS Delay tCCD 1 - CLK Write Command to Data-in Delay tWTL 0 - CLK Data-in to Precharge Command tDPL 2 - CLK Data-in to Active Command tDAL 5 - CLK DQM to Data-out Hi-Z tDQZ 2 - CLK DQM to Data-in Mask tDQM 0 - CLK MRS to New Command tMRD 2 - CLK /CAS Latency = 3 tPROZ3 3 - /CAS Latency = 2 tPROZ2 2 - Power Down Exit Time tPDE 1 - CLK Self Refresh Exit Time tSRE 1 - CLK Refresh Time tREF - 64 ms Precharge to Data Output Hi-Z NOTE MAX CLK 1 Note : 1. A new command can be given tRRC after self refresh exit. Rev. 1.1/Dec.99 11 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series OPERATING OPTION TABLE HYM71V63M1601TX/LTX-75 /CAS LATENCY tRCD tRAS tRC tRP tAC tOH 133MHz (7.5ns) 3CLKS 3CLKS 6CLKS 9CLKS 3CLKS 5.4ns 2.7ns 125MHz (8.0ns) 3CLKS 3CLKS 6CLKS 9CLKS 3CLKS 6ns 3ns 100MHz (10.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns COMMAND TRUTH TABLE A10/ AP CKEn-1 CKEn /CS /RAS /CAS /WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR RA BA NOTE V Read L CA V Read with Autoprecharge H Write L H X L H L L X CA V Write with Autoprecharge H Precharge All Banks H X L L H L X Precharge Selected Bank Burst Stop H X DQM H Auto Refresh H H L L L Entry H L L L H X Exit L H H H H L X X V X H X X L H X X X X Self Refresh Entry L X L V X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge Power Down H X 1 X X Exit Entry L H H X L X Clock Suspend X Exit L H X X Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high. 2. X = Don’ t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code, NOP = No operation Rev. 1.1/Dec.99 12 PC133 SDRAM SO DIMM HYM71V63M1601 X-Series PACKAGE DIMENSIONS Rev. 1.1/Dec.99 13