ETC HYM76V8C735HGT8-K

8Mx72 bits
PC133 SDRAM Registered DIMM
with PLL, based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM76V8C735HGT8 Series
DESCRIPTION
The Hynix HYM76V8C735HGT8 Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine
8Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin
glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM76V8C735HGT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes
memory. The Hyundai HYM76V8C735HGT8 Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
•
PC133/PC100MHz support
•
SDRAM internal banks : four banks
•
168pin SDRAM Unbuffered DIMM
•
Module bank : one physical bank
•
Serial Presence Detect with EEPROM
•
Auto refresh and self refresh
•
1.50” (38.10mm) Height PCB with double sided
components
•
4096 refresh cycles / 64ms
•
Programmable Burst Length and Burst Type
•
Single 3.3±0.3V power supply
•
All device pins are compatible with LVTTL interface
•
Data mask function by DQM
- 1, 2, 4 or 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock
Frequency
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
133MHz
4 Banks
4K
Normal
TSOP-II
Gold
HYM76V8C735HGT8-K
HYM76V8C735HGT8-H
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.3/Apr.01
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CK0~CK3
Clock Inputs
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE0
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
/S0, /S2
Chip Select
Enables or disables all inputs except CK, CKE and DQM
BA0, BA1
SDRAM Bank Address
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
/RAS, /CAS, /WE
Row Address Strobe, Column
Address Strobe, Write Enable
/RAS, /CAS and /WE define the operation
Refer function truth table for details
REGE
Register Enable
Register Enable pin which permits the DIMM to operateion in Buffered Mode
when REGE input is Low, in Registered Mode when REGE input is High
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ63
Data Input/Output
Multiplexed data input / output pin
CB0 ~ CB7
Check Bit Input/Output
Check bits for ECC
VCC
Power Supply (3.3V)
Power supply for internal circuits and input buffers
V SS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
SA0~2
SPD Address Input
Serial Presence Detect Address Input
WP
Write Protect for SPD
Write Protect for Serial Presence Detect on DIMM
NC
No Connection
No connection
Rev. 0.3/Apr.01
2
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
PIN NO.
NAME
PIN NO.
1
VSS
2
DQ0
3
FRONT SIDE
BACK SIDE
NAME
PIN NO.
NAME
PIN NO.
NAME
85
VSS
41
VCC
125
*CK1
86
DQ32
42
CK0
126
NC
DQ1
87
DQ33
43
VSS
127
VSS
4
DQ2
88
DQ34
44
NC
128
CKE0
5
DQ3
89
DQ35
45
/S2
129
NC
6
VCC
90
VCC
46
DQM2
130
DQM6
7
DQ4
91
DQ36
47
DQM3
131
DQM7
8
DQ5
92
DQ37
48
NC
132
NC
9
DQ6
93
DQ38
49
VCC
133
VCC
10
DQ7
94
DQ39
50
NC
134
NC
51
NC
135
NC
52
CB2
136
CB6
CB7
Architecture Key
11
DQ8
95
DQ40
53
CB3
137
12
VSS
96
VSS
54
VSS
138
VSS
13
DQ9
97
DQ41
55
DQ16
139
DQ48
14
DQ10
98
DQ42
56
DQ17
140
DQ49
15
DQ11
99
DQ43
57
DQ18
141
DQ50
16
DQ12
100
DQ44
58
DQ19
142
DQ51
17
DQ13
101
DQ45
59
VCC
143
VCC
18
VCC
102
VCC
60
DQ20
144
DQ52
19
DQ14
103
DQ46
61
NC
145
NC
20
DQ15
104
DQ47
62
NC
146
NC
21
CB0
105
CB4
63
NC
147
REGE
22
CB1
106
CB5
64
VSS
148
VSS
23
VSS
107
VSS
65
DQ21
149
DQ53
24
NC
108
NC
66
DQ22
150
DQ54
25
NC
109
NC
67
DQ23
151
DQ55
26
VCC
110
VCC
68
VCC
152
VCC
27
/WE
111
/CAS
69
DQ24
153
DQ56
28
DQM0
112
DQM4
70
DQ25
154
DQ57
29
DQM1
113
DQM5
71
DQ26
155
DQ58
30
/S0
114
NC
72
DQ27
156
DQ59
31
NC
115
/RAS
73
VCC
157
VCC
32
VSS
116
VSS
74
DQ28
158
DQ60
33
A0
117
A1
75
DQ29
159
DQ61
34
A2
118
A3
76
DQ30
160
DQ62
35
A4
119
A5
77
DQ31
161
DQ63
36
A6
120
A7
78
VSS
162
VSS
37
A8
121
A9
79
*CK2
163
*CK3
38
A10/AP
122
BA0
80
NC
164
NC
39
BA1
123
A11
81
WP
165
SA0
40
VCC
124
VCC
82
SDA
166
SA1
83
SCL
167
SA2
84
VCC
168
VCC
Voltage Key
Note : * CK1 ~ CK3 are connected with termination R/C (Rsfer to the block diagram)
Rev. 0.3/Apr.01
3
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10ohms
2. The padding capacitance of termination R/C for CK1~CK3 is 12pF
Rev. 0.3/Apr.01
4
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
FUNCTION
DESCRIPTION
FUNCTION
VALUE
-K
-H
-K
-H
BYTE0
# of Bytes Written into Serial Memory at Module
Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
SDRAM
04h
BYTE3
# of Row Addresses on This Assembly
12
0Ch
BYTE4
# of Column Addresses on This Assembly
9
09h
BYTE5
# of Module Banks on This Assembly
1 Bank
01h
BYTE6
Data Width of This Assembly
72 Bits
48h
BYTE7
Data Width of This Assembly (Continued)
-
00h
BYTE8
Voltage Interface Standard of This Assembly
LVTTL
01h
BYTE9
SDRAM Cycle Time @/CAS Latency=3
7.5ns
7.5ns
75h
BYTE10
Access Time from Clock @/CAS Latency=3
5.4ns
5.4ns
54h
BYTE11
DIMM Configuration Type
BYTE12
Refresh Rate/Type
BYTE13
Primary SDRAM Width
BYTE14
Error Checking SDRAM Width
BYTE15
Minimum Clock Delay Back to Back Random Column
Address
BYTE16
Burst Lenth Supported
BYTE17
# of Banks on Each SDRAM Device
BYTE18
SDRAM Device Attributes, /CAS Lataency
BYTE19
BYTE20
BYTE21
1
75h
54h
ECC
02h
15.625us
/ Self Refresh Supported
80h
x8
08h
x8
08h
tCCD = 1 CLK
01h
1,2,4,8,Full Page
8Fh
4 Banks
04h
/CAS Latency=2,3
06h
SDRAM Device Attributes, /CS Lataency
/CS Latency=0
01h
SDRAM Device Attributes, /WE Lataency
/WE Latency=0
01h
SDRAM Module Attributes
Registered/Buffered inputs, with PLL
1Fh
BYTE22
SDRAM Device Attributes, General
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
0Eh
BYTE23
SDRAM Cycle Time @/CAS Latency=2
7.5ns
10
75h
A0h
BYTE24
Access Time from Clock @/CAS Latency=2
5.7ns
6
54h
60h
BYTE25
SDRAM Cycle Time @/CAS Latency=1
-
-
00h
00h
BYTE26
Access Time from Clock @/CAS Latency=1
-
-
00h
00h
BYTE27
Minimum Row Precharge Time (tRP)
20ns
20ns
14h
14h
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
15ns
15ns
0Fh
0Fh
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
20ns
20ns
14h
14h
BYTE30
Minimum /RAS Pulse Width (tRAS)
45ns
45ns
2Dh
2Dh
BYTE31
Module Bank Density
BYTE32
Command and Address Signal Input Setup Time
1.5ns
1.5ns
15h
15h
BYTE33
Command and Address Signal Input Hold Time
0.8ns
0.8ns
08h
08h
BYTE34
Data Signal Input Setup Time
1.5ns
1.5ns
15h
15h
BYTE35
Data Signal Input Hold Time
0.8ns
0.8ns
08h
BYTE36
~61
Superset Information (may be used in future)
BYTE62
SPD Revision
BYTE63
Checksum for Byte 0~62
BYTE64
Manufacturer JEDEC ID Code
BYTE65
~71
....Manufacturer JEDEC ID Code
Rev. 0.3/Apr.01
64MB
NOTE
2
10h
Intel SPD 1.2A
-
08h
00h
12h
79h
3, 8
B0
Hynix JEDED ID
ADh
Unused
FFh
5
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
Continued
BYTE
NUMBER
FUNCTION
DESCRIPTION
FUNCTION
VALUE
NOTE
-H
-K
-H
-K
Hynix (Korea Area)
HSA (United States Area)
HSE (Europe Area)
HSJ (Japan Area)
Asia Area
0*h
1*h
2*h
3*h
4*h
10
7 (SDRAM)
37h
4, 5
6
36h
4, 5
V (3.3V, LVTTL)
56h
4, 5
8
38h
4, 5
C (RCC Registered with PLL)
43h
Manufacturer’s Part Number (Data Width)
7
37h
4, 5
....Manufacturer’s Part Number (Data Width)
3
33h
4, 5
5 (4K Refresh, 4Banks)
35h
4, 5
H
48h
4, 5
....Manufacturer’s Part Number (Generation)
G
47h
4, 5
Manufacturer’s Part Number (Package Type)
T
54h
4, 5
8 (x8 based)
48h
4, 5
- (Hyphen)
2Dh
4, 5
BYTE72
Manufacturing Location
BYTE73
Manufacturer’s Part Number (Component)
BYTE74
Manufacturer’s Part Number (128Mb based)
BYTE75
Manufacturer’s Part Number (Voltage Interface)
BYTE76
Manufacturer’s Part Number (Memory Width)
BYTE77
Manufacturer’s Part Number (Module Type)
BYTE78
BYTE79
BYTE80
Manufacturer’s Part Number (Refresh, SDRAM Bank)
BYTE81
Manufacturer’s Part Number (Generation)
BYTE82
BYTE83
BYTE84
Manufacturer’s Part Number (Component Configuration)
BYTE85
Manufacturer’s Part Number (Hyphen)
BYTE86
Manufacturer’s Part Number (Min. Cycle Time)
BYTE87
~90
Manufacturer’s Part Number
Blanks
20h
4, 5
BYTE91
Revision Code (for Component)
Process Code
-
4, 6
BYTE92
....Revision Code (for PCB)
Process Code
-
4, 6
BYTE93
Manufacturing Date
Work Week
-
3, 6
BYTE94
....Manufacturing Date
Year
-
3, 6
BYTE95
~98
Assembly Serial Number
Serial Number
-
6
BYTE99
~125
Manufacturer Specific Data (may be used in future)
None
00h
BYTE126
Reserved
100MHz
64h
7, 8, 9
BYTE127
Reserved
Refer to Note7
87h
7, 8, 9
BYTE128
~256
Unused Storage Locations
-
00h
K
H
4Bh
48h
4, 5
Note :
1. The bank address is excluded
2. 1, 2, 4, 8 for Interleave Burst Type
3. BCD adopted
4. ASCII adopted
5. Basically Hynix writes Part No. except for ‘HYM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90
6. Not fixed but dependent
7. CK0 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support
8. Refer to the most recent Intel and JEDEC SPD Specification
9. These values are applied to PC100 applications only per Intel PC SDRAM specification
10. Refer to Hynix Web Site
Rev. 0.3/Apr.01
6
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to V S S
V IN, VOUT
-1.0 ~ 4.6
V
Voltage on V DD relative to VSS
V DD, V DDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IO S
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (T A=0 to 70°C )
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
V DD , VDDQ
3.0
3.3
3.6
V
1
Input High voltage
V IH
2.0
3.0
V DDQ + 0.3
V
1,2
Input Low voltage
V IL
-0.3
0
0.8
V
1,3
Note
Note :
1.All voltages are referenced to VSS = 0V
2.V IH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V IL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA =0 to 70°C, VDD =3.3±0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
AC Input High / Low Level Voltage
V IH / VIL
2.4/0.4
V
Input Timing Measurement Reference Level Voltage
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
CL
50
pF
Output Load Capacitance for Access Time Measurement
1
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 0.3/Apr.01
7
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
CAPACITANCE (TA=25°C, f=1MHz)
-K/H
Parameter
Pin
Input Capacitance
Data Input / Output Capacitance
Symbol
Unit
Min
Max
CK0
CI1
-
30
pF
CKE0
CI2
-
15
pF
/S0, /S2
CI3
-
15
pF
A0~11, BA0, BA1
CI4
-
15
pF
/RAS, /CAS, /WE
CI5
-
15
pF
DQM0~DQM7
CI6
-
15
pF
DQ0 ~ DQ63
C I/O
-
15
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
DC Output Load Circuit
Rev. 0.3/Apr.01
50pF
AC Output Load Circuit
8
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
DC CHARACTERISTICS I (TA=0 to 70°C, VDD =3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-10
10
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
V OH
2.4
-
V
IOH = -4mA
Output Low Voltage
V OL
-
0.4
V
IOL = +4mA
Note :
1.V IN = 0 to 3.6V, All other pins are not tested under V IN =0V
2.DOUT is disabled, VOUT =0 to 3.6
DC CHARACTERISTICS II
Speed
Parameter
Symbol
Test Condition
-K
-H
1130
1130
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC (min), IOL =0mA
Precharge Standby Current
in Power Down Mode
IDD2P
CKE ≤ V IL (max), tCK = min
IDD2PS
CKE ≤ V IL (max), tCK =
IDD2N
CKE ≥ V IH (min), CS ≥ V IH (min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V
535
IDD2NS
CKE ≥ V IH (min), tCK = ∞
Input signals are stable.
225
IDD3P
CKE ≤ V IL (max), tCK = min
383
IDD3PS
CKE ≤ V IL (max), tCK =
IDD3N
CKE ≥ V IH (min), CS ≥ V IH (min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V
670
IDD3NS
CKE ≥ V IH (min), tCK = ∞
Input signals are stable.
360
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
tRRC ≥ tRRC (min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
Unit
Note
mA
1
338
mA
∞
338
mA
mA
∞
135
mA
CL=3
1400
1400
CL=2
1400
1400
mA
1
2000
mA
2
258
mA
Note :
1. IDD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. All values are measured with Registered and PLL
Rev. 0.3/Apr.01
9
PC133 SDRAM Registered DIMM
AC CHARACTERISTICS I
HYM76V8C735HGT8 Series
(AC operating conditions unless otherwise noted)
-K
Parameter
Unit
Min
System Clock
Cycle Time
CAS Latency = 3
-H
Symbol
tCK3
Max
7.5
Min
7.5
1000
ns
1000
10
1
tCK2
7.5
Clock High Pulse Width
tCHW
2.5
-
2.5
-
ns
2
Clock Low Pulse Width
tCLW
2.5
-
2.5
-
ns
2
CAS Latency = 3
tAC3
-
5.4
-
5.4
ns
CAS Latency = 2
tAC2
-
5.4
-
6
ns
Access Time
From Clock
CAS Latency = 2
Note
Max
ns
3
Data-Out Hold Time
tOH
2.7
-
2.7
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
ns
2
Data-Input Hold Time
tDH
0.8
-
0.8
-
ns
2
Address Setup Time
tAS
1.5
-
1.5
-
ns
2
Address Hold Time
tAH
0.8
-
0.8
-
ns
2
CKE Setup Time
tCKS
1.5
-
1.5
-
ns
2
CKE Hold Time
tCKH
0.8
-
0.8
-
ns
2
Command Setup Time
tCS
1.5
-
1.5
-
ns
2
Command Hold Time
tCH
0.8
-
0.8
-
ns
2
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
ns
CLK to Data
Output in High-Z
Time
CAS Latency = 3
tOHZ3
2.7
5.4
2.7
5.4
ns
CAS Latency = 2
tOHZ2
2.7
5.4
3
6
ns
Note :
1. In Registered DIMM, data is delayed an additional clock cycle due to the register (this is, Device CL + 1 = DIMM CL)
2. Assume tR / tF (input rise and fall time ) is 1ns, If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
3. Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.3/Apr.01
10
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
AC CHARACTERISTICS II
-K
Parameter
-H
Symbol
Unit
Min
Max
Min
Max
Note
Operation
tRC
65
-
65
-
ns
Auto Refresh
tRRC
65
-
65
-
ns
RAS to CAS Delay
tRCD
20
-
20
-
ns
RAS Active Time
tRAS
45
100K
45
100K
ns
RAS Precharge Time
tRP
20
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
15
-
15
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
CLK
1
Data-In to Precharge Command
tDPL
1
-
1
-
CLK
1
Data-In to Active Command
tDAL
4
-
4
-
CLK
1
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
CLK
1
DQM to Data-In Mask
tDQM
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
CLK
CAS Latency = 3
tPROZ3
4
-
4
-
CLK
CAS Latency = 2
tPROZ2
3
-
3
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
ms
RAS Cycle Time
Precharge to Data
Output Hi-Z
1
2
Note :
1. Timing delay due to the register is considered in a registered DIMM
2. A new command can be given tRRC after self refresh exit
Rev. 0.3/Apr.01
11
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
DEVICE OPERATING OPTION TABLE
HYM76V8C735HGT8-K
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
HYM76V8C735HGT8-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
Note : DIMM/CAS Latency = Device CL + 1 (Registered Mode)
COMMAND TRUTH TABLE
Command
Mode Register Set
CKEn-1
CKEn
H
X
No Operation
H
X
Bank Active
H
X
Read
CS
RAS
A10/
AP
CAS
WE
DQM
X
OP code
X
X
L
L
L
L
H
X
X
X
L
H
H
H
L
L
H
H
ADDR
X
RA
X
L
H
L
H
X
CA
H
X
L
H
L
L
X
CA
H
X
L
L
H
L
X
X
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
V
X
X
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Auto Refresh
Self Refresh1
X
H
H
L
L
L
H
X
Entry
H
L
L
L
L
H
X
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
Precharge
power down
Clock
Suspend
Exit
L
H
Entry
H
L
Exit
L
H
X
X
Note
V
L
H
Read with Autoprecharge
BA
H
L
H
V
V
H
X
L
V
X
X
X
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.3/Apr.01
12
PC133 SDRAM Registered DIMM
HYM76V8C735HGT8 Series
PACKAGE DEMENSION
Rev. 0.3/Apr.01
13