HyperPHY™ Transceiver Cores Gflx™ Standard HyperPHY OVERVIEW FEATURES HyperPHYTM is an LSI Logic CoreWare® transceiver technology family designed for broadband and networking applications for extremely high bandwidth CMOS ASICs. • Data rates from 528 Mbps to 800 Mbps HyperPHY transceiver technology includes a full clock recovery mechanism that permits the recovery of clock and data from a data stream alone. Communication on HyperPHY channels is possible over a variety of physical media, including copper cable and printed circuit board traces with high speed backplane connectors G flx T M S T A N D A R D H Y P E R P H Y D E S C R I P T I O N GflxTM Standard HyperPHY represents the fourth generation of a continuing transceiver technology family. The HyperPHY methodology allows for the construction of transceiver architectures in an ASIC methodology. The cores consist of a serializer, a de-serializer with clock and data recovery, and a low-jitter PLL. These cores, shown in Figure 1 as TX, RX and PLL, respectively, are combined into sub-systems per customer specifications. Figure 1 shows a generic full duplex subsystem, with 32 independent receive channels and 32 independent transmit channels, all serviced by a single PLL. RX Channel 2 Receive Data Word Clock (8 bit word) P S Control Clock and Data Recovery Serial High Speed Serial RX Data LVDS Receiver TX Channel 1 Transmit Data Word Transmit Data Word Clock (8 bit word) P S LVDS Driver Control High Speed Serial TX Data • Typical 55 mW per full duplex channel at 622 Mbps • Allows at-speed built-in-self-test of full transmit and receive/clock recovery functions • Produced in LSI Logic Gflx technology (0.13 micron CMOS) • 1.2V supply • Separate serializer and de-serializer cores allow for data flow architectures • Supports OC-12/STM-4 data rate with up to two levels of forward error correction PLL Clock To All Channels PLL • Physically separate serializer and de-serializer cores • Modular building blocks allow for flexible architectures with an ASICfriendly design approach TX Channel 2 Serial • LVDS buffers with on-chip termination resistors BENEFITS TX Channel 32 20 • Up to 128 full duplex channels allowed on a single ASIC • Receiver channel-to-channel de-skew RX Channel 1 20 • 8-bit parallel word with associated clock • Able to receive data reliably even with long sequences of data without transitions RX Channel 32 Receive Data Word • Supports SPI-4.2 and SFI-4 standards Reference Clock Figure 1: Block diagram of ASIC subsystem using Gflx Standard HyperPHY HyperPHY™ Transceiver Core The modular HyperPHY methodology allows for a single PLL to support 4 up to 64 TX and/or RX cores, with practically any combination of RX and TX. Up to 128 full duplex channels can be placed on a single ASIC using this methodology. Although TX and RX cores are physically separate, each channel can perform a built-in-self-test (BIST) using a PRBS pattern in a serial loopback mode.The TX LVDS drivers have programmable output levels allowing the user to “tune” the driver for specific transmission channels. G flx S T A N D A R D H Y P E R P H Y A P P L I C A T I O N S A common application for HyperPHY is the high-speed switch used in broadband networking and in local area networks. Thus, it includes routers, LAN switches, ATM switches, digital cross-connects, ADMs, and DWDM systems. A typical scenario is shown in Figure 2 for a SONET or DWDM system, where a switch card with a switch matrix ASIC communicates with a number of line cards. Packet Transfer Interface (SPI) Optical SERDES Interface (SFI) Optics O/E SERDES O/E SERDES High Speed Backplane Interface O/E SERDES O/E SERDES Line Card LSI Logic Corporation North American Headquarters Milpitas, CA Tel: 866 574 5741 LSI Logic Europe Ltd. European Headquarters United Kingdom Tel: 44 1344 426544 Fax: 44 1344 481039 LSI Logic KK Headquarters Tokyo, Japan Tel: 81 3 5463 7165 Fax 81 3 5463 7820 LSI: Logic web site: www.lsilogic.com LSI Logic logo design, CoreWare, HyperPHY and Gflx are trademarks or registered trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. Link Layer Traffic Processing PHY Line Card Optics For more information please call: Link PHY Layer Traffic Processing Switch Fabric High Speed Backplane Figure 2: HyperPHY in a DWDM/SONET System Architecture HyperPHY channels can be used as the serial backplane interface between line cards. Gflx Standard HyperPHY allows up to 128 full duplex channels on an ASIC, so a single switch fabric ASIC can have a total throughput of 159 Gbps, assuming 622 Mbps per channel. Since widely-used industry standard specifications for backplane interfaces do not exist, the modularity and flexibility of HyperPHY transceivers makes them suitable for nearly all applications. At the line card interface to the optics, Gflx Standard HyperPHY is well suited to comply with both the 10 Gbps SFI-4 specification. For interfacing between Traffic Processing ASICs and ASSPs such as framers, Gflx Standard HyperPHY also complies with the 10 Gbps SPI-4.2 specification. Gflx Standard HyperPHY receivers have lane-to-lane de-skew capabilities to meet the requirements of SPI-4.2. LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase, lease, or use of a product or service from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or of third parties. Copyright ©2002 by LSI Logic Corporation. All rights reserved. Order No.C20050 502.0k.SR.W - Printed in USA