VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Description The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. Selfrefresh is supported and CBR cycles are being performed. lt is packaged in JEDEC standard 42-pin 400mil SOJ and 50(44)-pin 400mil TSOPII. Features • Single 5V or 3.3V only power supply • High speed tRAC access time: 50/60ns • Extended-data-out (EDO) page mode access • I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) • 4 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh • Refresh interval: - RAS only refresh, CAS - before - RAS refresh and hidden refresh: 1024 cycles in 16 ms - Self-refresh: 1024 cycles • JEDEC standard pinout: 44-pin 400mil SOJ and 50(44)-pin 400mil TSOPII Document:1G5-0179 Rev.2 Page 1 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Pin Configuration 42-Pin 400mil SOJ VCC 1 DQ0 DQ1 DQ2 DQ3 VCC 2 3 40 VSS DQ15 DQ14 4 5 39 38 DQ13 DQ12 6 7 37 36 VSS DQ11 8 9 10 35 34 33 DQ10 DQ9 DQ8 11 32 12 13 31 30 NC LCAS UCAS 14 15 16 17 18 29 28 OE A9 27 26 25 A8 A6 24 23 A5 A4 22 VSS DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC NC A0 A1 A2 A3 50(44)-Pin 400mil TSOPII 42 41 19 VCC 20 21 A7 VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 GND DQ15 DQ14 DQ13 DQ12 GND DQ11 DQ10 DQ9 DQ8 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND Pin Description Pin Name Function A0-A9 Address inputs - Row address: A0-A9 - Column address: A0-A9 - Refresh address: A0-A9 DQ0~DQ15 Data-in / data-out RAS Row address strobe UCAS, LCAS Column address strobe WE Write enable OE Output enable Vcc Power (+5 V or + 3.3V) Vss Ground NC No connection Document:1G5-0179 Rev.2 Page 2 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Block Diagram WE LCAS CAS UCAS CONTROL LOGIC DATA - IN BUFFER DQ1 . . DQ16 NO.2 CLOCK GENERATOR DATA - OUT BUFFER OE COLUMNADDRESS BUFFERS (10) COLUMN DECODER A0 A1 A2 1024 REFRESH CONTROLLER A3 SENSE AMPLIFIERS I/0 GATING A4 A5 REFRESH COUNTER 1024x16 A6 RAS ROW ADDRESS BUFFERS (10) 1024 A8 A9 ROW DECODER A7 1024 x 1024 x 16 MEMORY ARRAY Vcc NO.1 CLOCK GENERATOR Document:1G5-0179 Vss Rev.2 Page 3 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM TRUTH TABLE ADDRESSES FUNCTION RAS LCAS UCAS WE OE ROW COL STANDBY H H→X H→X X X X X READ : WORD L L L H L ROW COL Data-Out READ : LOWER BYTE L L H H L ROW COL Lower Byte: Data-Out Upper Byte: High-Z READ: UPPER BYTE L H L H L ROW COL Lower Byte: High-Z Upper Byte: Data-Out WRITE: WORD (EARLY WRITE) L L L L X ROW COL Data-In WRITE: LOWER BYTE (EARLY) L L H L X ROW COL Lower Byte: Data-In Upper Byte: High-Z WRITE : UPPER BYTE (EARLY) L H L L X ROW COL Lower Byte: High-Z Upper Byte: Data-In READ WRITE L L L H→L L→H ROW COL Data-Out, Data-In 1st Cycle L H→L H→L H L ROW COL Data-Out 2 2nd Cycle L H→L H→L H L n/a COL Data-Out 2 1st Cycle L H→L H→L L X ROW COL Data-In 1 2nd Cycle L H→L H→L L X n/a COL Data-In 1 1st Cycle L H→L H→L H→L L→H ROW COL Data-Out, Data-In 1,2 2nd Cycle L H→L H→L H→L L→H n/a COL Data-Out, Data-In 1,2 READ L→H→L L L H L ROW COL Data-Out WRITE L→H→L L L L X ROW COL Data-In L H H X X ROW n/a High-Z H→L L L H X X X High-Z PAGE-MODE READ PAGE-MODE WRITE PAGE-MODE READWRITE HIDDEN REFRESH RAS-ONLY REFRESH CBR REFRESH DQS Notes High-Z 2 1,3 4 Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS). Document:1G5-0179 Rev.2 1,2 Page 4 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Absolute Maximum Ratings Parameter Symbol Voltage on an any pin relative to Vss 5V Supply voltage relative to Vss 5V Short circuit output current V -0.5 to + 4.6 -1.0 to + 7.0 VCC 3.3V Unit -1.0 to + 7.0 VT 3.3V Value V -0.5 to + 4.6 IOUT 50 mA PD 1.0 W Operating temperature TOPT 0 to + 70 °C Storage temperature TSTG -55 to + 125 °C Power dissipation Recommended DC Operating Conditions 5 Volt Version 3.3 Volt Version Unit Symbol Min Typ Max Min Typ Max Supply Voltage VCC 4.5 5.0 5.5 3.15 3.3 3.6 V Input High Voltage, all inputs VIH 2.4 - VCC + 1.0 2.0 - VCC + 0.3 V Input Low Voltage, all inputs VIL -1.0 - 0.8 -0.3 - 0.8 V Parameter/Condition Capacitance Ta = 25°C, VCC = 5V ± 10 % or 3.3V ± 10 %, f = 1MHz Parameter Symbol Max Unit Note Input capacitance (Address) CI1 5 pF 1 Input capacitance (RAS , LCAS , UCAS, OE, WE) CI2 7 pF 1 Output capacitance (Data-in, Data-out) CI/O 7 pF 1, 2 Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, LCAS and UCAS = VIH to disable Dout. Document:1G5-0179 Rev.2 Page 5 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM DC Characteristics; 5- Volt Verion (Ta = 0 to + 70 °C, VCC= + 5V ± 10 %,VSS = 0V) Parameter Symbol Test Conditions VG26(S)18165 -5 Operating current Standby current ICC1 ICC2 RAS cycling LCAS / UCAS cycling tRC = min Unit -6 Min Max Min Max - 160 - 145 2 - 2 1 - 1 1, 2 TTL interface RAS,LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS ≥ Vcc -0.2V Dout = High-Z RAS-only refresh current ICC3 RAS cycling, LCAS / UCAS = VIH tRC = min EDO page mode current ICC4 tRC = min CAS-before-RAS refresh current ICC5 Self-refresh current ICC6 mA mA mA 1, 2 - 160 - 145 mA - 90 - 80 mA tRC = min RAS, LCAS / UCAS cycling - 160 - 145 mA t RAS ≥ 100µs - 500 - 500 µA Input leakage current ILI 0V ≤ V IN ≤ V CC + 0.5V -5 5 -5 5 µA Output leakage current ILO 0V ≤ V OUT ≤ V CC + 0.5V Dout = Disable -5 5 -5 5 µA Output high Voltage VOH IOH = - 5mA 2.4 - 2.4 - V Output low voltage VOL IOL = + 4.2mA - 0.4 - 0.4 V Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. Document:1G5-0179 Rev.2 Notes Page 6 1, 3 1, 2 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM DC Characteristics ; 3.3 - Volt Version (Ta = 0 to 70°C, VCC = + 3.15V~3.6V, VSS = 0V) VG26V(S)18165 Parameter Symbol Test Conditions -5 -6 Min Max Min Max Unit Notes 1, 2 Operating current ICC1 RAS cycling LCAS / UCAS cycling tRC = min - 160 - 145 mA Standby Current ICC2 LVTTL interface RAS, LCAS / UCAS = VIH Dout = High-Z - 2 - 2 mA CMOS interface - 0.5 - 0.5 mA RAS, CAS ≥ VCC -0.2V Dout = High-Z RAS- only refresh current ICC3 RAS cycling LCAS / UCAS = VIH tRC = min - 160 - 145 mA 1, 2 EDO page mode current ICC4 tPC = min - 90 - 80 mA 1, 3 CAS- before- RAS refresh current ICC5 tRC = min RAS, LCAS / UCAS cycling - 160 - 145 mA 1, 2 Self- refresh current ICC6 t RASS ≥ 100µs - 450 - 450 µA Input leakage current ILI 0V ≤ Vin ≤ V CC + 0.3V -5 5 -5 5 µA Output leakage current ILO 0V ≤ Vout ≤ V CC + 0.3V -5 5 -5 5 µA Dout = Disable Output high Voltage VOH IOH = -2mA 2.4 - 2.4 - V Output low voltage VOL IOL = +2mA - 0.4 - 0.4 V Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. Document:1G5-0179 Rev.2 Page 7 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM AC Characteristics(Ta = 0 to + 70°C, Vcc = 5V ±10 % or 3.15V~3.6V, Vss = 0V) *1, *2, *3, *4, *5 Test conditions • Output load: two TTL Loads and 50pF (VCC = 5.0V ± 10 %); one TTL Load and 50pF (VCC = 3.15V~3.6V) • Input timing reference levels: VIH = 2.4V, VIL = 0.8V (VCC = 5.0V ± 10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.15V~3.6V) • Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VCC = 5V ± 10 %, 3.15V~3.6V) Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) VG26(V)(S) 18165 Parameter Symbol -5 Min -6 Max Min Unit Notes Max Random read or write cycle time tRC 84 - 104 - ns RAS precharge time tRP 30 - 40 - ns LCAS / UCAS precharge time in normal tCPN 10 - 10 - ns RAS pulse width tRAS 50 10K 60 10K ns 6 LCAS / UCAS pulse width tCAS 8 10K 10 10K ns 7 Row address setup time tASR 0 - 0 - ns Row address hold time tRAH 8 - 10 - ns Column address setup time tASC 0 - 0 - ns Column address hold time tCAH 8 - 10 - ns RAS to LCAS / UCAS delay time tRCD 12 37 14 45 ns 9 RAS to column address delay time tRAD 10 25 12 30 ns 10 Column address to RAS lead time tRAL 25 - 30 - ns RAS hold time tRSH 8 - 10 - ns LCAS / UCAS hold time tCSH 38 - 40 - ns LCAS / UCAS to RAS precharge time tCRP 5 - 5 - ns OE to Din delay time tOED 20 - 20 - ns Transition time (rise and fall) tT 1 50 1 50 ns Refresh period tREF - 16 - 16 ms LCAS / UCAS to output in Low- Z tCLZ 0 - 0 - ns LCAS / UCAS delay time from Din tDZC 0 - 0 - ns OE delay time from Din tDZO 0 - 0 - ns mode Document:1G5-0179 Rev.2 8 11 12 Page 8 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Read Cycle VG26(V)(S)18165 Parameter Symbol -5 Min -6 Max Min Unit Notes Max Access time from RAS tRAC - 50 - 60 ns 13 Access time from LCAS / UCAS tCAC - 13 - 15 ns 14, 15 Access time from column address tAA - 25 - 30 ns 15, 16 Access time from OE tOEA - 12 - 15 ns Read command setup time tRCS 0 - 0 - ns 8 Read command hold time to LCAS / UCAS tRCH 0 - 0 - ns 11, 17 Read command hold time to RAS tRRH 10 - 10 - ns 17 Output buffer turn-off time tOFF 0 12 0 15 ns 18 Output buffer turn-off time from OE tOEZ 0 12 0 15 ns 18 Unit Notes 8, 19 Write Cycle VG26(V)(S)18165 Parameter Symbol -5 Min -6 Max Min Max Write command setup time tWCS 0 - 0 - ns Write command hold time tWCH 8 - 10 - ns Write command pulse width tWP 8 - 10 - ns Write command to RAS lead time tRWL 13 - 15 - ns Write command to LCAS / UCAS lead time tCWL 8 - 10 - ns 20 Data-in setup time tDS 0 - 0 - ns 21 Data-in hold time tDH 8 - 10 - ns 21 WE to Data-in delay tWED 10 - 10 - ns Read- Modify- Write Cycle VG26(V)(S)18165 Parameter Symbol -5 Min -6 Max Min Unit Notes Max Read-modify- write cycle time tRWC 108 - 133 - ns RAS to WE delay time tRWD 64 - 77 - ns 19 LCAS / UCAS to WE dealy time tCWD 26 - 32 - ns 19 Column address to WE delay time tAWD 39 - 47 - ns 19 OE hold time from WE tOEH 8 - 10 - ns Document:1G5-0179 Rev.2 Page 9 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Refresh Cycle VG26(V)(S)18165 Parameter -5 Symbol -6 Min Max Min Max Unit Notes LCAS / UCAS setup time (CBR refresh) tCSR 5 - 5 - ns LCAS / UCAS hold time (CBR refresh) tCHR 8 - 10 - ns 11 RAS precharge to CAS hold time tRPC 5 - 5 - ns 8 RAS pulse width (self refresh) tRASS 100 - 100 - µs RAS precharge time (self refresh) tRPS 90 - 110 - ns LCAS / UCAS hold time (CBR self refresh) tCHS -50 - -50 - ns WE setup time tWSR 0 - 0 - ns WE hold time tWHR 10 - 10 - ns EDO Page Mode Cycle VG26(V)(S)18165 Parameter Symbol -5 Min -6 Max Min Unit Notes Max EDO page mode cycle time tPC 20 - 25 - ns EDO page mode LCAS / UCAS precharge time tCP 10 - 10 - ns EDO page mode RAS pulse width tRASP 50 105 60 105 ns 22 Access time from LCAS / UCAS precharge tCPA - 30 - 35 ns 11, 15 RAS hold time from LCAS / UCAS precharge tCPRH 30 - 35 - ns OE high hold time from LCAS / UCAS high tOEHC 5 - 5 - ns OE high pulse width tOEP 10 - 10 - ns Data output hold time after LCAS / UCAS low tCOH 5 - 5 - ns Output disable delay from WE tWHZ 3 10 3 10 ns WE pulse width for output disable when LCAS / UCAS high tWPZ 10 - 10 - ns EDO Page Mode Read Modify Write Cycle VG26(V)(S)18165 Parameter Symbol -5 Min -6 Max Min tCPW 45 - 55 - EDO page mode read- modify- write cycle time tPRWC 56 - 68 - Rev.2 Notes ns 11 Max EDO page mode read- modify- write cycle LCAS / UCAS precharge to WE delay time Document:1G5-0179 Unit ns Page 10 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Notes : 1. AC measurements assume tT = 1ns. 2. An initial pause of 100 µs is required after power up, and it followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. When both LCAS and UCAS go low at the same time, all 16-bits data are witten into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 6. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle. 7. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 8. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS . 9. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 10. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 11. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS . 12. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. 13. Assumes that t RCD ≤ tRCD(max) and t RAD ≤ tRAD(max). If t RCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 14. Assumes that t RCD ≥ t RCD (max) and t RAD ≤ t RAD (max). 15. Access time is determined by the maximum of tAA, tCAC, tCPA. 16. Assumes that t RCD ≤ t RCD (max) and t RAD ≥ t RAD (max). 17. Either tRCH or tRRH must be satisfied for a read cycle. 18. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). tOFF is determined by the later rising edge of RAS or CAS. 19. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS ≥ t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t RWD t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t RWD (min), ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 20. tCWL shall be satisfied by both LCAS and UCAS. 21. These parameters are referenced to LCAS or LCAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 22. tRASP defines RAS pulse width in EDO page mode cycles. Document:1G5-0179 Rev.2 Page 11 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Timing Waveforms • Word Read Cycle t RC t RAS t RP RAS t CRP t CSH t RCD t RSH t T t CPN t CAS UCAS LCAS t RAL t RAD t ASR ADDRESS t ASC t RAH t CAH Column Row t RRH t RCH t RCS WE OE t OEA t CAC t OEZ t OFF t AA t RAC DQ1~DQ16 Document:1G5-0179 t CLZ Rev.2 DOUT Page 12 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • Byte Read Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CAS UCAS (or LCAS) LCAS (or UCAS) t RAL t RAD t ASR ADDRESS t RAH t ASC t CAH Column Row tRRH t RCH t RCS WE OE t OEA t CAC t OEZ t OFF t AA t RAC DQ9~DQ16 (or DQ1~DQ8) DQ1~DQ8 (or DQ9~DQ16) Document:1G5-0179 DOUT t CLZ High-Z Rev.2 Page 13 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • Word Early Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CAS UCAS LCAS t RAL t RAD t RAH t ASR ADDRESS t ASC Row t CAH Column t WCS t WCH WE t DH t DS DQ1~DQ16 Document:1G5-0179 DIN Rev.2 Page 14 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • Byte Early Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CAS LCAS (or UCAS) LCAS (or UCAS) t RAL t RAD t ASR ADDRESS t RAH t ASC Row t CAH Column t WCH t WCS WE t DH tDS DQ9~DQ16 DIN DQ1~DQ8 Document:1G5-0179 Rev.2 Page 15 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • Word Delayed Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CPN t CAS UCAS LCAS t ASR ADDRESS t RAH t ASC Row t CAH Column t CWL t RWL t RCS t WP WE t OEH t OED OE t DS DQ1~DQ16 Document:1G5-0179 OPEN t DH DIN Rev.2 Page 16 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • Byte Delayed Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CAS LCAS (or UCAS) LCAS (or UCAS) t ASR ADDRESS t RAH t ASC Row t CAH Column tCWL t RCS t RWL t WP WE t OEH tOED OE t DS DQ9~DQ16 (or DQ1~DQ8) OPEN t DH DIN DQ1~DQ8 (or DQ9~DQ16) Document:1G5-0179 Rev.2 Page 17 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • Word Read-Modify-Write Cycle t RWC t t RP RAS RAS t T t RCD t CRP t CPN t CAS UCAS LCAS t RAD t ASR ADDRESS t RAH t ASC t CAH Column Row t CWD t RCS t CWL t AWD t RWL t RWD t WP WE t DH t DS OPEN DQ1~DQ16 D in t OED t OEH OE t OEA t CAC t OEZ t AA t RAC DOUT DQ1~DQ16 Document:1G5-0179 Rev.2 Page 18 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • EDO Page Mode Word Read-Modify-Write Cycle t RASP tCPRH t RP RAS t T t RCD UCAS LCAS t PRWC t CP t CAS t CAS t RAD t ASR t ASC t RAH ADDRESS Column N Column 2 t CWL t RWD t AWD t CWD WE t CAH t CAH Column 1 Column 1 Row t CWL t CPW t AWD t CWD t RCS t CAS t RAL t ASC t ASC t CAH t CRP tCP t t CWL CPW t AWD t CWD t RWL WE t RCS t WP t WP t DS t WP t DS t DS tDH OPEN DQ1~DQ16 Din 1 t DH OPEN Din 2 t DH OPEN Din N tDZO tOED tOED tOEH tOEH tOED tOEH OE t OEA tOEA tCAC tCAC tRAC tAA tCPA tAA tCPA tAA tOEZ t OEZ tOEA tCAC tOEZ DQ1~DQ16 DOUT 2 DOUT 1 Document:1G5-0179 Rev.2 DOUT N Page 19 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • EDO Page Mode Word Read-Early-Write Cycle t t RP RASP t CPRH RAS t CRP t PC t CSH t RCD t CRP t CAS t RSH t CAS t CP t CAS t CP t CPN UCAS LCAS t CAL t CSH t RAD t ASR ADDRESS t RAL t ASC t RAH Row t CAH t ASC Column 1 t CAH Column N Column 2 t RCH t RCS WE t ASC t CAH Row t WCS t WCH WE tOEA t WED OE OE tRAC tAA tCPA tAA tWHZ tCAC tCAC tDH tDS tCOH DQ1~DQ16 OPEN Data Output 1 Data Output 2 Data Intput N Document:1G5-0179 Rev.2 Page 20 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • Read Cycle with WE Controlled Disable RAS t CSH t RCD t T t CAS UCAS LCAS t RAD t ASR ADDRESS t CAH t ASC t RAH Row Column t RCH t RCS t WPZ WE t WHZ t OED t DS OE tOEA tCAC tOEZ tAA tRAC DQ1~DQ16 DOUT tCLZ Document:1G5-0179 Rev.2 Page 21 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS - Only Refresh Cycle t RC t RP t RAS RAS tT tRPC t CRP tCRP UCAS LCAS tASR ADDRESS tRAH Row tOFF OPEN DQ1~DQ16 CAS-Before-RAS Refresh Cycle tRC tRP tRC tRAS RAS tT tRAS tRP tRPC tRPC t RP tCRP t CSR t CHR tCSR tWSR tWHR tWSR tCHR tWHR UCAS LCAS WE tOFF OPEN DQ1~DQ16 Document:1G5-0179 Rev.2 Page 22 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • Hidden Refresh Cycle t RC t RC t RC t RP tRAS (READ) tRAS t RP (REFRESH) tRAS tRP (REFRESH) RAS tT t CHR tCRP tRSH tRCD tCAS UCAS LCAS t RAD t ASR ADDRESS t RAH t RAL tASC tCAH Column Row tRRH t RCS tRCH WE tORD OE t OEZ t OEA t CAC t OFF t AA t OFF t RAC D OUT DQ1~DQ16 Document:1G5-0179 Rev.2 Page 23 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM • SELF REFRESH CYCLE (Addresses, WE and OE = DON’T CARE) tRP t RPS tRASS RAS t RPC t CP tCHD t CSR t RPC t CP UCAS/LCAS DQ Open Don’t Care Document:1G5-0179 Rev.2 Page 24 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Ordering information Part Number Access time Package VG26(V)(S)18165CJ-5 50 ns 400mil 42-Pin Plastic SOJ or VG26(V)(S)18165CJ-6 60 ns 400mil 50(44) -Pin TSOPII VG26(V)(S)18165CJ-5 • VG • VIS Memory Product • 26 • Technology •V • V: 3.3V Version; Non: 5V •S • S: Self Refresh; Non: Non Self Refresh • 18165 • Device Type and Configuation •C • Revision (C and D) •J • Package Type (J : SOJ, T : TSOP II) •5 • Speed (5: 50 ns, 6: 60 ns) Document:1G5-0179 Rev.2 Page 25 VIS VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM Package Information 42-pin SOJ D DIM A A1 A2 b b1 b2 c c1 e D E E1 E2 R1 θ MILLIMETERS MIN. NOM. MAX. 3.25 3.51 3.76 2.08 ----2.79 REF. --0.38 0.51 --0.38 0.46 0.66 0.71 0.81 0.18 --0.33 0.18 0.20 0.28 1.27 BASIC 27.18 27.31 27.43 11.05 11.18 11.30 10.03 10.16 10.29 9.40 BASIC 0.76 0.89 1.02 3° --16° INCHES MIN. NOM. MAX. 0.128 0.138 0.148 0.082 ----0.110 REF. --0.015 0.020 --0.015 0.018 0.026 0.028 0.032 0.007 --0.013 0.007 0.008 0.011 0.050 BASIC 1.070 1.075 1.080 0.435 0.440 0.445 0.395 0.400 0.405 0.370 BASIC 0.040 0.030 0.035 16° 3° --- 42 22 b b1 c1 c E1 E BASE METAL WITH PLATING SECTION B-B 1 21 θ 0.025" MIN. A2 A NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025) BELOW b2 MIN. b2 b 0.004" B E2 RAD R1 e 0.007" M B A1 SEATING PLANE Package Information 50(44)-pin TSOPII DIM MILLIMETERS MIN. NOM. INCHES MAX. MIN. A --- --- 1.20 --- --- 0.047 A1 0.05 --- 0.15 0.002 --- 0.006 A2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.30 --- 0.45 0.012 --- 0.018 b1 0.30 --- 0.40 0.012 --- 0.016 c 0.12 --- 0.21 0.005 --- 0.008 c1 0.11 --- 0.16 0.0045 --- 0.006 D 20.82 20.95 21.08 0.820 0.825 0.830 ZD 0.875 BASIC e 0.80 BASIC NOM. MAX. 50 40 36 26 RAD R1 RAD R A2 E1 0.0344 BASIC 0.0315 BASIC 11.56 11.76 11.96 0.455 0.463 0.471 E1 10.03 10.16 10.29 0.395 0.400 0.405 L 0.40 0.50 0.60 0.016 0.020 0.024 R 0.11 --- 0.25 0.004 --- 0.010 R1 0.11 --- --- 0.004 --- --- 1 11 15 b b1 25 B L DETAIL A E c B A1 0 ~5 SECTION B-B D c1 c BASE METAL WITH PLATING NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. Document:1G5-0179 DETAIL A ZD A b 4-1.60 REF. E 40 - e SEATING PLANE 0.100(0.004) Rev.2 Page 26