ETC WED3EG72256SXX-JD3

WED3EG72256SXX-JD3
ADVANCED
2GB- 256Mx72, ECC, DDR SDRAM DIMM REGISTERED
MODULE
DESCRIPTION
FEATURES
Double data rate architecture; two data transfers
per clock cycle
The WED3EG72256SXX-JD3 is a 256Mx72 Double
Data Rate SDRAM memory module based on 1
Gigabit DDR SDRAM components. The module
consists of eighteen, 256Mx4 DDR SDRAMs in 66
pin TSOP packages mounted on a 184 pin FR4
substrate.
Clock speeds of 100MHz and 133MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK)
DLL aligns DQ and DQS transition with CK
transition
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lengths allow the
same device to be useful for a variety of high
bandwidth, high performance memory system
applications.
Programmable Read latency 2, 2.5 (clock)
Programmable Burst Length (2, 4, 8)
Programmable Burst type (sequential &
interleave)
Edge aligned data output, center aligned data
input
Auto and self refresh
Serial presence detect
JEDEC standard 184 pin DIMM package
Power supply: Vdd: 2.5V ± 0.2V, Vddq: 2.5V ±
0.2V
OPERATING FREQUENCIES
Speed
CL-tRCD-tRP
262JD3
(DDR266@CL=2)
133MHz
2-3-3
265JD3
(DDR266@CL=2.5)
133MHz
2.5-3-3
202JD2
(DDR200@CL=2)
100MHz
2-2-2
Advance information: Speed may not be available.
January 2004 Rev. 0
1
White Electronic Designs Corporation •
(602) 437-1520 • www.whiteedc.com
WED3EG72256SXX-JD3
PIN CONFIGURATION (FRONT SIDE/BACK SIDE)
PIN FRONT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
RESET
VSS
DQ8
DQ9
DQS1
VDDQ
NC
NC
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
PIN
FRONT
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
KEY
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
53
54
55
56
57
58
59
60
61
PIN
FRONT
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
NC
NC
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
PIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
BACK
PIN BACK
VSS
DQ4
DQ5
VDDQ
DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DQS10
VDD
DQ14
DQ15
NC
VDDQ
NC
DQ20
A12
VSS
DQ21
A11
DQS11
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
PIN BACK
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
A6
DQ28
DQ29
VDDQ
DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0
VSS
DQS17
A10
CB6
VDDQ
CB7
KEY
VSS
DQ36
DQ37
VDD
DQS13
DQ38
DQ39
VSS
DQ44
RAS
DQ45
VDDQ
CS0
NC
DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
A13
VDD
DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
PIN DESCRIPTION
Pin Name
A0 ~ A13
BA0 ~ BA1
Function
Address input (Multiplexed)
Bank Select Address
Pin Name
VDD
Function
Power supply (2.5V)
DQ0 ~ DQ63
Data input/output
VDDQ
VSS
Power Supply for DQS (2.5V)
Ground
DQS0 ~ DQS17 Data Strobe input/output
VREF
Power Supply for reference
CK0, CK0
Clock input
VDDSPD
Serial EEPROM Power/Supply (2.3V to 3.6V)
CKE0
Clock enable input
SDA
Serial data I/O
CS0,
RAS
Chip select input
Row address strobe
SCL
Serial clock
CAS
Address in EEPROM
No Connection
Column address strobe
SA0 ~ 2
NC
WE
Write enable
VDDID
VDD Identification flag
CB0 ~ CB7
Check bit (Data-in/data-out)
Reset
RESET ENABLE
2
White Electronic Designs Corporation •
(602) 437-1520 • www.whiteedc.com
WED3EG72256SXX-JD3
FUNCTIONAL BLOCK DIAGRAM:
VSS
RS0
DQS0
DQS0
CS
DQ0
DQ1
DQ2
DQ3
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQ8
DQ9
DQ10
DQ11
DQS
I/O 0
I/O 1
I/O 2
I/O3
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQ16
DQ17
DQ18
DQ19
CS
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O3
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQ32
DQ33
DQ34
DQ35
CS
DQ40
DQ41
DQ42
DQ43
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQ56
DQ57
DQ58
DQ59
DQS
I/O 0
I/O 1
I/O 2
I/O3
DM
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DQ12
DQ13
DQ14
DQ15
D1
DQ20
DQ21
DQ22
DQ23
D2
CS
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O3
CS
DM
D10
DM
D11
DQS12
DM
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM
D12
CKO
DM
DQ36
DQ37
DQ38
DQ39
D4
SDRAM
PLL
DQS13
DM
CKO
REGISTER
D13
DQS14
DQS5
DM
DQ44
DQ45
DQ46
DQ47
D5
DM
Serial PD
D14
SCL
WP
DQS15
DQS6
DM
DQ52
DQ53
DQ54
DQ55
D6
DM
SDA
A0
A1
A2
SA0 SA1 SA2
D15
DQS16
DQS7
DM
DQ60
DQ61
DQ62
DQ63
D7
DM
D16
VDDSPD
DQS
I/O 0
I/O 1
I/O 2
I/O3
CB0
CB1
CB2
CB3
R
E
G
I
S
T
E
R
CS
DM
D8
RS0A
RSOB
RBAO - RBAn
RAO - RA13
RRAS
RCAS
RCKE0A
RCKE0B
RWE
CB4
CB5
CB6
CB7
D17
BAO - BAn :SDRAMs DQ0 - D17
A0 - An :SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
CAS : SDRAMs DQ0 - D17
CKE : SDRAMs D0 - D8
CKE : SDRAMs D9 - D17
WE: SDRAMs D0 - D17
SPD
VDD/VDDQ
D0-D17
VREF
D0-D17
Vss
D0-D17
DQS17
DQS8
WE
PCK
PCK
DQS
I/O 0
I/O 1
I/O 2
I/O3
DM
D9
DQS11
DM
DQS3
CS0
CS
DQS10
DM
DQS2
BA0-BAN
A0-A13
RAS
CAS
CKE0
DQS
I/O 0
I/O 1
I/O 2
I/O3
D0-D17
DM
Notes"
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. Address and control resistors should be 22 Ohms.
RESET
3
White Electronic Designs Corporation •
(602) 437-1520 • www.whiteedc.com
WED3EG72256SXX-JD3
POWER & DC OPERATING CONDITIONS (SSTL_2 IN/OUT)
Recommend operating conditions (voltage referenced to Vss = øV, TA = ø to 70°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage (for device with a nominal VDD of 2.5V)
I/O Supply voltage
VDD
VDDQ
2.3
2.3
2.7
2.7
–
V
–
I/O Reference voltage
I/O Termination voltage (system)
VREF
VTT
VDDQ/2-50mV
VREF-0.04
VDDQ/2+50mV
VREF+0.04
V
V
1
2
Input logic high voltage
Input logic low voltage
VIH (DC)
VIL (DC)
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
V
V
4
4
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
VIN (DC)
VID(DC)
-0.3
0.3
VDDQ+0.3
VDDQ+0.6
V
V
3
Input leakage current
Output leakage current
I
IOZ
-2
-5
2
5
uA
uA
Output High Current (Normal strength driver); VOUT = VTT + 0.84V
Output High Current (Normal strength driver); VOUT = VTT - 0.84V
IOH
IOL
-16.8
16.8
mA
mA
Output High Current (Half strength driver); VOUT = VTT + 0.45V
Output High Current (Half strength driver); VOUT = VTT - 0.45V
IOH
IOL
-9
9
mA
mA
Notes:
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF,
both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,
and must track variations in the DC level of VREF.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The
AC and DC input specifications are relative to a VREF that has been bandwidth limited to 200MHZ.
AC OPERATING CONDITIONS
Parameter/Condition
Input High (Logic 1) Voltage,
Symbol
VIH (AC)
Min
VREF+ 0.31
Max
-
Unit
V
Note
3
Input Low (Logic 0) Voltage,
clock Input Differential Voltage, CK and CK inputs
clock Input Crossing Point Voltage, CK and CK inputs
VIL (AC)
VID (AC)
VIX (AC)
-VREF - 0.31
0.7
0.5XVDDQ-0.2
VDDQ+0.6
0.5XVDDQ+0.2
V
V
V
3
1
2
Notes:
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
The AC and DC input specifications are relation to VREF relation to a VREF envelope that has been bandwidth limited 20MHZ.
4
White Electronic Designs Corporation •
(602) 437-1520 • www.whiteedc.com
WED3EG72256SXX-JD3
IDD SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, TA = 0 to 70C, VDDQ = 2.5V +\-0.2V, VDD = 2.5V +\-0.2V)
Parameter
Operating Current
Operating Current
Precharge Power-Down
Symbol
IDD0
IDD1
IDD2P
Standby Current
Conditions
One device bank; Active = Precharge;
TRC=TRC (MIN); TCK=TCK
(MIN); DQ, DM and DQS inputs changing
once per clock cycle; Address and control
inputs changing once every two cycles.
One device bank; Active-Read-Precharge;
Burst = 2; TRC=TRC (MIN); TCK=TCK
(MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
All device banks idle; Power- down
DDR266@CL=2, 2.5
DDR200@CL=2
Max
Max
Units
1957
1900
mA
2632
2450
mA
135
125
mA
mode; TCK=TCK (MIN); CKE=(low)
dle Standby Current
IDD2F
CS# = High; All device
banks idle; TCK=TCK (MIN);
CKE = high; Address and other
control inputs changing once per clock
cycle. Vin = Vref for DQ, DQS and DM.
810
750
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Powerdown mode; TCK (MIN); CKE=(low)
405
385
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One
device bank; Active-Precharge;
TRC=TRAS (MAX); TCK=TCK (MIN);
DQ, DM and DQS inputs changing twice
per clock cycle; Address and other control
inputs changing once per clock cycle.
790
700
mA
3375
2970
mA
Burst = 2; Writes;
Continuous burst; One device
bank active; Address and control
inputs changing once per clock cycle;
TCK=TCK (MIN); DQ, DM and DQS
inputs changing twice per clock cycle.
3375
3250
mA
Operating Current
Operating Current
IDD4R
IDD4W
Burst = 2; Reads; Continuous
burst; One device bank active; Address
and control inputs changing once per
clock cycle; TCK=TCK (MIN); Iout = 0mA.
Auto Refresh Current
IDD5
TRC=TRC (MIN)
4455
4300
mA
Self Refresh Current
IDD6
CKE £ 0.2V
121
115
mA
Four bank interleaving Reads
(BL=4) with auto precharge with
TRC=TRC (MIN); TCK=TCK (MIN);
Address and control inputs change only
during Active Read or Write commands.
6682
6550
mA
Operating Current
IDD7A
Note: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
5
White Electronic Designs Corporation •
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WED3EG72256SXX-JD3
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
Row cycle time
Refresh row cycle time
262JD3
(DDR266@CL=2)
Min
Max
202JD3
(DDR200@CL=2)
Min
Max
Unit
tRC
65
65
70
ns
tRFC
75
75
80
ns
Row active time
tRAS
40
RAS to CAS delay
tRCD
20
Row precharge time
265JD3
(DDR266@CL=2.5)
Min
Max
120K
40
120K
20
48
120K
20
ns
ns
tRP
20
20
20
ns
tRRD
15
15
15
ns
Write recovery time
tWR
15
15
15
ns
Last data in to Read command
tWTR
1
1
1
tCK
Col. address to Col. address delay
tCCD
Row active to Row active delay
Clock cycle time
CL=2.0
CL=2.5
tCK
1
1
10
1
13
10
7.5
13
tCK
13
ns
5
ns
5
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tDQSCK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
Output data access time from CK/CK
tAC
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
Data strobe edge to output data edge
tDQSQ
0.5
Read Preamble
tRPRE
0.9
1.1
tCK
DQS-out access time from CK/CK
0.5
1.1
0.9
0.6
1.1
0.9
ns
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
tWPRE
0.25
0.25
0.25
tCK
DQS-in hold time
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
1.1
0.9
1.1
1.1
5
2
tDSC
0.9
Address and Control Input setup time (fast)
tIS
0.9
0.9
1.1
ns
Address and Control Input hold time (fast)
tIH
0.9
0.9
1.1
ns
i,6
Address and Control Input setup time (slow)
tIS
1.0
1.0
1.1
ns
i, 6
ns
i, 6
Address and Control Input hold time (slow)
tIH
1.0
Data-out high impedance time from CK/CK
tHZ
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
+0.75
-0.75
+0.75
-0.8
+0.8
Data-out low impedance time from CK/CK
1.0
0.9
Note
1.1
tCK
i,6
ns
tLZ
-0.75
tSL(I)
0.5
0.5
0.5
V/ns
6
Input Slew Rate (for I/O pins)
tSL(IO)
0.5
0.5
0.5
V/ns
7
Output Slew Rate (x4,x8)
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
10
Output Slew Rate Matching Ratio (rise to fall) tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
Input Slew Rate (for input only pins)
6
White Electronic Designs Corporation •
ns
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WED3EG72256SXX-JD3
SYSTEM CHARACTERISTICS FOR DDR SDRAM
The following specification parameters are required in systems using DDR266 & DDR200 devices to ensure proper system performance. These
characteristics are for system simulation purposes and are guaranteed by design.
Parameter
Symbol
262JD3
265JD3
202JD3
(DDR266@CL=2)
(DDR266@CL=2.5)
(DDR200@CL=2)
Min
Max
Min
Max
Min
Unit
Note
Max
Mode register set cycle time
tMRD
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.5
0.5
0.6
ns
j, k
DQ & DM hold time to DQS
tDH
0.5
0.5
0.6
ns
j, k
Control & Address input pulse width
t lPW
2.2
2.2
2.5
ns
8
DQ & DM unput pulse width
t DIPW
1.75
1.75
2
ns
8
Power down exit time
t PDEX
7.5
7.5
10
ns
Exit self refresh to non-Read command
t XSNR
75
75
80
ns
Exit self refresh to read command
t XSRD
200
200
200
tCK
Refresh interval time
t REFl
7.8
t HP
tQHS
t CLmin
or tCH min
Output DQS valid window
tQH
Clock half period
t HP
Data hold skew factor
tQHS
DQS write postamble time
0.75
7.8
t HP
tQHS
t CLmin
or t CH min
0.6
0.4
7.8
t HP
tQHS
t CLmin
or t CH min
0.75
t QPST
0.4
0.6
Active to Read with Auto precharge command
t RAP
20
20
20
Auto precharge write revovery + Precharge time
tDAL
(t WR /t CK )
+
(t WR /t CK )
+
(t WR/t CK )
+
-
0.4
us
4
ns
11
-
ns
10, 11
0.8
ns
11
0.6
tCK
2
tCK
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
VIN, Vout
VDD, VDDQ
TSTG
PD
IOS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
27
50
Units
V
V
°C
W
mA
Notes:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE (TA = 25°C, F = 1MHZ, VDD = 2.5V)
Parameter
Input Capacitance (A0-A13)
Input Capacitance (RAS, CAS, WE)
Input Capacitance (CKE0)
Input Capacitance (CK0, CK0)
Input Capacitance (CS0)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63) (DQS)
Data input/output capacitance (CB0-CB7)
7
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
Cout
Cout
Min
-
Max
12
12
12
12
11
11
12
11
11
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WED3EG72256SXX-JD3
COMMAND TRUTH TABLE
(V = Valid, X = Don't Care, H = Logic High, L = Logic Low)
COMMAND
CKEn-1 CKEn CS
RAS
CAS WE
BA0,1
A10/AP
A0~A9
A11, A13
Note
Register
Extended MRS
H
X
L
L
L
L
OP Code
1,2
Register
Mode register Set
H
X
L
L
L
L
OP Code
1,2
H
H
L
L
L
L
H
X
3
3
L
H
L
H
H
X
H
X
H
X
X
3
3
H
X
L
L
L
L
V
H
X
L
H
L
H
V
H
X
L
H
L
L
V
H
X
L
H
H
L
H
X
L
L
H
L
X
V
X
V
X
V
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read &
Auto Precharge
Column Address Disable
Write &
Auto Precharge Enable
Column Address Auto Precharge Disable
Burst Stop
Precharge
Auto Precharge Enable
Bank Selection
All Banks
Active Power Down
Entry
H
L
H
L
Exit
L
H
X
X
X
X
Entry
H
L
Exit
L
H
H
L
H
L
X
H
X
V
X
X
H
X
V
X
H
X
V
H
L
X
H
X
H
X
H
Precharge Power Down
Mode
DM
Non Operation (NOP):Not Defined
H
H
X
Row Address
(A0~A9, A11,A13)
L
Column
Address
H
L
H
Column
Address
L
H
4
4.6
7
X
V
X
4
4
X
5
X
X
X
X
8
9
9
Notes:
1. OP Code: Operand Code. A0~A 13 & BA 0 ~ BA 1: Program keys (@EMRS/MRS)
2. EMRS/MRS can be issued only at all blanks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA 0 ~ BA 1: Bank select addresses.
If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA 0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10 /AP is "High" at row precharge, BA 0 and BA 1 are ignored and all blanks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued at tRP after the end of the burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation (NOP)" in DDR SDRAM.
8
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WED3EG72256SXX-JD3
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1:OPERATING CURRENT:ONE BANK
1.
2.
3.
Typical Case : Vdd = 2.5V, T = 25'C
Worst Case : Vdd = 2.7V, T = 10'C
Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per
clock cycle.
Iout = 0mA
Timing patterns
- 202JD3, DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
4.
-
265JD3, DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
-
262JD3, DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
ORDERING INFORMATION
Part Number
WED3EG72256S202JD3-M
WED3EG72256S262JD3-M
WED3EG72256S265JD3-M
Density
2GB
2GB
2GB
Speed
100MHz/CL=2
133MHz/CL=2
133MHz/CL=2.5
Organization
256M x 72
256M x 72
256M x 72
Height
1.2 in
1.2 in
1.2 in
M = Micron ® Die
PACKAGE DIMENSIONS
5.255 MAX.
.150
MAX.
.157
(4x)
1.200
MAX.
.700
.394
.157 MIN.
P1
.050 TYP.
.250
1.950
2.550
.250
.118
(4X)
.050
+/- .004
.070
All dimensions are in inches.
9
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WED3EG72256SXX-JD3
Document Title
2GB- 256Mx72, ECC, DDR SDRAM DIMM Registered Module
Revision History
Rev # History
Release Date
Status
Rev 0
January 2004
Advanced
Initial Release
10
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