ETC HYM4V33100BTWG-75

1Mx32 bits
PC133 SDRAM AIMM
based on 1Mx32 SDRAM with LVTTL, 2 banks & 4K Refresh
HYM4V33100BTWG Series
DESCRIPTION
The Hynix HYM4V33100BTWG
Series are 1Mx32bits Synchronous DRAM Modules. The modules are composed of one 1Mx32bits
CMOS Synchronous DRAMs in 400mil 86pin TSOP-II package, on a 132pin glass-epoxy printed circuit board. Two 0.22uF and one
0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hyundai HYM4V33100BTWG
Series are AGP In-line Memory Modules suitable for easy interchange and addition of 4Mbytes
memory. The Hyundai HYM4V33100BTWG
Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
•
PC133/PC100MHz support
•
Module bank : one physical bank
•
132pin SDRAM
•
Auto refresh and self refresh
•
1.4” (35.56mm) Height PCB with double sided com-
•
4096 refresh cycles / 64ms
•
Programmable Burst Length and Burst Type
AIMM
ponents
•
Single 3.3±0.3V power supply
•
All device pins are compatible with LVTTL interface
•
Data mask function by DQM
•
SDRAM internal banks : two banks
- 1, 2, 4 or 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock
Frequency
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
HYM4V33100BTWG-75
133MHz
2 Banks
4K
Normal
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.1/Apr.01
PC133 SDRAM AIMM
HYM4V33100BTWG Series
PIN DESCRIPTION
PIN
PIN NAME
CK0, CK1
Clock Inputs
CKE
Clock Enable
/CS
Chip Select
BA
SDRAM Bank Address
A0 ~ A10
Address
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
Row Address Strobe, Column
/RAS, /CAS and /WE define the operation
Address Strobe, Write Enable
Refer function truth table for details
DQM0~DQM3
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31
Data Input/Output
Multiplexed data input / output pin
VCC
Power Supply (3.3V)
Power supply for internal circuits and input buffers
VSS
Ground
Ground
NC
No Connection
No connection
/RAS, /CAS, /WE
Rev. 0.1/Apr.01
2
PC133 SDRAM AIMM
HYM4V33100BTWG Series
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
FRONT SIDE
BACK SIDE
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
1
NC
2
TYPEDET
67
NC
68
NC
3
NC
4
NC
69
NC
70
NC
5
GND
6
NC
71
GND
72
NC
7
NC
8
NC
73
NC
74
DQ27
9
VCC
10
DQM3
75
VCC
76
DQ28
11
NC
12
DQ24
77
DQ29
78
DQ30
13
GND
14
NC
79
GND
80
NC
15
DQ25
16
VCC
81
DQ31
82
VCC
17
DQ26
18
NC
83
DQM2
84
NC
19
GND
20
WE
85
GND
86
DQ23
21
FSEL
22
KEYWAY
87
DQ22
88
KEYWAY
23
KEYWAY
24
KEYWAY
89
KEYWAY
90
KEYWAY
25
KEYWAY
26
TCLK0
91
KEYWAY
92
DQ21
27
TCLK1
28
VCC
93
DQ20
94
VCC
29
CAS
30
NC
95
DQ19
96
DQ18
31
GND
32
NC
97
GND
98
NC
33
RAS
34
VDDQ
99
DQ17
100
VDDQ
35
A0
36
A9
101
DQ16
102
DQ15
37
GND
38
A11
103
GND
104
DQ14
39
A8
40
VDDQ
105
DQ13
106
VDDQ
41
A10
42
NC
107
DQ12
108
NC
43
GND
44
NC
109
GND
110
NC
45
VCC
46
A7
111
VCC
112
DQ11
47
CS
48
NC
113
VDDQ
114
NC
49
GND
50
A6
115
GND
116
NC
51
A1
52
VDDQ
117
DQ10
118
VDDQ
53
A5
54
A2
119
DQ9
120
DQ8
55
GND
56
A4
121
GND
122
DQM1
57
A3
58
VDDQ
123
DQ0
124
VDDQ
59
NC
60
DQ5
125
NC
126
DQ1
61
GND
62
DQ6
127
GND
128
DQ2
63
DQ7
64
VDDQ
129
DQ3
130
VDDQ
65
DQM0
66
NC
131
DQ4
132
NC
Rev. 0.1/Apr.01
3
PC133 SDRAM AIMM
HYM4V33100BTWG Series
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TS T G
-55 ~ 125
°C
Voltage on Any Pin relative to V S S
V IN, V O U T
-1.0 ~ 4.6
V
Voltage on V D D relative to V S S
VDD, VD D Q
-1.0 ~ 4.6
V
Short Circuit Output Current
IO S
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ T i m e
TSOLDER
260 ⋅ 10
°C ⋅ S e c
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION
Parameter
(T A = 0 t o 7 0 ° C )
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
VD D , VDDQ
3.0
3.3
3.6
V
1
Input High voltage
V IH
2.0
3.0
V DDQ + 0.3
V
1,2
Input Low voltage
V IL
-0.3
0
0.8
V
1,3
Note
Note :
1.All voltages are referenced to VSS = 0 V
2.V IH( m a x ) i s a c c e p t a b l e 5 . 6 V A C p u l s e w i d t h w i t h < = 3 n s o f d u r a t i o n .
3 . V I L( m i n ) i s a c c e p t a b l e - 2 . 0 V A C p u l s e w i d t h w i t h < = 3 n s o f d u r a t i o n .
A C O P E R A T I N G T E S T C O N D I T I O N (TA =0
t o 7 0° C , V D D = 3 . 3 ± 0 . 3 V , V S S = 0 V )
Parameter
Symbol
Value
Unit
AC Input High / Low Level Voltage
V IH / V IL
2.4/0.4
V
Vtrip
1.4
V
tR / tF
1
ns
Voutref
1.4
V
CL
50
pF
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
1
Note :
1 . O u t p u t l o a d t o m e a s u r e a c c e s s t i m e s i s e q u i v a l e n t t o t w o T T L g a t e s a n d o n e c a p a c i t o r ( 5 0 p F ) . F o r d e t a i l s , r e f e r t o A C / D C o u t p ut
load circuit
Rev. 0.1/Apr.01
4
PC133 SDRAM AIMM
HYM4V33100BTWG Series
CAPACITANCE
( T A = 2 5° C , f = 1 M H z )
-75
Parameter
Pin
Symbol
Unit
Min
Max
CK0, CK1
CI1
5
10
pF
CKE0, CKE1
CI2
5
10
pF
/S0, /S1
CI3
10
15
pF
A0~10, BA0
CI4
10
20
pF
/RAS, /CAS, /WE
CI5
10
20
pF
DQM0~DQM3
C I6
5
10
pF
C I/O
5
15
pF
Input Capacitance
Data Input / Output Capacitance
DQ0 ~ DQ31
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
DC Output Load Circuit
Rev. 0.1/Apr.01
50 pF
AC Output Load Circuit
5
PC133 SDRAM AIMM
HYM4V33100BTWG Series
( T A = 0 t o 7 0 ° C , V DD =3.3 ± 0.3V)
DC CHARACTERISTICS I
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
IL I
-8
8
uA
1
Output Leakage Current
IL O
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IO H = - 4 m A
Output Low Voltage
VOL
-
0.4
V
IO L = + 4 m A
Note :
1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V
2.DO U T is disabled, V O U T =0 to 3.6
DC CHARACTERISTICS II
Speed
Parameter
Symbol
Test Condition
Unit
Note
mA
1
-75
Operating Current
Precharge Standby Current
in Power Down Mode
ID D 1
Burst length=1, One bank active
220
t R C ≥ tR C ( m i n ) , I O L = 0 m A
ID D 2 P
C K E ≤ V IL ( m a x ) , t C K = m i n
ID D 2 P S
C K E ≤ V IL ( m a x ) , t C K =
2
mA
∞
2
C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K = m i n
ID D 2 N
Input signals are changed one time during
in Non Power Down Mode
ID D 2 N S
Active Standby Current
in Power Down Mode
40
2 c l k s . A l l o t h e r p i n s ≥ V D D - 0 . 2 V o r ≤ 0.2V
Precharge Standby Current
C K E ≥ V IH ( m i n ) , t C K =
∞
30
Input signals are stable.
ID D 3 P
C K E ≤ V IL ( m a x ) , t C K = m i n
ID D 3 P S
C K E ≤ V IL ( m a x ) , t C K =
mA
60
mA
∞
60
C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K = m i n
ID D 3 N
Input signals are changed one time during
100
2 c l k s . A l l o t h e r p i n s ≥ V D D - 0 . 2 V o r ≤ 0.2V
Active Standby Current
mA
in Non Power Down Mode
ID D 3 N S
C K E ≥ V IH ( m i n ) , t C K =
∞
60
Input signals are stable.
Burst Mode Operating
Current
ID D 4
t C K ≥ t C K ( m i n ) , IO L = 0 m A
All banks active
Auto Refresh Current
ID D 5
tR R C ≥ tR R C ( m i n ) , A l l b a n k s a c t i v e
Self Refresh Current
ID D 6
C K E ≤ 0.2V
CL=3
220
mA
1
220
mA
2
4
mA
3
Note :
1. ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HYM4v33100BTWG-75
Rev. 0.1/Apr.01
6
PC133 SDRAM AIMM
HYM4V33100BTWG Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-75
Parameter
Symbol
Unit
Min
System Clock
Cycle Time
C A S Latency = 3
tCK3
Note
Max
7.5
ns
1000
tCK2
10
Clock High Pulse Width
tCHW
2.5
-
ns
1
Clock Low Pulse Width
tCLW
2.5
-
ns
1
C A S Latency = 3
tAC3
-
5.4
ns
C A S Latency = 2
tAC2
-
6
ns
Access Time
From Clock
C A S Latency = 2
ns
2
Data-Out Hold Time
tOH
2.7
-
ns
Data-Input Setup Time
tDS
1.5
-
ns
1
Data-Input Hold Time
tDH
0.8
-
ns
1
Address Setup Time
tAS
1.5
-
ns
1
Address Hold Time
tAH
0.8
-
ns
1
CKE Setup Time
tCKS
1.5
-
ns
1
CKE Hold Time
tCKH
0.8
-
ns
1
Command Setup Time
tCS
1.5
-
ns
1
Command Hold Time
tCH
0.8
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
ns
CLK to Data
Output in High-Z
C A S Latency = 3
tOHZ3
2.7
5.4
ns
Time
C A S Latency = 2
tOHZ2
3
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.1/Apr.01
7
PC133 SDRAM AIMM
HYM4V33100BTWG Series
AC CHARACTERISTICS II
-75
Parameter
Symbol
Unit
Min
Max
Operation
tRC
65
-
ns
Auto Refresh
tRRC
65
-
ns
R A S to C A S Delay
tRCD
20
-
ns
R A S Active Time
tRAS
45
100K
ns
RAS Precharge Time
tRP
20
-
ns
R A S to R A S Bank Active Delay
tRRD
15
-
ns
C A S to C A S Delay
tCCD
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
CLK
Data-In to Precharge Command
tDPL
2
-
CLK
Data-In to Active Command
tDAL
5
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
CLK
MRS to New Command
tMRD
2
-
CLK
C A S Latency = 3
tPROZ3
3
-
CLK
C A S Latency = 2
tPROZ2
2
-
CLK
Power Down Exit Time
tPDE
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
CLK
Refresh Time
tREF
-
64
ms
Note
R A S Cycle Time
Precharge to Data
Output Hi-Z
1
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.1/Apr.01
8
PC133 SDRAM AIMM
HYM4V33100BTWG Series
DEVICE OPERATING OPTION TABLE
HYM4V33100BTWG-75
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
133MHz(7.5ns)
COMMAND TRUTH TABLE
Command
A10/
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
ADDR
RA
Read
BA
Note
V
L
CA
Read with Autoprecharge
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Precharge selected Bank
Burst Stop
H
DQM
H
Auto Refresh
H
H
L
L
L
Entry
H
L
L
L
X
L
H
H
H
X
Exit
L
H
L
X
L
V
X
V
X
H
X
X
L
H
X
X
X
X
X
L
H
H
H
H
X
X
X
Precharge
L
H
H
H
power down
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
H
X
X
X
Self Refresh1
Entry
V
H
Precharge All Banks
L
X
X
Exit
Clock
AP
Entry
L
H
H
L
Suspend
Exit
L
X
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2 . X = D o n′ t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s ,
Opcode = Operand Code, NOP = No Operation
Rev. 0.1/Apr.01
9
PC133 SDRAM AIMM
HYM4V33100BTWG Series
PACKAGE DEMENSION
¢3.175 x4
x
Rev. 0.1/Apr.01
10