ETC PEF2426

D at a S h e et , D S 1 , O c t o be r 20 0 1
QIHPC
QUAD ISDN/S(H)DSL
High Voltage Power
Controller
PE F 24 26 Ve rsi on 1.1
Wi re d
C om m un ic a t io ns
N e v e r
s t o p
t h i n k i n g .
Edition 2001-10-31
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 31. 10. 01.
All Rights Reserved.
Attention please!
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characteristics.
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circuits, descriptions and charts stated herein.
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Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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list).
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be endangered.
D at a S h e et , D S 1 , O c t o be r 20 0 1
QIHPC
QUAD ISDN/S(H)DSL
High Voltage Power
Controller
PE F 24 26 Ve rsi on 1.1
Wi re d
C om m un ic a t io ns
N e v e r
s t o p
t h i n k i n g .
PEF 2426
Revision History:
2001-10-31
Previous Version:
06.99 (Preliminary Data Sheet DS 1)
Page
Subjects (major changes since last revision)
6
feature-comparison IEPC vs. QIHPC for S-feeding
17
Updated proposal for the protection circuitry
22
Table 5 Item 5
DS 1
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 2426
Table of Contents
Page
1
1.1
1.2
1.3
1.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration
(top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
3.4
3.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Biasing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Feed Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Current Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relays Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
13
14
4
4.1
4.2
4.3
4.4
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistor RS1..4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistor RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitor CS1..4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
17
5
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
6.1
6.2
6.3
6.4
6.5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing the Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Sheet
1
2
3
4
6
20
20
21
21
21
23
2001-10-31
PEF 2426
List of Figures
Page
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
16-Line Card Application with DELIC, DFE-Q/T and AFE . . . . . . . . . . . 4
System integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Delay time tOC as a function of the value of CS1..4 (typical values). . 16
Proposal for a Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Circuit with “LT Power Source Test Loads” . . . . . . . . . . . . . . . . . . . . . 18
Simultaneous Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Line Currents and Delay Time tOC . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DMOS-RON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PF1..4, Logic Input Levels and NACK1..4, Logic Output Levels . . . . . 25
RDin1..8, Relay Driver Inputs and RDout1..8 Relay Driver Outputs . . 26
Test circuit for maximum DC-voltages, pulse voltages and impulse
voltages on pins D1..4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Sheet
2001-10-31
PEF 2426
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Data Sheet
Page
Comparing the Power Feeeding IC's: IEPC vs. QIHPC. . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Detector Threshold Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Function Table for Controlling One Line . . . . . . . . . . . . . . . . . . . . . . . 13
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2001-10-31
PEF 2426
Overview
1
Overview
The QUAD ISDN/S(H)DSL High Voltage Power Controller provides a power source for
up to four U-line interfaces or S-interfaces. The power source to the device is a local
battery or a centralized power supply.
Each powered line is individually controlled and monitored by the device interface. Line
powering can be switched on or off by command. The QIHPC indicates, when the output
current is above a threshold for longer than the programmable time tOC. At a second
(higher) value the current is limited. The values of the current limitation and the
overcurrent indication threshold are defined with external resistors, the overcurrent
indication setup delay is selected by external capacitances.
The status information of each line (acknowledge of requested power feed) is returned
to the system. The status information enables an easy detection of overloads and faults
and a fast localization even on a large system.
The integrated intelligent chip temperature control guards the QIHPC in case of
overloads.
Additionally eight drivers for external relays and their control logic are integrated on the
QIHPC. These relay drivers provide open collector output stages with high current
capability.
Data Sheet
1
2001-10-31
QUAD ISDN/S(H)DSL High Voltage Power Controller
QIHPC
Version 1.1
1.1
PEF 2426
SPT 170
Features
• Supplies power for up to four ISDN or S(H)DSL
transmission lines on Central Office and DSLAM
Linecards
• ETSI TS 102 080 compatible
• TS 101 524 and ITU-T G.991.2 Annex B compatible
• Feediing of multiple S/T interfaces in IADs and
PBXs.
• Line Feed Supply Voltage up to 130 V
P-MQFP-44
• Separate Current Monitoring and Limiting for each line
• Current Limiting Level can be programmed by an external resistor
• Overcurrent indication threshold can be programmed with external resistors
independently from the current limitation.
• The overcurrent indication setup delay can be programmed by external capacitors,
separately for each line
• Intelligent Chip Temperature Control
• Automatically switching off lines in current limitation when expecting over temperature
problems
• Automatically switching off all four lines in case of real overtemperature
• Integrated Relay Drivers and Relay Driver Controlling for eight relays
• Optimized for working in conjunction with PEB/F 24901 (DFE-T) and PEB/F 24911
(DFE-Q).
• Small P-MQFP-44 Package
• Reliable 170 V Smart Power Technology
Type
Package
PEF 2426
P-MQFP-44
Data Sheet
2
2001-10-31
PEF 2426
Overview
1.2
Logic Symbol
•
Relay Driver
input pins
Relay Driver pins
RDin1 . . . RDin8
Figure 1
Data Sheet
D1
D2
D3
D4
QIHPC
VILF
PF1
PF2
PF3
PF4
Power Feed
Control Pins
Battery
Voltage
Power Feed
VDD
GND
NACK1
NACK2
NACK3
NACK4
Power Feed
Status Pins
RDout1 . . . RDout8
S1 . . . S4
CS1 . . . CS4
RFpos RFneg
Current
Sensing
Capacitor low
pass filter
Current
Sensing
Logic Symbol
3
2001-10-31
PEF 2426
Overview
1.3
Typical Applications
The QIHPC is an integrated power controller especially designed for feeding two-wire
ISDN/S(H)DSL-transmission lines. Four U interface lines can be powered by one
QIHPC.
Test Unit
1
AFE
V2.1
2
PEF 24902
DFE-Q/T
V2.1
PEF 24911
PEF 24901
PCM HW
IOM-2
DELIC
PEB 20570
Signalling
3
4
Q-IHPC
RAM
PEF 2426
VILF
Figure 2
Data Sheet
µC
GND
16-Line Card Application with DELIC, DFE-Q/T and AFE
4
2001-10-31
PEF 2426
Overview
•
Uk0
Channel1
AC-Path
Channel 1
VDD
VDD
OVP1
Uk0
Channel2
AC-Path
Channel 2
RDin1 . . . RDin8
RDout1 . . . RDout8
VDD
VDD
VDD
D1
OVP2
Uk0
Channel3
PF1
PF2
PF3
PF4
D2
D3
AC-Path
Channel 3
QIHPC
D4
NACK1
NACK2
NACK3
NACK4
VILF
VILF
OVP3
GND
S1 . . . S4
CS1 . . . CS4
RS1..4
Uk0
AC-Path
Channel 4
RFneg
CS1..4
4∗ 2Ω
Channel4
RFpos
4 ∗ 220 nF
VILF
RF
1700 Ω
VILF
OVP4
Figure 3
System integration
Figure 3 gives general overview of the system integration of the QIHPC.
Due to the integrated “pull-down current-sinks” on the input pins PF1..4 and RDin1..8 only
connections to VDD are necessary to switch on power feeding to the lines or to switch on
the relay drivers. When power feeding to a line is switched on, and this line is in a normal
feeding condition (current less than the current limiting level), then the QIHPC shows a
resistive connection from Dx to Sx. Dx and Sx are the drain and source of the integrated
DMOS-transistor of channel x. The resistance value (DMOS-Ron) is typically 1.4 Ω with
a total tolerance of about +/- 0.35 Ω.
Data Sheet
5
2001-10-31
PEF 2426
Overview
1.4
S/T-Feeding
Due to its functional similarity to the PEB 2025 IEPC, the QIHPC can be used as a
replacement for the PEB 2025 in applications such as current feeding at multiple S
interfaces:
•
Table 1
Comparing the Power Feeeding IC's: IEPC vs. QIHPC
PEB 2025 IEPC
PEF 2426 QIHPC
Vbat Range
-60V to -12V
-130V to - 30V
Channels
4
4
Vbat supply current (excl.
Line feeding currents)
0.2mA max.
1mA max
Dig. supply voltage
4.75V to 5.25V
+3V to +6V
Dig. supply current (@ 5V)
5mA typ.; 10mA max.
0.7mA typ.; 1.5mA max.
Feeding current control
System controlled turn- Automatic current limitation;
on; automatic turn-off
system controlled turn-off
Specified feeding current
control settings
75mA; 152mA
(approx. +25%)
Turn-on resistance
7Ohm typ., 9 Ohm max. 1.4 Ohm typ., 2 Ohm max.
System interface
Parallel µP i/f (9 pins)
8 I/O pins
Relay drivers integrated
None
8
67 up to 150mA (+12%)
possible
Operating temperature range 0 to 70 °C
-40 to +85°C (PEF)
Package
P-MQFP-44
Data Sheet
P-LCC-28; P-DIP-22
6
2001-10-31
PEF 2426
Pin Descriptions
Pin Descriptions
2.1
Pin Configuration
(top view)
RDin4
RDout4
RDout3
RDout2
RDout1
VDD
RDout5
RDout6
RDout7
RDout8
RDin8
2
RDin7
RDin6
RDin5
GND
D4
S4
CS4
CS3
S3
D3
GND
RFpos
RFneg
GND
PF1
PF2
PF3
PF4
NACK1
NACK2
NACK3
NACK4
RDin3
RDin2
RDin1
GND
D1
S1
CS1
CS2
S2
D2
VILF
Figure 4
Data Sheet
Pin Configuration
7
2001-10-31
PEF 2426
Pin Descriptions
2.2
Pin Definitions and Functions
•
Table 2
Pin Definitions and Functions
Pin No. Symbol Input (I)
Function
Output (O)
28
VDD
Supply
Positive Supply Voltage, referred to GND.
Operating Voltage Range from 3.0 V to 6.0 V.
3
12
19
37
GND
Supply
Ground
44
VILF
Supply
Line Feed Voltage, referred to GND.
Operating Voltage Range from -130 V to -30 V.
38
43
13
18
D1
D2
D3
D4
O
Drain Connections of the Output Transistors
of Channels 1..4.
These pins have to be connected (via external
resistors) to ISDN/S(H)DSL lines a (ring) of channels
1..4.
1
2
RFpos
RFneg
O
Current limitation of Channels 1..4.
These pins have to be connected to an external
resistor RF. RF and RS1..4 are defining the output current
limit for all four lines.
39
42
14
17
S1
S2
S3
S4
O
Overcurrent indication threshold.
These pins have to be connected via external resistors
RS1..4 to VILF defining the overcurrent indication
threshold of each line individually.
40
41
15
16
Cs1
Cs2
Cs3
Cs4
O
External capacitors defining t OC-delays of
Channels 1..4.
These pins have to be connected via external
capacitors to VILF defining the overcurrent indication
delay.
4
5
6
7
PF1
PF2
PF3
PF4
PD
Power Feed Signal of Channels 1..4.
Logic high on PF1..4 switches on the power feeding to
the line of channel 1..4.
Data Sheet
8
2001-10-31
PEF 2426
Pin Descriptions
Table 2
Pin Definitions and Functions (Continued)
Pin No. Symbol Input (I)
Function
Output (O)
8
9
10
11
NACK1
NACK2
NACK3
NACK4
O
Not Acknowledged Signal of Channels 1..4.
Logic low on NACK1..4 signals that either the ISDN/
S(H)DSL line of channel 1..4 is powered and in a
normal power on condition or that power feed is not
requested..
36
35
34
33
20
21
22
23
RDin1
RDin2
RDin3
RDin4
RDin5
RDin6
RDin7
RDin8
PD
Switch-On-Signal of Relay-Channels 1..8.
Logic high on Rin1..8 switches on the relay driver npntransistor of channel 1..8.
29
30
31
32
27
26
25
24
RDout1
RDout2
RDout3
RDout4
RDout5
RDout6
RDout7
RDout8
O
Open Collector Output of Relay-Channels 1..8.
When the relay driver npn-transistor of channel 1..8 is
switched on, than this pin sinks a current of up to
40 mA.
An integrated zener diode guards the QIHPC against
inductive voltage peaks from the relay coil.
Data Sheet
9
2001-10-31
PEF 2426
Functional Description
3
Functional Description
3.1
Functional Block Diagram
•
VDD
GND
Biasing
RDin1..8
2 kΩ
9.3 V
Junction
Temperature
Control
Bandgap
RDout1..8
20 µA
4 * 10 µ A
Relay Drivers
20 µA
PF1..4
20 µA
NACK1..4
Logic
Line Feed Control
D1..4
Line Current Control
DMOS
TF
DPS
S1..4
DPD
1 µA
ZDGS
+
+
T UF
-
RDC
RFpos
OPF
10..100 mV +/-20%
RFneg
OPDC
100 mV +/-10%
RSubstrat
Substrat
VILF
CS1..4
Figure 5
Data Sheet
Functional Block Diagram
10
2001-10-31
PEF 2426
Functional Description
In the Functional Block Diagram, Figure 5, we can see four different types of circuit
blocks: one biasing circuit, four line feed control circuits, four line current control circuits
and eight relay driver circuits.
3.2
Biasing Circuit
The bandgap circuit generates a constant voltage with respect to GND. This reference
voltage is converted into a current of about 20 µA which is necessary for level shifting.
This current is converted back into 100 mV and 10..100 mV (depending on the value of
the external resistor RF) reference voltages with respect to VILF. These reference
voltages and the external resistors connected between pins S1..4 and VILF defines the line
current limit and the overcurrent indication threshold.
Currents of about 10 µA are used for level shifting the power feed information. In the
biasing block also all other biasing currents used on the chip are generated.
Intelligent junction temperature control in coordination with line current limiting protects
the QIHPC against overloads. Also a fault condition on one line shall under no
circumstance disturb a connection on another line. Therefore a junction temperature
control circuit is necessary.
The junction temperature of the QIHPC will be monitored by an integrated thermal
detector with three threshold levels, as defined in Table 3
Table 3
Thermal Detector Threshold Levels
Symbol Parameter Description
Test Conditions
Limits
Unit
Min Typ Max
Tj1
130 °C Thermal Detector
threshold
guaranteed by
design
120 130 140
°C
Th1
130 °C Thermal Detector
hysteresis
guaranteed by
design
10
°C
Tj2
170 °C Thermal Detector
threshold
guaranteed by
design
160 170 180
°C
Th2
170 °C Thermal Detector
hysteresis
guaranteed by
design
10
°C
Tj3
190 °C Thermal Detector
threshold
guaranteed by
design
180 190 200
°C
Th3
190 °C Thermal Detector
hysteresis
guaranteed by
design
10
°C
Power on requests will only be executed if the junction temperature is below Tj1 (typical
130 °C) and if no other line is in overcurrent condition. If the device junction temperature
reaches the second threshold Tj2 (typical 170 °C), then all the line drivers in the currentData Sheet
11
2001-10-31
PEF 2426
Functional Description
overload condition will be switched off by the QIHPC. If the device junction temperature
then still continues to increase to Tj3 (typical 190 °C), all the line drivers will be turned off
by the QIHPC.
The line(s) in current overload will be switched off sufficiently fast once the second
threshold Tj2 is reached, i.e. before the Tj3 threshold is reached. This guarantees a
disturbance free operation on lines not affected by a fault condition. Once a line had
been switched off the relevant PF-pin has to be set to low and subsequently to high, for
attempting to power this line again.
The internal protection mechanisms (current limiting and junction temperature control)
already provide full protection of the D1..4 outputs against short circuits to a voltage
between GND and VILF .
Note: The thermal protection mechanism of the QIHPC is a protection against instant
damages due to overload at the outputs. Continuous high temperatures during
operation, however, will reduce the life time of the QIHPC. Measures have to be
taken to switch off the QIHPC in case of a short-circuit. E.g. if pin NACKx indicates
an current overload condition, the QIHPC should be deactivated after few seconds
using pin PFx.
3.3
Line Feed Control Circuit
The QIHPC can supply the power for up to four transmission lines simultaneously. The
exchange of activation commands and status information with the QIHPC will occur via
a parallel interface, consisting of one input (PF) and one output (NACK) per line. The
power switch can be controlled (PF) for each line individually. The status information
(NACK) can be monitored for each line separately.
Integrated “pull-down current-sinks” are connected to the input pins PF1..4. If one of these
pins is not connected externally, the logic level at this pin is “0”.
Logic level “0” means that the voltage on this pin is about 0 and logic level “1” means that
the voltage level on this pin is about VDD.
A diagnostic of possible fault conditions is available on the status information pins
(NACK) for each line separately.
The NACK pin is set to “1” when PF=”1” and:
- Current on the line reaches the overcurrent indication threshold for longer than tOC.
- Over temperature (Tj > Tj3) is detected.
- Power feed setting is not acknowledged by the QIHPC.
Data Sheet
12
2001-10-31
PEF 2426
Functional Description
See also Table 4.
Table 4
PF
Function Table for Controlling One Line
current
current
Tj
NACK Comment
(other channels) (this channel)
0
don’t care
don’t care
don’t care 0
line feeding not requested
0 → 1 at least one
above
indication
threshold
don’t care
don’t care 1
power feeding not
acknowledged and the line is
not powered as long as an
other line is in overcurrent
condition
0 → 1 don’t care
don’t care
> Tj1
1
power feeding not
acknowledged and the line is
not powered, as long as the
junction temperature is to high
1
don’t care
above
indication
threshold
< Tj2
1
feeding: this line is in over
current condition
1
don’t care
below
indication
threshold
< Tj3
0
normal line feeding
1
don’t care
don’t care
> Tj3
1
overtemperature condition,
feeding is switched off
In case of simultaneous power up requests (PF1..4) the QIHPC take care of a proper
start-up sequencing. The four channels have different priority. First priority for channel
1, second priority for channel 2 etc.
By simultaneous power up requests on more than one channel, the channel with the
highest priority will be powered first, and will normally start with current limiting condition.
When this channel is powered up and the drawn current drops below the current
indication level, the next channel will be powered. And so on (see also figure 6 and
table 3).
3.4
Line Current Control Circuit
Two different current limiting circuits are integrated to control the DMOS power switch.
An ultrafast and a fast current limiting circuit. See also Figure 5.
The ultrafast current limiting circuit consists of a bipolar npn-transistor TUF. Note that
bipolar npn-transistors are the fastest devices from the used technology. If the voltage
Data Sheet
13
2001-10-31
PEF 2426
Functional Description
between S1..4 and VILF exceeds about 0.7 V the DMOS is switched off as fast as possible.
0.7 V divided by RS1..4 = 2 Ω results in an ultrafast current limiting level of about 350 mA.
This level has a strong temperature dependence (-40 °C junction temperature gives
about 420 mA and +120 °C results in about 300 mA). The ultrafast current limiting circuit
protects the QIHPC against short circuit on the line side with a resulting current rising as
fast as 2 A/100 nsec.
The fast current limiting circuit keeps the voltage between S1..4 and VILF below a
programmable voltage level. This results in a current limitation.
Zener diode ZDGS protects the DMOS-gate.
Diodes DPD and DPS are the parasitic drain-bulk-diode and drain-substrate-diode of the
DMOS transistor (junction isolated technology). The diodes do not provide overvoltage
protection, negative surges would pass through to S1..4 and VILF affecting the battery
voltage. Extra overvoltage protection circuitry is necessary to conduct voltage surges
form the line to ground, and to prevent that any current can flow into Diodes DPD and DPS.
Typical value of DMOS-on-resistance including internal wiring-resistance to the pins D1..4
and S1..4 is 1.4 Ω.
To identify overcurrent, the voltage between S1..4 and VILF is compared to 100 mV. If the
voltage exceeds this level, this is indicated to the line current control circuits. A resistor
and the external capacitor CS define a lowpass filter (time delay) to suppress the
changes on NACK due to short overcurrent surges. This enables to filter the effects of
longitudinal AC current.
An external capacitor with a value of about 220 nF results in a delay time (tOC) of about
25 msec.
3.5
Relays Driver Circuit
The output transistor is a bipolar npn. The maximal collector current should not exceed
40 mA. When switching off an inductive load, zener diode and npn clamps the voltage
level on pin RDout1..8 at about 10 V. The 2 kΩ resistor limits the input current on pin
RDin1..8 and additionally the npn collector current.
If a pin RDin1..8 is not connected, the integrated “pull-down current-sink” holds the
respective relay driver in switched-off condition.
Data Sheet
14
2001-10-31
PEF 2426
Application Hints
4
Application Hints
4.1
Resistor RS1..4
The value of this resistor defines the overcurrent indication level. Note, that the value of
this resistor must be considered for line symmetry. The typical overcurrent indication
level Iind can be programmed by using the following formula.
•
100mV
Iind = ------------------RS 1… 4
If for any reason one or more ports of the QIHPC shall remain unused, the respective
resistor RSx has to provided anyway. Pin Dx, however, can be left unconnected.
4.2
Resistor RF
The values of resistors RF and RS1..4 define the current limiting level. The typical
overcurrent limitation level Ilim can be programmed by using the following formula.
•
100mV + R F ⋅ 20µA
I l im = ---------------------------------------------------RS 1… 4
4.3
Capacitor CS1..4
The value of this capacitor define the resulting delay time tOC for the overcurrent
indication. For typical values of tOC as a function of CS1..4 see Figure 6.
Data Sheet
15
2001-10-31
PEF 2426
Application Hints
t OC1..4 [msec]
•
160
140
120
100
80
60
40
20
0
22
33
47
68
100
220
330
470
680
1000
CS1..4 [nF]
Figure 6
Data Sheet
Delay time tOC as a function of the value of CS1..4 (typical values)
16
2001-10-31
PEF 2426
Application Hints
4.4
Protection Circuitry
•
VLIF
1N4007
1N4007
T410
HV
10 Κ
A
D1..D4
12 Ω
AC path
10 nF
470 nF
15 Ω
B
Figure 7
QIHPC
Proposal for a Protection Circuitry
An external circuitry is needed to protect the QIHPC against damages due to high
voltages from the line. High voltages can be caused by lightning surges or foreign
voltage contact.
The protection element in this scheme is a Triac (T410). With positive going surges, the
Triac will fire through a gate current flowing via diode 1N4107 to ground. With negative
going surges, the gate current is supplied by VILF via the second 1N4007 diode.This
circuit is capable to protect the QIHPC against damage with surges up to +/- 3kV (1.2/
50µs and 10/700 µs pulse shape).
Shorting of voltage surges to GND is sensed by the QIHPC in the same way as a shortcircuit at the line. It will react according to the programmed overcurrent indication and
overcurrent limitation.
Data Sheet
17
2001-10-31
PEF 2426
Operational Description
5
Operational Description
The QIHPC is compliant to the ETSI TS 102 080 “Dynamic power feeding requirements”
using the LT power test load (see Figure 8). There is no requirement for the order of
powering up the lines, or for dependencies of controlling between the lines.
•
Channel1
1k
3k
400 µ F
RDin1 . . . RDin8
Channel2
RDout1 . . . RDout8
D1
400 µ F
PF1
PF2
PF3
PF4
D2
D3
Channel3
QIHPC
D4
1k
3k
NACK1
NACK2
NACK3
NACK4
400 µ F
VILF
VILF
Channel4
VDD
VDD
1k
3k
VDD
GND
S1 . . . S4
CS1 . . . CS4
RFpos RFneg
1k
3k
400 µ F
RS1..4
CS1..4
4∗ 2Ω
4 ∗ 220 nF
VILF
Figure 8
RF
1700 Ω
VILF
Circuit with “LT Power Source Test Loads”
With the LT power source test load from TS 102 080 the QIHPC can power up four U
line interfaces within about 2 seconds “quasi simultaneous”. The input sequence and
expected output sequence with power dissipation diagram is shown in Figure 9. The
power dissipation in the chip is quite small.
A fault condition (short circuit) on one line does not affect the power up of the other lines.
Example:
Assumed a short circuit on line 3. A simultaneous power up request is applied to the
QIHPC. The power up of lines 1 and 2 will proceed as expected. When powering up line
3, the chip temperature control (Tj2) will switch off this line. Lines 1 and 2 are still powered
and remain in normal power on condition. When the junction temperature is decreased
to Tj1 the QIHPC will try to power up line 4. If there is no fault condition on line 4 the lines
1, 2 and 4 are finally in a normal power on condition. Line 3 is still in power off. To to
repeat the trial to powering up line 3, the input signal PF3 must set to “0” and “1” again.
Data Sheet
18
2001-10-31
PEF 2426
Operational Description
•
PF1
t
PF2
t
PF3
t
PF4
t
iD1
67 mA
t
NACK1
t
0.5 sec
iD2
67 mA
t
NACK2
t
1.0 sec
iD3
67 mA
t
NACK3
t
1.5 sec
iD4
67 mA
t
NACK4
t
2.0 sec
Power Dissipation on Chip
2W
1W
t
0
Figure 9
Data Sheet
0.5 sec
1.0 sec
1.5 sec
2.0 sec
Simultaneous Power Up Sequence
19
2001-10-31
PEF 2426
Electrical Characteristics
6
Electrical Characteristics
•
6.1
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
− 40 to 85
°C
− 65 to 125
°C
− 0.4 to + 8
V
− 140 to VDD + 0.4
V
− 0.4 to + 150
V
− 3 to + 150
V
− 3 to + 150
VP
Impulse voltages on pins D1..4 with respect to VD1..4impulse
VILF with series resistor RS = 5 Ω /figure 15:
Tdur = 20 µsec / Trise = 25 nsec / non repetitive
− 5 to + 160
VP
VS1..4max
Voltages on pins D 1..4 with respect to voltages VDS1..4max
− 0.4 to + 8
V
− 0.4 to + 140
V
− 0.4 to + 8
V
− 0.4 to VDD + 0.4
V
− 0.4 to VDD + 0.4
V
Voltages on pins Rin1..4 with respect to ground VRi1..4max
− 0.4 to VDD + 0.4
V
Voltages on pins Rout1..4 with respect to
ground
VRo1..4max
− 0.4 to VDD + 0.4
V
ESD-voltage, all pins (Human body model)
VESD-HBM
- 1 to + 1
kV
TA
Storage temperature range
Tstg
VDDmax
Voltage on pin VDD with respect to ground
Voltage on pin VILF with respect to ground
VILFmax
VD1..4max
Voltages on pins D1..4 with respect to VILF
Voltages on pins D 1..4 with respect to VILF with VD1..4maxRs
Operating ambient temperature range:
series resistor RS = 5 Ω /figure 15
Pulse voltages on pins D1..4 with respect to
VILF with series resistor RS = 5 Ω /figure 15:
t = 200 msec / f = 50 Hz or
t = 50 msec / f = 16.7 Hz
VD1..4pulse
Voltages on pins S1..4 with respect to VILF
on pins S1..4
VCS1..4max
Voltages on pins PF1..4 with respect to ground VPF1..4max
VNA1..4max
Voltages on pins NACK1..4 with respect to
Voltages on pins CS1..4 with respect to VILF
ground
Note: Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values
may cause irreversible damage to the integrated circuit.
Data Sheet
20
2001-10-31
PEF 2426
Electrical Characteristics
•
6.2
Operating Range
Parameter
Symbol
VDD supply voltage
VDD
VILF
VILF supply voltage
Limit Values
Unit
+ 3.0 to + 6.0
V
- 130 to - 30
V
Note: In the operating range the functions given in the circuit description are fulfilled.
6.3
Static Thermal Resistance
Parameter
Symbol
Junction to ambient
Rth, jA
Rth, jC
Junction to case
6.4
Limit Values
Unit
< 62.9
K/W
< 14.6
K/W
AC/DC-Characteristics
General Test Conditions (if not indicated otherwise):
RS1..4 =
2Ω
RF = 1700 Ω
± 0.1 %
± 0.1 %
CS1..4 =220 nF ± 1 %(63 V)
Supply voltages for typical characteristics:
VDD =
5V
±1%
VILF =−100 V ± 1 %
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage
Data Sheet
21
2001-10-31
PEF 2426
Electrical Characteristics
•.
Table 5
No.
DC Characteristics
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Condition
max.
Test
Fig.
Supply Currents
1
2
VDD current
VILF current
IDD
IILF
0.7
1.5
mA
0.4
1
mA
10
excluding line
currents
10
Line Currents, Delay Time tOC and DMOS-RON resistance
3
ImaxOC1..4
Overcurrent
Indication Level
45
50
55
mA
PF1..4 = ”1”
11
4
Current Limiting ImaxL1..4
Level
59
67
75.5
mA
PF1..4 = ”1”
11
5
Line Current in
“on”-condition
ImaxON1..4
168
mA
PF1..4 = ”1”
11
6
Line Current in
“off”-condition
ImaxOFF1..4
7
Delay Time tOC
tOC1..4
8
DMOS-RON
resistance
RON1..4
if ImaxL1..4 > ImaxON1..4
0
10
µA
10
25
40
msec PF1..4 = ”1”,
ILine >= 55 mA
11
0.8
1.4
2.0
Ω
12
PF1..4 = ”0”
11
PF1..4 = ”1”,
ILine = 25 mA
PF1..4, Logic Input Levels
9
“1” - Input
Voltage
VHPF1..4
10
“0” - Input
Voltage
VLPF1..4
11
pull down
Input Current
IPF1..4
2
10
20
V
13
0.8
V
13
30
µA
0.8 V < VPF1..4 <
13
VDD
NACK1..4, Logic Output Levels
12
13
“1” - Output
Voltage
VHNACK1..4
“0” - Output
Voltage
VLNACK1..4
Data Sheet
VDD −
V
ISource1..4 = 100 µA 13
V
ISink1..4 = 100 µA
0.4
0.4
22
13
2001-10-31
PEF 2426
Electrical Characteristics
Table 5
No.
DC Characteristics (Continued)
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Fig.
min. typ.
max.
2.0
VDD
V
14
0.4
V
14
20
30
µA
0 < VRDin1..8 < 0.4 V 14
0.25
0.4
V
0.4
0,5
V
0
20
µA
VRDin1..8 = 2,4 V,
IRDout1..8 = 33 mA
VRDin1..8 = 2,4 V,
IRDout1..8 = 40 mA
VRDin1..8 = 0.4 V
RDin1..8, Relay Driver Inputs
14
“ON” - Input
Voltage
Von,RDin1..8
15
“OFF” - Input
Voltage
Voff,RDin1..8
16
pull down
Input Current
Ipd,RDin1..8
RDout1..8, Relay Driver Outputs
17
Saturation
Voltage
Vsat1,RD1..8
18
Saturation
Voltage
Vsat2,RD1..8
19
Current in “off”condition
Ioff,RD1..8
6.5
0.2
14
14
14
Testing the Electrical Parameters
•
VDD
RDin1..8: open
RDout1..8: open
RDin1 . . . RDin8
RDout1 . . . RDout8
IDD
VDD
D1
PF1
PF2
PF3
PF4
D2
D1..4: open
D3
D4
QIHPC
NACK1
NACK2
NACK3
NACK4
VILF
S1 . . . S4
PF1..4: all
combinations
NACK1..4: open
GND
CS1 . . . CS4
RS1..4
RFpos RFneg
CS1..4
4∗ 2Ω
4 ∗ 220 nF
RF
1700 Ω
IILF
VILF
Figure 10
Data Sheet
Supply Currents
23
2001-10-31
PEF 2426
Electrical Characteristics
•
ImaxOC1
Imax1
ImaxOFF1
ILine
GND
ImaxOC2
Imax2
ImaxOFF2
ILine
GND
Channel1
Channel2
OFF ==> ON: ImaxOC1, Imax1
ON: ImaxOFF1
OFF ==> ON: tOC1
RDin1..8: open
RDout1..8: open
RDin1 . . . RDin8
RDout1 . . . RDout8
OFF ==> ON: ImaxOC2, Imax2
ON: ImaxOFF2
OFF ==> ON: tOC2
VDD
D1
ImaxOC3
Imax3
ImaxOFF3
ILine
ImaxOC4
Imax4
ImaxOFF4
ILine
VDD
VDD
GND
Channel3
PF1
PF2
PF3
PF4
D2
OFF ==> ON: ImaxOC3, Imax3
ON: ImaxOFF3
D3
QIHPC
D4
OFF ==> ON: tOC3
NACK1
NACK2
NACK3
NACK4
VILF
Channel4
OFF ==> ON: ImaxOC4, Imax4
ON: ImaxOFF4
VILF
NACK1..4: open
GND
S1 . . . S4
CS1 . . . CS4
RFpos RFneg
OFF ==> ON: tOC4
RS1..4
RF
CS1..4
4∗2Ω
4 ∗ 220 nF
VILF
1700 Ω
VILF
Stop
Start
ILine >= 55 mA
Timer
tOC1..4
Figure 11
Line Currents and Delay Time tOC
•
GND
GND
IDS3 =
25 mA
IDS4 =
25 mA
GND
IDS2 =
25 mA
RDin1..8: open
RDout1..8: open
RDin1 . . . RDin8
RDout1 . . . RDout8
GND
IDS1 =
25 mA
PF1
PF2
PF3
PF4
D2
D3
QIHPC
D4
VDS3
VDS2
VDS1
NACK1
NACK2
NACK3
NACK4
VILF
VILF
S1 . . . S4
CS1 . . . CS4
RFpos RFneg
4 ∗ 220 nF
RON 3 =
Figure 12
Data Sheet
VDS 1
I DS 1
RON 2 =
VDS 3
I DS 3
RON 4 =
VDS 2
I DS 2
NACK1..4: open
GND
CS1..4
RON 1 =
VDD
VDD
D1
VDS4
VDD
RS1..4
RF
1700 Ω
VILF
4∗2Ω
VILF
VDS 4
I DS 4
DMOS-RON resistance
24
2001-10-31
PEF 2426
Electrical Characteristics
•
IPF1
VHPF1
VLPF1
VPF1
RDin1..8: open
RDout1..8: open
RDin1 . . . RDin8
RDout1 . . . RDout8
RLoad1..4
D1
VHPF3
VLPF3
VPF3
VDD
PF1
PF2
PF3
PF4
D2
D3
QIHPC
D4
NACK1
NACK2
NACK3
NACK4
VILF
VILF
VHNACK1
VLNACK1
VDD
ISource1
4∗ 2Ω
4 ∗ 220 nF
VILF
VDD
1700 Ω
VILF
ISink2
VHNACK2
VLNACK2
VHNACK3
VLNACK3
VDD
ISource3
ISink4
VHNACK4
VLNACK4
Figure 13
Data Sheet
ISource2
ISink3
RF
CS1..4
VHPF4
VLPF4
VPF4
ISink1
CS1 . . . CS4 RFpos RFneg
RS1..4
IPF4
VDD
GND
S1 . . . S4
VHPF2
VLPF2
VPF2
IPF3
VDD
4 ∗ 1 kΩ
IPF2
ISource4
PF1..4, Logic Input Levels and NACK1..4, Logic Output Levels
25
2001-10-31
PEF 2426
Electrical Characteristics
•
VDD
Ipd,RDin8
Ioff,RD1
Von,RDin8
Voff,RDin8
VRDin8
VDD
180
IRDout1
Ioff,RD1
Vsat,RD1
Vsat,RD1
VDD
Ioff,RD8
Ipd,RDin2
VDD
180
Von,RDin2
Voff,RDin2
VRDin2
IRDout8
Ioff,RD8
Ipd,RDin1
Vsat,RD8
Von,RDin1
Voff,RDin1
VRDin1
Vsat,RD8
RDin1 . . . RDin8
VDD
RDout1 . . . RDout8
VDD
D1
PF1
PF2
PF3
PF4
D2
D1..4: open
D3
QIHPC
D4
NACK1
NACK2
NACK3
NACK4
VILF
VILF
NACK1..4: open
GND
S1 . . . S4
CS1 . . . CS4
RS1..4
RFpos RF neg
RF
CS1..4
4∗ 2Ω
4 ∗ 220 nF
VILF
Figure 14
PF1..4: open
1700 Ω
VILF
RDin1..8, Relay Driver Inputs and RDout1..8 Relay Driver Outputs
•
RDin1..8: open
RDout1..8: open
RDin1 . . . RDin8
RDout1 . . . RDout8
5Ω
VD1maxRs
VD1pulse
VD1impulse
RS
5Ω
VD2maxRs
VD2pulse
VD2impulse
VILF
VDD
RS
D1
D3
VD3maxRs
VD3pulse
VD3impulse
RS
VILF
5Ω
VD4maxRs
VD4pulse
VD4impulse
RS
VILF
QIHPC
D4
5Ω
Data Sheet
PF1..4: all
combinations
NACK1..4: open
GND
S1 . . . S4
CS1 . . . CS4
RS1..4
RFpos RFneg
CS1..4
4∗ 2Ω
4 ∗ 220 nF
VILF
Figure 15
NACK1
NACK2
NACK3
NACK4
VILF
VILF
VDD
PF1
PF2
PF3
PF4
D2
VILF
VDD
RF
1700 Ω
VILF
Test circuit for maximum DC-voltages, pulse voltages and impulse
voltages on pins D1..4
26
2001-10-31
PEF 2426
Package Outlines
7
Package Outlines
•
P-MQFP-44
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
27
2001-10-31
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Published by Infineon Technologies AG