TL3M Device Triple Level 3 Mapper TXC-03453 PRODUCT INFORMATION DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/ SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte-wide drop and Add buses - Drop bus timing mode (Add bus timing derived from Drop bus) - Add bus timing mode (independent timing for drop/Add buses) • Path overhead byte processing: - Microprocessor access - External interface - B3 generation/detection with test mask - B3 bit/block performance counters - REI bit/block performance counters - C2 mismatch detection - C2 unequipped detection and generation • Alarm indication port - Path REI count and RDI status for APS applications • O-bit channel access via external interface • Digital desynchronizer with internal pointer leak algorithm • Line interface: - NRZ or P/N rail option for transmit and for receive - Monitor NRZ transmit data • Microprocessor access: - Motorola or Intel compatible - Hardware interrupt with mask bits - Software polling bits • Testing: - Facility or line loopback - PRBS generator/analyzer - Boundary scan (IEEE 1149.1 standard) • A fully tested device driver is available • 3.3 volt power supply, 5 volt tolerant inputs • 324-lead plastic ball grid array package (23 mm x 23 mm) SDH/SONET SIDE (TELECOM BUS) O-Bit Interfaces APPLICATIONS • • • • Add/drop multiplexers Digital cross connect systems Broadband switching systems Transmission equipment External Alarm Interfaces Drop Bus Add Bus Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal using a bytewide parallel interface in the TranSwitch Telecom Bus format. The TL3M supports Drop bus and Add bus SDH/SONET timing modes. Drop bus timing provides the timing signals for the add side. Timing for both buses is independent for the Add bus timing mode. Individual POH bytes are mapped into a RAM interface for microprocessor access and to an external interface for external processing if required. In the add direction (except for the B3 byte) POH bytes may be inserted individually from RAM locations, from the external interface, or from the local side/alarm indication port. An option is provided to generate an unequipped channel or AIS. An external interface is provided for accessing the O-bits. An alarm indication port is provided for ring operation. The TL3M also uses internal digital desynchronizers that have a built-in pointer leak algorithm. The line side can be configured for a NRZ or positive/negative rail interface. For testing purposes, the TL3M provides boundary scan, PRBS generators and analyzers, a BIP error mask, and DS3/E3 line and facility loopbacks. The TL3M provides either Motorola or Intel microprocessor access. The interrupt has programmable mask bits. A software polling register is also provided. Control Signals Triple Level 3 Mapper TXC-03453 Alarm Indication Port LINE SIDE Receive Interfaces (3) (Rail, NRZ) TL3M Microprocessor Interface POH Interfaces Transmit Monitor Interfaces (3) Transmit Interfaces (3) (Rail, NRZ) Boundary Scan U.S. Patents No.: 4,967,405; 5,040,170; 5,157,655; 5,265,096 U.S. and/or foreign patents issued or pending Copyright © 2001 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com Document Number: TXC-03453-MC Ed. 4, December 2001 • USA Proprietary TranSwitch Corporation Information for use Solely by its Customers FEATURES TL3M, TXC-03453 APPLICATION DIAGRAM Note: Each bus contains a Drop bus and an Add bus Proprietary TranSwitch Corporation Information for use Solely by its Customers STM-1/STS-3 Serial I/O or Parallel I/O PHAST-3N TL3M TXC-06103 TXC-03453 Three Asynchronous E3 or DS3 Line Signals B Bus Alarm Indication Ports STM-1/STS-3 Serial I/O or Parallel I/O Alarm Indication Ports A Bus PHAST-3N TL3M TXC-06103 TXC-03453 Three Asynchronous E3 or DS3 Line Signals RELATED PRODUCTS • TXC-02030 • TXC-02302B • TXC-03001B • TXC-03003B • TXC-03303 • TXC-03305 • TXC-03452B • TXC-06103 • TXC-06125 Advanced E3/DS3 Receiver/Transmitter VLSI Device (DART) 155-Mbit/s Synchronizer, Clock and Data Output VLSI Device (SYN155C) SONET STM-1 Overhead Terminator VLSI Device (SOT-1) STM-1/STS-3/STS-3c Overhead Terminator VLSI Device (SOT-3) DS3/DS1 Mux/Demux, Extended Features VLSI Device (M13E) DS3/DS1 Mux/Demux VLSI Device (M13X) Level 3 Mapper VLSI Device (L3M) SDH/SONET STM-1, STS-3 or STS-3c Overhead Terminator VLSI Device (PHAST-3N) Bit Error Rate Generator Receiver VLSI Device (XBERT) FURTHER INFORMATION Contact TranSwitch for technical and ordering information on these products. TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product or circuit. TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com Document Number: TXC-03453-MC Ed. 4, December 2001 • USA