SCBS136M − MAY 1992 − REVISED OCTOBER 2003
D
D
D
SN54LVTH273 . . . J PACKAGE
SN74LVTH273 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
D
D
D
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH273 . . . FK PACKAGE
(TOP VIEW)
2D
2Q
3Q
3D
4D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
D Ioff Supports Partial-Power-Down-Mode
8Q
D
(5-V Input and Output Voltages With
3.3-V VCC )
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Support Unregulated Battery Operation
Down To 2.7 V
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
1D
1Q
CLR
VCC
D Support Mixed-Mode Signal Operation
description/ordering information
These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D)
inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the
D-input signal has no effect at the output.
ORDERING INFORMATION
PACKAGE†
TA
SN74LVTH273DW
Tape and reel
SN74LVTH273DWR
SOP − NS
Tape and reel
SN74LVTH273NSR
LVTH273
SSOP − DB
Tape and reel
SN74LVTH273DBR
LXH273
Tube
SN74LVTH273PW
Tape and reel
SN74LVTH273PWR
CDIP − J
Tube
SNJ54LVTH273J
SNJ54LVTH273J
LCCC − FK
Tube
SNJ54LVTH273FK
SNJ54LVTH273FK
TSSOP − PW
−55°C to 125°C
TOP-SIDE
MARKING
Tube
SOIC − DW
−40°C to 85°C
ORDERABLE
PART NUMBER
LVTH273
LXH273
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(& *"!$# #"')"*% "
+&#)#("' +&* & &*% ") &.( '*$%&' ('!(*! /(**('0
*"!$#"' +*"#&'1 !"& '" '&#&(*-0 '#-$!& &'1 ") (-+(*(%&&*
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1
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
description/ordering information (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
CLK
D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
H or L
X
Q0
logic diagram (positive logic)
CLK
1D
2D
3D
4D
3
4
7
8
13
7D
14
8D
17
18
CLK(I)
1D
C1
1
1D
C1
R
2
6D
11
1D
CLR
5D
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
R
2
5
6
1Q
2Q
3Q
POST OFFICE BOX 655303
9
4Q
• DALLAS, TEXAS 75265
12
5Q
15
6Q
16
7Q
19
8Q
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVTH273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH273 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH273 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVTH273
SN74LVTH273
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
−24
−32
mA
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
High-level input voltage
2
2
0.8
V
V
0.8
V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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!&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&*
+&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 "
#('1& "* !#"''$& && +*"!$# /"$ '"#&
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3
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
II = −18 mA
IOH = −100 µA
VCC = 2.7 V,
IOH = −8 mA
IOH = −24 mA
VOL
VCC = 3 V
Data inputs
Ioff
VCC = 3.6 V
VCC = 0,
Data inputs
V
V
2
2
0.2
0.2
IOL = 24 mA
IOL = 16 mA
0.5
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
V
0.55
0.55
10
10
VI = VCC or GND
VI = VCC
±1
±1
1
1
VI = 0
VI or VO = 0 to 4.5 V
−5
VI = 0.8 V
VI = 2 V
VCC = 3 V
II(hold)
−1.2
UNIT
VCC−0.2
2.4
IOL = 64 mA
VI = 5.5 V
VCC = 0 or 3.6 V,
VCC = 3.6 V,
SN74LVTH273
TYP†
MAX
MIN
−1.2
VCC−0.2
2.4
IOH = −32 mA
IOL = 100 µA
VCC = 2.7 V
II
MIN
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
VCC = 3 V
Control inputs
SN54LVTH273
TYP†
MAX
TEST CONDITIONS
−5
±100
75
75
−75
−75
500
−750
VCC = 3.6 V‡,
VI = 0 to 3.6 V
VCC = 3.6 V, IO = 0,
VI = VCC or GND
Outputs high
ICC
∆ICC§
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
Outputs low
A
µA
0.19
0.19
5
5
0.2
0.2
µA
µA
mA
mA
Ci
VI = 3 V or 0
4
4
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH273
VCC = 3.3 V
± 0.3 V
MIN
fclock
tw
Clock frequency
tsu
Setup time
th
Hold time, data high or low after CLK↑
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
Pulse duration
MAX
VCC = 2.7 V
MIN
150
3.3
3.3
3.3
Data high or low before CLK↑
2.3
2.7
2.3
2.7
CLR high before CLK↑
2.3
2.7
2.3
2.7
0
0
0
0
POST OFFICE BOX 655303
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UNIT
MAX
MHz
3.3
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!&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&*
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4
SN74LVTH273
ns
ns
ns
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH273
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
fmax
tPLH
tPHL
tPHL
MAX
SN74LVTH273
VCC = 2.7 V
MIN
MAX
150
CLK
Any Q
CLR
Any Q
† All typical values are at VCC = 3.3 V, TA = 25°C.
VCC = 3.3 V
± 0.3 V
MIN
TYP†
VCC = 2.7 V
MAX
MIN
UNIT
MAX
150
MHz
1.6
5
5.6
1.7
3.2
4.9
5.5
1.8
4.9
5.2
1.9
3.2
4.8
5.1
1.5
4.4
4.8
1.6
2.7
4.3
4.7
ns
ns
')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "*
!&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&*
+&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 "
#('1& "* !#"''$& && +*"!$# /"$ '"#&
POST OFFICE BOX 655303
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5
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
2.7 V
Input
1.5 V
1.5 V
th
2.7 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
1.5 V
VOL
Output
tPLZ
3V
1.5 V
tPZH
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
Output
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVTH273DBLE
OBSOLETE
SSOP
DB
20
SN74LVTH273DBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273DBRE4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273NSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273NSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273PWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
SN74LVTH273PWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273PWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH273PWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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