FINAL Am27C1024 1 Megabit (65,536 x 16-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS ■ ±10% power supply tolerance available ■ Fast access time ■ 100% Flashrite programming — 55 ns maximum access time ■ Low power consumption — Typical programming time of 8 seconds — 100 µA typical CMOS standby current ■ JEDEC-approved pinouts — 40-Pin DIP/PDIP — 44-Pin PLCC ■ Single +5 V power supply ■ Latch-up protected to 100 mA from –1 V to VCC + 1 V ■ High noise immunity ■ Versatile features for simple interfacing — Both CMOS and TTL input/output compatibility — Two line control functions GENERAL DESCRIPTION The Am27C1024 is a 1 Mbit ultraviolet erasable programmable read-only memory. It is organized as 64K words by 16 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic DIP packages as well as plastic one time programmable (OTP) PDIP and PLCC packages. Typically, any byte can be accessed in less than 70 ns, allowing operation with high-performance microprocessors without any WAIT states. The Am27C1024 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity.Typical power consumption is only 125 mW in active mode, and 100 µW in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The Am27C1024 supports AMD’s Flashrite programming algorithm (100 µs pulses) resulting in a typical programming time of 8 seconds. BLOCK DIAGRAM VCC VSS VPP OE CE PGM A0–A15 Address Inputs Data Outputs DQ0–DQ15 Output Enable Chip Enable and Prog Logic Output Buffers Y Decoder Y Gating X Decoder 1,048,576-Bit Cell Matrix 06780I-1 Publication# 06780 Rev: I Issue Date: July 1997 Amendment/+2 PRODUCT SELECTOR GUIDE Family Part No: Am27C1024 Ordering Part No: VCC = 5.0 V ± 5% -55 VCC = 5.0 V ± 10% -255 -55 -70 -90 -120 -150 -200 Max Access Time (ns) 55 70 90 120 150 200 250 CE (E) Access (ns) 55 70 90 120 150 200 250 OE (G) Access (ns) 40 40 40 50 65 75 75 CONNECTION DIAGRAMS Top View A16 37 A15 DQ13 5 36 A14 DQ12 6 35 A13 DQ11 7 34 A12 DQ10 8 33 A11 DQ9 9 32 DQ8 10 31 A9 VSS 11 30 VSS DQ7 12 29 A8 DQ6 13 28 A7 5 4 3 2 1 44 43 42 41 40 7 39 A13 DQ11 8 38 A12 DQ10 A11 DQ12 A10 6 A14 38 4 A15 3 DQ14 PGM (P) NC DQ15 VCC PMG (P) DU VCC 39 CE (E) 40 2 DQ14 1 DQ13 VPP CE (E) VPP PLCC DQ15 DIP 9 37 DQ9 10 36 A10 DQ8 11 35 A9 VSS 12 34 VSS NC 13 33 NC DQ7 14 32 A8 DQ5 14 27 A6 DQ6 15 31 A7 DQ4 15 26 A5 DQ5 16 30 A6 DQ3 16 25 A4 DQ4 17 29 A5 DQ2 17 24 A3 DQ1 18 23 A2 DQ0 19 22 A1 OE (G) 20 21 A0 A4 A3 A2 A1 A0 DU OE (G) DQ0 DQ1 DQ2 DQ3 18 19 20 21 22 23 24 25 26 27 28 06780I-2 06780I-3 Note: 1. JEDEC nomenclature is in parenthesis. PIN DESIGNATIONS A0–A15 = Address Inputs CE (E) = Chip Enable LOGIC SYMBOL 16 DQ0–DQ15 = Data Inputs/Outputs = Output Enable Input PGM (P) = Program Enable Input VCC = VCC Supply Voltage VPP = Program Voltage Input VSS = Ground NC = No Internal Connection DU = No External Connection (Do Not Use) 2 16 A0–A15 OE (G) DQ0–DQ15 CE (E) PMG (P) OE (G)/VPP 06780I-4 Am27C1024 ORDERING INFORMATION UV EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C1024 -55 D C 5 B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In VOLTAGE TOLERANCE 5 = VCC ± 5%, 55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C1024 1 Megabit (65,536 x 16-Bit) CMOS UV EPROM Valid Combinations Valid Combinations AM27C1024-55 VCC = 5.0 V ± 5% Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DC5, DC5B, DI5, DI5B AM27C1024-55 VCC = 5.0 V ± 10% AM27C1024-70 DC, DCB, DI, DIB AM27C1024-90 AM27C1024-120 AM27C1024-150 DC, DCB, DE, DEB, DI, DIB AM27C1024-200 AM27C1024-255 VCC = 5.0 V ± 5% DC, DCB, DI, DIB Am27C1024 3 ORDERING INFORMATION OTP EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C1024 -55 J C 5 OPTIONAL PROCESSING Blank = Standard Processing VOLTAGE TOLERANCE 5 = VCC ± 5%, -55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Square Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C1024 2 Megabit (131,072 x 16-Bit) CMOS OTP EPROM Valid Combinations Valid Combinations AM27C1024-55 VCC = 5.0 V ± 5% PC5, PI5, JC5, JI5 AM27C1024-55 VCC = 5.0 V ± 10% Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM27C1024-70 AM27C1024-90 AM27C1024-120 PC, PI, JC, JI AM27C1024-150 AM27C1024-200 AM27C1024-255 VCC = 5.0 V ± 5% 4 Am27C1024 FUNCTIONAL DESCRIPTION Erasing the Am27C1024 In order to clear all locations of their programmed contents, it is necessary to expose the Am27C1024 to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase an Am27C1024. This dosage can be obtained by exposure to an ultraviolet lamp—wavelength of 2537 (Å)—with intensity of 12,000 µW/cm2 for 15 to 20 minutes. The Am27C1024 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27C1024 and similar devices will erase with light sources having wavelengths shorter than 4000 Å. Although erasure times will be much longer than with UV sources at 2537 Å, exposure to fluorescent light and sunlight will eventually erase the Am27C1024 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27C1024 Upon delivery or after each erasure the Am27C1024 has all 1,048,576 bits in the “ONE” or HIGH state. “ZEROs” are loaded into the Am27C1024 through the procedure of programming. The programming mode is entered when 12.75 V ± 0.25V is applied to the VPP pin and CE and PGM are atVIL. For programming, the data to be programmed is applied 16 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 µs programming pulses and by giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is repeated while sequencing through each address of the Am27C1024. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27C1024 in parallel with different data is also easily accomplished. Except for CE, all like inputs of the parallel Am27C1024 may be common. A TTL low-level program pulse applied to an Am27C1024 CE input with VPP = 12.75 V ± 0.25 V, and PGM Low will program that Am27C1024. A high-level CE input inhibits the other Am27C1024 devices from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE and CE at VIL, PGM at VIH and VPP between 12.75 V ± 0.25 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the Am27C1024. To activate this mode, the programming equipment must force 12.0 V ± 0.5 V open address the A9 of the Am27C1024. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code, and byte 1 (A0 = V IH ), the device code. For the Am27C1024, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27C1024 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC –tOE. Standby Mode The Am27C1024 has a CMOS standby mode which reduces the maximum VCC current to 100 µA. It is placed in CMOS-standby when CE is at V CC ± 0.3 V. The Am27C1024 also has a TTL-standby mode which reduces the maximum VCC current to 1.0 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. Am27C1024 5 Output OR-Tieing System Applications To accommodate multiple memory connections, a two-line control function is provided to allow for: During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 µF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. ■ Low memory power dissipation ■ Assurance that output bus contention will not occur It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular memory device. MODE SELECT TABLE Pins CE OE PGM A0 A9 VPP Outputs VIL VIL X X X X DOUT Output Disable X VIH X X X X Hi-Z Standby (TTL) VIH X X X X X Hi-Z VCC ± 0.3 V X X X X X Hi-Z Program VIL X VIL X X VPP DIN Program Verify VIL VIL VIH X X VPP DOUT Program Inhibit VIH X X X X VPP Hi-Z Manufacturer Code VIL VIL VIH VIL VH X 01H Device Code VIL VIL VIH VIH VH X 8CH Mode Read Standby (CMOS) Autoselect (Note 3) Notes: 1. VH = 12.0 V ± 0.5 V 2. X = Either VIH or VIL 3. A1–A8 = A10–A15 = VIL 4. See DC Programming Characteristics for VPP voltage during programming. 6 Am27C1024 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C All Other Products . . . . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –55°C to +125°C Voltage with Respect to VSS All pins except A9,VPP,VCC . . . .–0.6 V to VCC + 0.6 V Industrial (I) Devices Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C Extended (E) Devices Ambient Temperature (TA). . . . . . . . .–55°C to +125°C Supply Read Voltages A9 and VPP (Note 2). . . . . . . . . . . . . –0.6 V to +13.5 V VCC for Am27C1024-55, 255 . . . . +4.75 V to +5.25 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . –0.6 V to +7.0 V VCC for Am27C1024 (All Others) . +4.50 V to +5.50 V Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, the inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20ns. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. Minimum DC input voltage on A9 pin is –0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. A9 and VCC must not exceed +13.5 V for any period of time. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Am27C1024 7 DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 2, and 4) Parameter Symbol Parameter Description Test Conditions Min 2.4 Max Unit VOH Output HIGH Voltage IOH = –400 mA VOL Output LOW Voltage IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage ILI Input Load Current ILO Output Leakage Current VOUT = 0 V to +VCC ICC1 VCC Active Current (Note 3) CE = VIL, f = 10 MHz IOUT = 0 mA ICC2 VCC TTL Standby Current CE = VIH 1.0 mA ICC3 VCC CMOS Standby Current CE = VCC ± 0.3 V 100 µA IPP1 VPP Current During (Read) CE = OE = VIL, VPP = VCC 100 µA VIN = 0 V to +VCC V 0.45 V 2.0 VCC + 0.5 V –0.5 +0.8 V C/I Devices 1.0 E Devices 5.0 5.0 C/I Devices 50 E Devices 60 µA µA mA Notes: 1. VCC must be applied simultaneously or before VPP , and removed simultaneously or after VPP . 2. Caution: The Am27C1024 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. ICC1 is tested with OE = VIH to simulate open outputs. 40 40 35 35 Supply Current in mA Supply Current in mA 4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. 30 25 20 1 2 3 4 5 6 7 Frequency in MHz 8 9 30 25 20 –75 –50 –25 10 0 25 50 75 100 125 150 Temperature in °C 06780I-5 Figure 1. 8 Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25°C Figure 2. Am27C1024 Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25°C CAPACITANCE Parameter Symbol CIN COUT Test Conditions Parameter Description CDV040 PD 040 PL 044 Typ Max Typ Max Typ Max Unit Input Capacitance VIN = 0 9 12 7 12 8 10 pF Output Capacitance VOUT = 0 12 14 11 14 11 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25°C, f = 1 MHz. AC CHARACTERISTICS Parameter Symbols Am27C1024 JEDEC Standard Description Test Setup -55 -70 -90 -120 -150 -200 -255 Unit tAVQV tACC Address to Output Delay CE, OE = VIL Max 55 70 90 120 150 200 250 ns tELQV tCE Chip Enable to Output Delay OE = VIL Max 55 70 90 120 150 200 250 ns tGLQV tOE Output Enable to Output Delay CE = VIL Max 40 40 45 50 65 75 75 ns tEHQZ tGHQZ tDF (Note 3) Chip Enable to Output High Z or Output Enable to Output High Z to Output Float, whichever occurs first Max 30 30 40 50 50 50 50 ns tAXQX tOH Output Hold Time from Addresses, CE or OE, whichever occurs first Min 0 0 0 0 0 0 0 ns Notes: 1. Caution: Do not remove the Am27C1024 from (or insert it into) a socket or board that has VPP or VCC applied. 2. VCC must be applied simultaneously or before VPP , and removed simultaneously or after VPP . 3. This parameter is sampled and not 100% tested. 4. Switching characteristics are over operating range, unless otherwise specified. 5. Test Conditions for Am27C1024-55: Output Load: 1 TTL gate and CL = 30 pF Input rise and fall times: 20 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Inputs and Outputs: 1.5 V Test Conditions for all others: Output Load: 1 TTL gate and CL = 100 pF Input rise and fall times: 20 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level Inputs and Outputs: 0.8 and 2.0 V Am27C1024 9 SWITCHING TEST CIRCUIT 5.0 V IN3064 or Equivalent Device Under Test CL 2.7 kΩ 6.2 kΩ Diodes = IN3064 or Equivalent Notes: For -55: CL = 30 pF including jig capacitance For all others: CL = 100 pF including jig capacitance 06780I-8 Test Conditions SWITCHING TEST WAVEFORM 3V 2.4 V 2.0 V 2.0 V Test Points 1.5 V Test Points 1.5 V 0.8 V 0V 0.8 V 0.45 V Input Output Input AC Testing for -55 devices: Inputs are driven at 3.0 V for a logic “1” and 0 V for a logic “0”. Input pulse rise and fall times are ≤20 ns. Output AC Testing (except for -55 devices): Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are ≤20 ns. 06780I-9 10 Am27C1024 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010 SWITCHING WAVEFORMS 2.4 Addresses 0.45 2.0 0.8 2.0 0.8 Addresses Valid CE tCE OE tOE Output High Z tACC (Note 1) tOH Valid Output tDF (Note 2) High Z 06780I-10 Notes: 1. OE may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC. 2. DF is specified from OE or CE, whichever occurs first. Am27C1024 11 REVISION SUMMARY FOR AM27C1024 Operating Ranges: Distinctive Characteristics: Changed Supply Read Voltages listings to match those in the Product Selector Guide. The fastest speed grade available is now 55 ns. AC Characteristics: Product Selector Guide: Added column for 55 ns speed grade, rearranged notes, moved text from table title to Note 4, renamed table. Added 55 ns column. Ordering Information, UV EPROM Products: The 55 ns part number is now listed in the example. The nomenclature now has a method of clearly designating the voltage operating range and speed grade. Added 55 ns to the CL note on 30 pF test condition. Switching Test Waveform: Ordering Information, OTP EPROM Products: Changed the part number example from -70 to -55. The nomenclature now has a method of clearly designating the voltage operating range and speed grade. 12 Switching Test Circuit: Added the 3 V test waveform. Am27C1024