HY57V56820H(L)T 4 Banks x 8M x 8Bit Synchronous DRAM DESCRIPTION The HY57V56820HT is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V56820HT is organized as 4banks of 8,388,608x8. HY57V56820HT is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3±0.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 8192 refresh cycles / 64ms • JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch • Programmable Burst Length and Burst Type • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4, 8 or Full page for Sequential Burst • Data mask function by DQM • Internal four banks operation - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HY57V56820HT-6 166MHz HY57V56820HT-K 133MHz HY57V56820HT-H 133MHz HY57V56820HT-8 125MHz HY57V56820HT-P 100MHz HY57V56820HT-S 100MHz HY57V56820HLT-6 166MHz HY57V56820HLT-K 133MHz HY57V56820HLT-H 133MHz HY57V56820HLT-8 125MHz HY57V56820HLT-P 100MHz HY57V56820HLT-S 100MHz Power Organization Interface Package 4Banks x 8Mbits x8 LVTTL 400mil 54pin TSOP II Normal Low power This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3/Nov. 01 HY57V56820H(L)T PIN CONFIGURATION VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 54pin TSOP II 42 400mil x 875mil 41 0.8mm pin pitch 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A12 Address Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details DQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ7 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 1.3/Nov. 01 2 HY57V56820H(L)T FUNCTIONAL BLOCK DIAGRAM 8Mbit x 4banks x 8 I/O Synchronous DRAM Self refresh logic & timer Internal Row counter 8Mx8 Bank3 CLK Row active Row Pre Decoders 8Mx8 Bank2 CS Column Pre Decoders DQM DQ0 I/O Buffer & Logic Column Active Memory Cell Array Sense AMP & I/O Gate WE X decoders refresh 8Mx8 Bank0 X decoders CAS State Machine RAS 8Mx8 Bank1 X decoders X decoders CKE DQ1 DQ6 DQ7 Y decoders Bank Select A0 A1 Column Add Counter Address Registers Address buffers A12 BA0 BA1 Rev. 1.3/Nov. 01 Burst Counter Mode Registers CAS Latency Data Out Control Pipe Line Control 3 HY57V56820H(L)T ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70°C) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1 Input High Voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2 Input Low Voltage VIL VSSQ - 2.0 0 0.8 V 1,3 Note : 1.All voltages are referenced to VSS = 0V 2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration 3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V) Parameter Symbol Value Unit AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voutref 1.4 V CL 50 pF Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Note 1 Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit Rev. 1.3/Nov. 01 4 HY57V56820H(L)T CAPACITANCE (TA=25°C, f=1MHz) -6/K/H Parameter Pin Input capacitance Data input / output capacitance -8/P/S Symbol Unit Min Max Min Max CLK CI1 2.5 3.5 2.5 4.0 pF A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM CI2 2.5 3.8 2.5 5.0 pF DQ0 ~ DQ7 CI/O 4.0 6.5 4.0 6.5 pF OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V) Parameter Symbol Min. Max Unit Note Input Leakage Current ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -4mA Output Low Voltage VOL - 0.4 V IOL = +4mA Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6V Rev. 1.3/Nov. 01 5 HY57V56820H(L)T DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V) Speed Parameter Operating Current Precharge Standby Current in Power Down Mode Symbol -6 -K -H -8 -P -S 130 120 120 120 110 110 IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA IDD2P CKE ≤ VIL(max), tCK = min 2 IDD2PS CKE ≤ VIL(max), tCK = ∞ 2 IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 20 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 15 IDD3P CKE ≤ VIL(max), tCK = min 5 IDD3PS CKE ≤ VIL(max), tCK = ∞ 5 IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 30 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 20 Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Test Condition Active Standby Current in Non Power Down Mode Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active Unit Note mA 1 mA mA mA mA CL=3 150 140 130 130 120 120 CL=2 120 130 120 120 120 110 240 220 220 210 200 200 Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V mA 1 mA 2 3 mA 3 1.5 mA 4 Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V56820HT-6/K/H/8/P/S/10 4.HY57V56820HLT-6/K/H/8/P/S/10 Rev. 1.3/Nov. 01 6 HY57V56820H(L)T AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -6 Parameter CAS Latency = 3 tCK3 Max 6 Min Max 7.5 1000 CAS Latency = 2 -H -8 -P -S Unit Min System clock cycle time -K Symbol Min Max 7.5 1000 Max 8 1000 Max 10 1000 10 Min 10 1000 10 Note Max ns 1000 10 Clock high pulse width tCHW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 Clock low pulse width tCLW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 CAS Latency = 3 tAC3 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 ns CAS Latency = 2 tAC2 - 6 - 6 - 6 - 6 - 6 - 6 ns Data-out hold time tOH 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Data-Input hold time tDH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Address setup time tAS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Address hold time tAH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CKE setup time tCKS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 CKE hold time tCKH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Command setup time tCS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Command hold time tCH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 2 - 2 - 2 - 2 - 2 - 2 - ns CLK to data output in high Z-time 10 Min tCK2 Access time from clock 10 Min 12 ns 2 CAS Latency = 3 tOHZ3 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3 6 3 6 ns CAS Latency = 2 tOHZ2 3 6 3 6 3 6 3 6 3 6 3 6 ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate Rev. 1.3/Nov. 01 7 HY57V56820H(L)T AC CHARACTERISTICS II -6 Parameter -H -8 -P -S Unit Min System clock cycle time -K Symbol CAS Latency = 3 tCK3 Max 6 Min 7.5 1000 CAS Latency = 2 tCK2 Max 10 Min Max 7.5 1000 10 Min Max 8 1000 10 Min Max 10 1000 10 Min 10 1000 10 Note Max ns 1000 12 ns Clock high pulse width tCHW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 Clock low pulse width tCLW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 CAS Latency = 3 tAC3 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 ns CAS Latency = 2 tAC2 - 6 - 6 - 6 - 6 - 6 - 6 ns Access time from clock 2 Data-out hold time tOH 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Data-Input hold time tDH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Address setup time tAS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Address hold time tAH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CKE setup time tCKS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 CKE hold time tCKH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Command setup time tCS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Command hold time tCH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 2 - 2 - 2 - 2 - 2 - 2 - ns CAS Latency = 3 tOHZ3 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3 6 3 6 ns CAS Latency = 2 tOHZ2 3 6 3 6 3 6 3 6 3 6 3 6 ns CLK to data output in high Ztime Note : 1. A new command can be given tRRC after self refresh exit Rev. 1.3/Nov. 01 8 HY57V56820H(L)T IBIS SPECIFICATION IOH Characteristics (Pull-up) Voltage 100MHz (Min) 100MHz (Max) 66MHz (Min) (V) I(mA) I(mA) I(mA) -2.4 3.3 -27.3 0 0.5 1 1.5 2 2.5 3 3.5 0 -100 3.0 0 -74.1 -0.7 2.6 -21.1 -129.2 -7.5 2.4 -34.1 -153.3 -13.3 2.0 -58.7 -197 -27.5 1.8 -67.3 -226.2 -35.5 1.65 -73 -248 -41.1 1.5 -77.9 -269.7 -47.9 1.4 -80.8 -284.3 -52.4 1.0 -88.6 -344.5 -72.5 0 -93 -502.4 -93 -200 I (mA) 3.45 66MHz and 100MHz Pull-up -300 -400 -500 -600 Voltage (V) IOH Min (100MHz) IOH Min (66MHz) IOH Max (66 /100MHz) IOL Characteristics (Pull-down) 66MHz and 100MHz Pull-down Voltage 100MHz (Min) 100MHz (Max) 66MHz (Min) (V) I(mA) I(mA) I(mA) 0 0 0 0 0.4 27.5 70.2 17.7 0.65 41.8 107.5 26.9 0.85 51.6 133.8 33.3 1.0 58.0 151.2 37.6 1.4 70.7 187.7 46.6 1.5 72.9 194.4 48.0 1.65 75.4 202.5 49.5 1.8 77.0 208.6 50.7 Voltage (V) 1.95 77.6 212.0 51.5 IOL Min (100MHz) 3.0 80.3 219.6 54.2 IOL Min (66MHz) 3.45 81.4 222.6 54.9 IOL Max (100MHz) Rev. 1.3/Nov. 01 250 I (mA) 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 9 HY57V56820H(L)T VDD Clamp @ CLK, CKE, CS, DQM & DQ Minimum VDD clamp current (Referenced to VDD) I(mA) 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 20 15 mA VDD (V) 10 5 0 0 -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 Rev. 1.3/Nov. 01 3 I (mA) Minimum VSS clamp current -3 -2.5 -2 -1.5 -1 -0.5 0 0 -10 -20 mA I (mA) 2 V o lta g e VSS Clamp @ CLK, CKE, CS, DQM & DQ VSS (V) 1 -30 -40 -50 -60 Vo ltage I (mA) 10 HY57V56820H(L)T DEVICE OPERATING OPTION TABLE HY57V56820H(L)T-6 CAS Latency tRCD tRAS tRC tRP tAC tOH 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns HY57V56820H(L)T-K CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns CAS Latency tRCD tRAS tRC tRP tAC tOH HY57V56820H(L)T-H HY57V56820H(L)T-8 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns HY57V56820H(L)T-P CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns HY57V56820H(L)T-S CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns Rev. 1.3/Nov. 01 11 HY57V56820H(L)T COMMAND TRUTH TABLE A10/ AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Command Bank Active H X L L H H X H X L H L H X ADDR RA Read L V H Write L H X L H L L X CA Write with Autoprecharge H X L L H L X Burst Stop H DQM H Auto Refresh H H L L L Burst-Read-SingleWRITE H X L L Entry H L L H Exit L H H X L H H L X L V X X V X H X X L H X A9 Pin High (Other Pins OP code) L L H X X X X X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge power down H X Precharge selected Bank Entry V H Precharge All Banks X X Exit Clock Suspend Note V CA Read with Autoprecharge Self Refresh1 BA Entry Exit L H L H X L H X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev. 1.3/Nov. 01 12 HY57V56820H(L)T PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 0.80(0.0315)BSC Rev. 1.3/Nov. 01 0.400(0.016) 0.300(0.012) 1.194(0.0470) 0.991(0.0390) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 13