4-Channel, ±10 V Input Range, High Throughput, 24-Bit ∑-∆ ADC AD7734 FEATURES High resolution ADC 24 bits no missing codes ±0.0025% nonlinearity Optimized for fast channel switching 18-bit p-p resolution (21 bits effective) at 500 Hz 16-bit p-p resolution (19 bits effective) at 2 kHz 14-bit p-p resolution (18 bits effective) at 15 kHz On-chip per channel system calibration 4 single-ended analog inputs Input ranges +5 V, ±5 V, +10 V, ±10 V Overvoltage tolerant Up to ±16.5 V not affecting adjacent channel Up to ±50 V absolute maximum 3-wire serial interface SPI™, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on logic inputs Single-supply operation 5 V analog supply 3 V or 5 V digital supply Package: 28-lead TSSOP FUNCTIONAL BLOCK DIAGRAM REFIN(–) AIN0 REFIN(+) REFERENCE DETECT AIN1 BUFFER MUX 24-BIT Σ−∆ ADC AIN2 AIN3 AD7734 BIASHI BIASLO SCLK CALIBRATION CIRCUITRY SERIAL INTERFACE DOUT DIN CS P0 SYNC/P1 I/O PORT CLOCK GENERATOR AGND AVDD MCLKOUT MCLKIN CONTROL LOGIC RDY RESET DGND DVDD Figure 1. APPLICATIONS PLCs/DCS Multiplexing applications Process control Industrial instrumentation GENERAL DESCRIPTION The differential reference input features “No-Reference” detect capability. The ADC also supports per channel system calibration options. The digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt triggered. The AD7734 is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total conversion time of 500 µs (2 kHz channel switching), making it ideally suitable for high resolution multiplexing applications. The part is specified for operation over the extended industrial temperature range of –40°C to +105°C. The part can be configured via a simple digital interface, which allows users to balance the noise performance against data throughput up to a 15.4 kHz. The AD7732 is similar to AD7734, but its analog front end features two fully differential input channels. The analog front end features four single-ended input channels with unipolar or true bipolar input ranges to ±10 V while operating from a single +5 V analog supply. The part has an overrange and underrange detection capability and accepts an analog input overvoltage to ±16.5 V without degrading the performance of the adjacent channels. The AD7738 analog front end is configurable for four fully differential or eight single-ended input channels, features 0.625 V to 2.5 V bipolar/unipolar input ranges, and accepts a common-mode input voltage from 200 mV to AVDD–300 mV. The AD7738 multiplexer output is pinned out externally, allowing the user to implement programmable gain or signal conditioning before being applied to the ADC. Other parts in the AD7734 family are the AD7732 and the AD7738. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD7734 TABLE OF CONTENTS AD7734—Specifications.................................................................. 3 Mode Register ............................................................................. 20 Timing Specifications....................................................................... 6 Digital Interface Description ........................................................ 22 Absolute Maximum Ratings............................................................ 8 Hardware ..................................................................................... 22 Typical Performance Characteristics ............................................. 9 Reset ............................................................................................. 23 Output Noise and Resolution Specification................................ 10 Access the AD7734 Registers.................................................... 23 Chopping Enabled...................................................................... 10 Single Conversion and Reading Data ...................................... 23 Chopping Disabled..................................................................... 11 Dump Mode................................................................................ 24 Pin Configurations and Functional Descriptions ...................... 12 Continuous Conversion Mode ................................................. 24 Register Description....................................................................... 14 Continuous Read (Continuous Conversion) Mode .............. 25 Register Access............................................................................ 15 Circuit Description......................................................................... 26 Communications Register......................................................... 15 Analog Front End....................................................................... 26 I/O Port Register......................................................................... 16 Analog Input’s Extended Voltage Range ................................. 27 Revision Register ........................................................................ 16 Chopping ..................................................................................... 27 Test Register ................................................................................ 16 Multiplexer, Conversion, and Data Output Timing............... 28 ADC Status Register................................................................... 17 Sigma-Delta ADC....................................................................... 28 Checksum Register..................................................................... 17 Frequency Response .................................................................. 29 ADC Zero-Scale Calibration Register ..................................... 17 Voltage Reference Inputs........................................................... 29 ADC Full-Scale Register............................................................ 17 Reference Detect......................................................................... 29 Channel Data Registers ............................................................. 17 I/O Port........................................................................................ 30 Channel Zero-Scale Calibration Registers .............................. 18 Calibration................................................................................... 30 Channel Full-Scale Calibration Registers................................ 18 ADC Zero-Scale Self-Calibration ............................................ 30 Channel Status Registers ........................................................... 18 Per Channel System Calibration .............................................. 30 Channel Setup Registers ............................................................ 19 Outline Dimensions ....................................................................... 32 Channel Conversion Time Registers ....................................... 19 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7734 AD7734—SPECIFICATIONS Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS0 to BIAS3, BIASHI, REFIN(+) = 2.5 V; BIASLO, REFIN(–) = AGND; AIN Range = ±10 V; fMCLKIN = 6.144 MHz; unless otherwise noted.) Parameter ADC PERFORMANCE CHOPPING ENABLED Conversion Time Rate No Missing Codes1, 2 Output Noise Min 372 24 Table 4 See Table 5 and Table 6 ±0.0010 ±0.0025 ±0.0050 ±4 100 737 24 Unit Test Conditions/Comments 12190 Hz Bits Configure via Conv. Time Register FW ≥ 6 (Conversion Time ≥ 165 µs) ±0.0030 ±0.0045 ±10 ±2.5 ±0.35 ±3.2 ±0.5 ±3 % of FSR % of FSR mV µV/°C % ppm of FS/°C % of FSR ppm of FS/°C % of FSR LSB16 dB fMCLKIN = 2.5 MHz fMCLKIN = 6.144 MHz Before Calibration Hz Bits Configure via Conv. Time Register FW ≥ 8 (Conversion Time ≥ 117 µs) ±10 15437 Before Calibration Before Calibration After Calibration At DC, AIN = 7 V, AVDD = 5 V ± 5% At DC, Maximum ±16.5 V AIN Voltage See Resolution Integral Nonlinearity (INL)2 Offset Error (Unipolar, Bipolar)5 Offset Drift vs. Temperature Gain Error3 Gain Drift vs. Temperature Positive Full-Scale Error3 Positive Full-Scale Drift vs. Temp. Bipolar Negative Full-Scale Error4 Power Supply Sensitivity Channel-to-Channel Isolation ANALOG INPUTS Analog Input Voltage1, 6, 7 ±10 V Range 0 V to +10 V Range ±5 V Range 0 V to +5 V Range BIASLO Voltage BIAS0 to 3, BIASHI Voltage AIN Impedance1, 8 AIN Pin, BIASLO Pin Impedance1, 8 Max See Resolution Integral Nonlinearity (INL) 1, 2 Integral Nonlinearity (INL)2 Offset Error (Unipolar, Bipolar)3 Offset Drift vs. Temperature1 Gain Error3 Gain Drift vs. Temperature1 Positive Full-Scale Error3 Positive Full-Scale Drift vs. Temp.1 Bipolar Negative Full-Scale Error4 Power Supply Sensitivity Channel-to-Channel Isolation ADC PERFORMANCE CHOPPING DISABLED Conversion Time Rate No Missing Codes1, 2 Output Noise Typ 100 87.5 Table 7 See Table 8 and Table 9 ±0.0025 ±15 ±25 ±0.1 ±5.3 ±0.2 ±4 ±0.0050 ±4 100 % of FSR mV µV/°C % ppm of FS/°C % of FSR ppm of FS/°C % of FSR LSB16 dB ±10 0 to +10 ±5 0 to +5 0 2.5 124 108.5 V V V V V V kΩ kΩ Rev. 0 | Page 3 of 32 Before Calibration Before Calibration Before Calibration After Calibration At DC, AIN = 7 V, AVDD = 5 V ± 5% At DC, Maximum ±16.5 V AIN Voltage AD7734 Parameter BIAS0 to 3, BIASHI Pin Impedance1, 8 Input Resistor Matching Input Resistor Temp. Coefficient REFERENCE INPUTS REFIN(+) to REFIN(–) Voltage1, 9 NOREF Trigger Voltage REFIN(+), REFIN(–) Common-Mode Voltage1 Reference Input DC Current10 SYSTEM CALIBRATION1, 11 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span Min 12.5 Typ 15.5 2.475 2.5 0.5 0 –1.05 × FS 0.8 × FS AVDD Current (Normal Mode) DVDD Current (Normal Mode) 13 DVDD Current (Normal Mode) 13 2.525 V V AVDD 400 V µA +1.05 × FS V V V 2.1 × FS ±1 ±10 –40 5 1.4 0.8 0.3 0.95 0.4 0.3 Unit Test Conditions/Comments kΩ % ppm/°C 0.2 –30 LOGIC INPUTS Input Current Input Current CS Input Capacitance VT+1 VT–1 VT+ – VT–1 VT+1 VT– 1 VT+ – VT–1 MCLK IN ONLY Input Current Input Capacitance VINL Input Low Voltage VINH Input High Voltage VINL Input Low Voltage VINH Input High Voltage LOGIC OUTPUTS12 VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage Floating State Leakage Current Floating State Leakage Capacitance P0, P1 INPUTS/OUTPUTS Input Current VINL Input Low Voltage VINH Input High Voltage VOL Output Low Voltage VOH Output High Voltage POWER REQUIREMENTS AVDD–AGND Voltage DVDD–DGND Voltage Max 2 1.4 0.85 2 1.1 0.85 ±10 5 0.8 3.5 0.4 2.5 0.4 4.0 0.4 DVDD – 0.6 ±1 3 µA µA µA pF V V V V V V µA pF V V V V V V V V µA pF NOREF Bit in Channel Status Register CS = DVDD CS = DGND, Internal Pull-Up Resistor DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V ISINK = 800 µA, DVDD = 5 V ISOURCE = 200 µA, DVDD = 5 V ISINK = 100 µA, DVDD = 3 V ISOURCE = 100 µA, DVDD = 3 V Levels Referenced to Analog Supplies ±10 0.8 3.5 0.4 4.0 4.75 4.75 2.70 13.5 2.8 1.0 5.25 5.25 3.60 15.9 3.1 1.5 Rev. 0 | Page 4 of 32 µA V V V V AVDD = 5 V AVDD = 5 V ISINK = 7 mA, See Abs. Max. Ratings ISOURCE = 200 µA, AVDD = 5 V V V V mA mA mA AVDD = 5 V DVDD = 5 V DVDD = 3 V AD7734 Parameter Power Dissipation (Normal Mode) 13 AVDD+DVDD Current (Standby Mode)14 Power Dissipation (Standby Mode) 14 Min Typ 85 100 525 Max 100 1 Unit mW µA µW Test Conditions/Comments Specifications are not production tested but guaranteed by design and/or characterization data at initial product release. See Typical Performance Characteristics. Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5 ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise. 6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details. 7 The adjacent channels are not affected by AIN voltage up to ±16.5 V. 8 Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ = 124 kΩ. 9 For specified performance. Part is functional with lower VREF. 10 Dynamic current charging the sigma-delta modulator input switching capacitor. 11 Outside the specified calibration range, calibration is possible but the performance may degrade. 12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14 External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD. 2 3 Rev. 0 | Page 5 of 32 AD7734 TIMING SPECIFICATIONS Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.)1 Parameter Master Clock Range t1 t2 Min 1 50 500 Read Operation t4 t52 0 Typ Max 6.144 Unit MHz ns ns ns SYNC Pulsewidth RESET Pulsewidth 0 0 60 80 ns ns 0 0 50 50 0 10 60 80 ns ns ns ns ns ns CS Falling Edge to SCLK Falling Edge Setup Time SCLK Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.3 V CS Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.3 V SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge after SCLK Rising Edge Hold Time Bus Relinquish Time after SCLK Rising Edge ns ns ns ns ns ns CS Falling Edge to SCLK Falling Edge Setup Data Valid to SCLK Rising Edge Setup Time Data Valid after SCLK Rising Edge Hold Time SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge after SCLK Rising Edge Hold Time t5A2, 3 t6 t7 t8 t94 Write Operation t11 t12 t13 t14 t15 t16 Test Conditions/Comments 0 30 25 50 50 0 80 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 2 and Figure 3. These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. 3 This specification is relevant only if CS goes low while SCLK is low. 4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 2 Rev. 0 | Page 6 of 32 AD7734 CS t4 t8 t6 SCLK t7 t5 t9 t5A DOUT MSB LSB Figure 2. Read Cycle Timing Diagram CS t11 t16 t14 SCLK t12 DIN t15 t13 MSB LSB Figure 3. Write Cycle Timing Diagram ISINK (800µA AT DVDD = 5V 100µA AT DVDD = 3V) TO OUTPUT PIN 1.6V 50pF ISOURCE (200µA AT DVDD = 5V 100µA AT DVDD = 3V) Figure 4. Load Circuit for Access Time and Bus Relinquish Time Rev. 0 | Page 7 of 32 AD7734 ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25°C, unless otherwise noted. Parameter AVDD to AGND, DVDD to DGND AGND to DGND AVDD to DVDD AIN to AGND BIAS to AGND REFIN+, REFIN– to AGND MUX0, INTBIAS to AGND P0, P1 Voltage to AGND P0, P1 Current (TMAX = 70°C) P0, P1 Current (TMAX = 85°C) P0, P1 Current (TMAX = 105°C) Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package, Power Dissipation Rating –0.3 V to +7 V –0.3 V to +0.3 V –5 V to +5 V –50 V to +50 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V 8 mA 5 mA 2.5 mA –0.3 V to DVDD + 0.3 V –0.3 V to DVDD + 0.3 V –40°C to +105°C –65°C to +150°C 150°C 660 mW 97.9°C/W θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 215°C 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 32 AD7734 TYPICAL PERFORMANCE CHARACTERISTICS 300 25 24 MCLK = 6.144MHz CHOP = 1 250 200 22 INL – ppm NO MISSING CODES 23 21 20 150 100 19 18 50 17 16 1 2 3 4 5 6 7 8 9 0 –20 10 –15 –10 –5 0 5 10 15 20 FILTER WORD AIN DIFFERENTIAL VOLTAGE – V Figure 5. No Missing Codes Performance, Chopping Enabled Figure 8. Typical INL vs. AIN Voltage, AIN Range =±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = O V 300 25 24 MCLK = 6.144MHz CHOP = 0 250 200 22 INL – ppm NO MISSING CODES 23 21 20 150 100 19 18 50 17 16 1 2 3 4 5 6 7 8 9 0 –20 10 –15 –10 –5 0 5 10 15 20 FILTER WORD AIN DIFFERENTIAL VOLTAGE – V Figure 6. No Missing Codes Performance, Chopping Disabled Figure 9. Typical INL vs. AIN Voltage, AIN Range = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = 0 V 20 30 AVDD + DVDD CURRENT – mA 25 INL – ppm 20 15 10 15 10 5 5 0 0 1 2 3 4 5 6 0 7 0 1 2 3 4 5 6 MCLK FREQUENCY – MHz MCLK FREQUENCY – MHz Figure 7. Typical INL vs. MCLK Frequency, AIN = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = 0 V Figure 10. Typical Supply Current vs. MCLK Frequency, Normal Operation, Converting Rev. 0 | Page 9 of 32 7 AD7734 OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7734 can be operated with chopping enabled or disabled, allowing the ADC to be programmed to either optimize the throughput rate and channel switching time or to optimize the offset drift performance. Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times. The AD7734 noise performance depends on the selected chopping mode, the filter word (FW) value, and the selected analog input range. The AD7734 noise will not vary significantly with MCLK frequency. frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. Table 4 shows the typical output rms noise. Table 5 shows the typical effective resolution based on rms noise. Table 6 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The conversion time is selected via the channel conversion time register. Chopping Enabled The first mode, in which the AD7734 is configured with chopping enabled (CHOP = 1), provides very low noise with lower output rates. Table 4 to Table 6 show the –3 dB Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled FW 127 46 22 17 8 6 2 Conversion Time Register FFh AEh 96h 91h 88h 86h 82h Conversion Time (µs) 2686 999 499 395 207 166 82 Output Data Rate (Hz) –3 dB Frequency (Hz) 372 1001 2005 2534 4826 6041 12166 RMS Noise (µV) 200 520 1040 1300 2500 3100 6300 9.6 15.5 22.7 26.1 39.2 46.0 120.0 Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled FW 127 46 22 17 8 6 2 Conversion Time Register Conversion Time (µs) Output Data Rate (Hz) –3 dB Frequency (Hz) ±10 V Input Range/Effective Resolution (Bits) 0 V to +10 V ±5 V 0 V to +5 V FFh AEh 96h 91h 88h 86h 82h 2686 999 499 395 207 166 82 372 1001 2005 2534 4826 6041 12166 200 520 1040 1300 2500 3100 6300 21.0 20.3 19.7 19.5 19.0 18.7 17.3 20.0 19.3 18.7 18.5 18.0 17.7 16.3 20.0 19.3 18.7 18.5 18.0 17.7 16.3 19.0 18.3 17.7 17.5 17.0 16.7 15.3 Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled FW 127 46 22 17 8 6 2 Conversion Time Register Conversion Time (µs) Output Data Rate (Hz) –3 dB Frequency (Hz) FFh AEh 96h 91h 88h 86h 82h 2686 999 499 395 207 166 82 372 1001 2005 2534 4826 6041 12166 200 520 1040 1300 2500 3100 6300 Rev. 0 | Page 10 of 32 Input Range/Peak-to-Peak Resolution (Bits) ±10 V 18.1 17.4 16.9 16.7 16.2 15.8 15.0 0 V to +10 V 17.1 16.4 15.9 15.7 15.2 14.8 13.4 ±5 V 17.1 16.4 15.9 15.7 15.2 14.8 13.4 0 V to +5 V 16.1 15.4 14.9 14.7 14.2 13.8 12.4 AD7734 Chopping Disabled The second mode, in which the AD7734 is configured with chopping disabled (CHOP = 0), provides faster conversion time while still maintaining high resolution. Table 7 to Table 9 show the –3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. Table 7 shows the typical output rms noise. Table 8 shows the typical effective resolution based on the rms noise. Table 9 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The conversion time is selected via the channel conversion time register. Table 7. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Disabled FW 127 92 44 35 16 8 3 Conversion Time Register 7Fh 5Ch 2Ch 23h 10h 08h 03h Conversion Time (µs) 1357 992 492 398 200 117 65 Output Data Rate –3 dB Frequency (Hz) (Hz) 737 1008 2032 2511 4991 8545 15398 RMS Noise (µV) 670 920 1850 2290 2500 7780 14000 13.2 15.5 22.7 26.3 39.0 57.0 132 Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled FW 127 92 44 35 16 8 3 Conversion Time Register Conversion Time (µs) Output Data Rate (Hz) –3 dB Frequency (Hz) 7Fh 5Ch 2Ch 23h 10h 08h 03h 1357 992 492 398 200 117 65 737 1008 2032 2511 4991 8545 15398 670 920 1850 2290 2500 7780 14000 Input Range/Effective Resolution (Bits) ±10 V 20.5 20.3 19.7 19.5 19.0 18.4 17.2 0 V to +10 V 19.5 19.3 18.7 18.5 18.0 17.4 16.2 ±5 V 19.5 19.3 18.7 18.5 18.0 17.4 16.2 0 V to +5 V 18.5 18.3 17.7 17.5 17.0 16.4 15.2 Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled FW 127 92 44 35 16 8 3 Conversion Time Register Conversion Time (µs) Output Data Rate (Hz) –3 dB Frequency (Hz) 7Fh 5Ch 2Ch 23h 10h 08h 03h 1357 992 492 398 200 117 65 737 1008 2032 2511 4991 8545 15398 670 920 1850 2290 2500 7780 14000 Rev. 0 | Page 11 of 32 Input Range/Peak-to-Peak Resolution (Bits) ±10 V 17.6 17.4 16.8 16.6 16.1 15.5 14.3 0 V to +10 V 16.6 16.4 15.8 15.6 15.1 14.5 13.3 ±5 V 16.6 16.4 15.8 15.6 15.1 14.5 13.3 0 V to +5 V 15.6 15.4 14.8 14.6 14.1 13.5 12.3 AD7734 PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS REFIN(–) AIN0 BIAS0 SCLK 1 28 DGND MCLKIN 2 P0 7 BIAS1 25 DOUT RESET 5 AVDD 6 AIN1 26 DIN CS 4 24 RDY AD7734 AIN2 23 AGND BIAS2 22 REFIN(–) TOP VIEW SYNC/P1 8 (Not to Scale) 21 REFIN(+) INTBIAS 9 19 BIASLO BIAS0 11 18 BIAS3 AIN0 12 AIN1 13 BIAS1 14 AIN3 20 BIASHI MUX0 10 REFIN(+) REFERENCE DETECT R=15.5kΩ MUX0 27 DVDD MCLKOUT 3 7R BIAS3 BIASHI 17 AIN3 BIASLO 16 AIN2 INTBIAS BUFFER 7R R 24-BIT Σ-∆ ADC 7R MUX R AD7734 7R DVDD R CS R CALIBRATION CIRCUITRY 7R SERIAL INTERFACE SCLK DIN DOUT AVDD 15 BIAS2 P0 Figure 11. 28-Lead TSSOP SYNC/P1 I/O PORT CLOCK GENERATOR CONTROL LOGIC RESET RDY AGND AVDD MCLKOUT MCLKIN DGND DVDD Figure 12. Block Diagram Table 10. Pin Function Descriptions—28-Lead TSSOP Pin No. 1 Mnemonic SCLK 2 MCLKIN 3 MCLKOUT 4 CS 5 RESET 6 7 AVDD P0 8 SYNC/P1 Description Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input to transfer serial data to or from the AD7734. Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, the MCLKIN pin can be driven with a CMOS compatible clock and MCLKOUT left unconnected. When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce the device power consumption. MCLK OUT is capable of driving one CMOS load. Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7734 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. Schmitt Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. Analog Positive Supply Voltage. 5 V to AGND nominal. Digital Input/Output. The pin direction is determined by the P0 DIR bit; the digital value can be read/written as the P0 bit in the I/O port register. The digital voltage is referenced to analog supplies. When configured as an input, the pin should be tied high or low. SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit; the digital value can be read/written as the P1 bit in the I/O port register. When the SYNC bit in the I/O port register is set to 1, then the SYNC/P1 pin can be used to synchronize the AD7734 modulator and digital filter with other devices in the system. The digital voltage is referenced to analog supplies. When configured as an input, the pin should be tied high or low. Rev. 0 | Page 12 of 32 AD7734 Pin No. 9 Mnemonic INTBIAS 10 MUX0 11, 14, 15, 18 BIAS0–BIAS3 12, 13, 16, 17 19 AIN0–AIN3 BIASLO 20 BIASHI 21 REFIN(+) 22 REFIN(–) 23 24 AGND RDY 25 DOUT 26 DIN 27 28 DVDD DGND Description This pin provides direct access to the analog input’s common node, bypassing the input resistor divider. In normal circuit configuration, this pin is left open circuit. This pin provides direct access to the multiplexer input of Channel 0, bypassing the input resistor divider. The input voltage range is 0 V to +0.625 V, ±0.625 V, 0 V to +1.25 V, or ±1.25 V referenced to the INTBIAS pin. In normal circuit configuration, this pin is left open circuit. These inputs are used to level shift the analog inputs. These signals are used to ensure that the differential signal seen by the internal buffer amplifier is within its commonmode range. The BIAS0 to BIAS3 pins will normally be connected to 2.5 V. Analog Inputs. BIASLO, in association with BIASHI, is used to set the analog input common-mode voltage. Assuming the BIAS0 to BIAS3 and BIASHI pins are connected to 2.5 V, the analog input voltages are referenced to the voltage at BIASLO. In normal circuit configuration, this pin should be connected to 0 V. BIASHI, in association with BIASLO, is used to set the analog input common-mode voltage. In normal circuit configuration, this pin should be connected to 2.5 V. Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 2.5 V reference voltage. Negative Terminal of the Differential Reference Input. REFIN(–) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 0 V reference voltage. Ground Reference Point for Analog Circuitry. Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a falling edge on this output indicates that either any channel or all channels have unread data available, according to the RDYFN bit in the I/O port register. In calibration mode, a falling edge on this output indicates that calibration is complete (see the Digital Interface Description section for more details). Serial data output with serial data being read from the output shift register on the part. This output shift register can contain information from any AD7734 register, depending on the address bits of the communications register. Serial data input (Schmitt triggered) with serial data being written to the input shift register on the part. Data from this input shift register is transferred to any AD7734 register, depending on the address bits of the communications register Digital Supply Voltage, 3 V or 5 V Nominal. Ground Reference Point for Digital Circuitry. Rev. 0 | Page 13 of 32 AD7734 REGISTER DESCRIPTION Table 11. Register Summary Register Addr (hex) 00 Dir Bit 7 Bit 6 W 0 R/W I/O Port 01 R/W P0 P0 Pin Revision 02 R Test 03 R/W ADC Status 04 R Checksum 05 R/W ADC Zero-Scale Calibration 06 R/W ADC Full-Scale 07 R/W Channel Data1 08–0B R Channel Zero-Scale Cal.1 10–13 R/W Channel Full-Scale Cal. 1 18–1B R/W Channel Status1 20–23 R Channel Setup1 28–2B R/W Channel Conversion Time1 30–33 R/W Mode2 38–3B R/W Communications x 1 2 Bit 5 Bit 4 Bit 3 Bit 2 Default Value 6-Bit Register Address Bit 1 P1 P0 DIR P1 DIR RDYFN 0 0 P1 Pin 1 1 0 0 0 Chip Revision Code Chip Generic Code x x x 0 0 1 24-Bit Manufacturing Test Register – 0 – 0 – 0 – RDY3 RDY2 0 0 0 16-Bit Checksum Register RDY1 0 24-Bit ADC Zero-Scale Calibration Register 800000h 24-Bit ADC Full-Scale Register 800000h 16-/24-Bit Data Registers 8000h 24-Bit Channel Zero-Scale Calibration Registers 800000h 24-Bit Channel Full-Scale Calibration Registers 200000h 0 CH1 CH0 0/P0 RDY/P1 NOREF SIGN Channel Number 0 0 0 0 0 0 0 Stat OPT ENABLE 0 RNG1 0 0 0 0 0 0 0 CHOP FW (7-Bit Filter Word) 1 11h MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT 0 0 0 0 0 0 0 Bit 0 SYNC 0 0 RDY0 0 OVR 0 RNG0 0 CLAMP 0 The two LSBs of the register address, i.e., Bit 1 and Bit 0 in the communication register, specify the channel number of the register being accessed. There is only one mode register, although the mode register can be accessed in one of four address locations. The address used to write the mode register specifies the ADC channel on which the mode will be applied. Only address 38h must be used for reading from the mode register. Table 12. Operational Mode Summary Table 13. Input Range Summary MD2 0 0 0 0 1 1 1 1 RNG1 0 0 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Mode Idle Mode Continuous Conversion Mode Single Conversion Mode Power-Down (Standby) Mode ADC Zero-Scale Self-Calibration For Future Use Channel Zero-Scale System Calibration Channel Full-Scale System Calibration Rev. 0 | Page 14 of 32 RNG0 0 1 0 1 Nominal Input Voltage Range ±10 V 0 V to +10 V ±5 V 0 V to +5 V AD7734 Register Access The AD7734 is configurable through a series of registers. Some of them configure and control general AD7734 features, while others are specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the communications register, i.e., any communication to the AD7734 must start with a write to the communications register specifying which register will be subsequently read or written. Communications Register 8 Bits, Write-Only Register, Address 00h All communications to the part must start with a write operation to the communications register. The data written to Bit 6 R/W Bit 5 the communications register determines whether the subsequent operation will be a read or write and to which register this operation will be directed. The digital interface defaults to expect write operation to the communications register after power-on, after reset, or after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset by writing at least 32 serial clock cycles with DIN high and CS low. (Note that all of the parts, including the modulator, filter, interface, and all registers are reset in this case.) Remember to keep DIN low while reading 32 bits or more either in continuous read mode or with the DUMP bit and “24/16” bit in the mode register set. Bit Mnemonic Bit 7 0 Bit 4 Bit 7 6 Mnemonic 0 R/W 5–0 Address Description This bit must be 0 for proper operation. A 0 in this bit indicates that the next operation will be a write to a specified register. A 1 in this bit indicates that the next operation will be a read from a specified register. Address specifying to which register the read or write operation will be directed. For channel specific registers, two LSBs, i.e., Bit 1 and Bit 0, specify the channel number. When the subsequent operation writes to the Mode register, two LSBs specify the channel selected for operation determined by the mode register value (see Table 14). Table 14. Bit 2 0 0 0 0 Bit 1 0 0 1 1 Bit 0 0 1 0 1 Channel 0 1 2 3 Input AIN0 AIN1 AIN2 AIN3 Rev. 0 | Page 15 of 32 Bit 3 Bit 2 6-Bit Register Address Bit 1 Bit 0 AD7734 I/O Port Register 8 Bits, Read/Write Register, Address 01h, Default Value 30h + Digital Input Value × 40h The bits in this register are used to configure and access the digital I/O port on the AD7734. Bit Mnemonic Default Bit 7 P0 P0 Pin Bit 6 P1 P1 Pin Bit 5 P0 DIR 1 Bit 4 P1 DIR 1 Bit 3 RDYFN 0 Bit 2 0 0 Bit 1 0 0 Bit 0 SYNC 0 Bit 7, 6 Mnemonic P0, P1 5, 4 P0 DIR, P1 DIR 3 RDYFN 2, 1 0 0 SYNC Description When the P0 and P1 pins are configured as outputs, the P0 and P1 bits determine the pins’ output level. When the P0 and P1 pins are configured as inputs, the P0 and P1 bits reflect the current input level on the pins. These bits determine whether the P0 and P1 pins are configured as inputs or outputs. When set to 1, the corresponding pin will be an input; when reset to 0, the corresponding pin will be an output. This bit is used to control the function of the RDY pin on the AD7734. When this bit is reset to 0, the RDY pin goes low when any channel has unread data. When this bit is set to 1, the RDY pin will only go low if all enabled channels have unread data. These bits must be 0 for proper operation. This bit enables the SYNC pin function. By default, this bit is 0 and SYNC/P1 can be used as a digital I/O pin. When the SYNC bit is set to 1, the SYNC pin can be used to synchronize the AD7734 modulator and digital filter with other devices in the system. Revision Register 8 Bits, Read-Only Register, Address 02h, Default Value 02h + Chip Revision × 10h Bit Mnemonic Default Bit 7–4 3–0 Bit 7 x Mnemonic Chip Revision Code Chip Generic Code Bit 6 Bit 5 Chip Revision Code x x Bit 4 Bit 3 x 0 Bit 2 Bit 1 Chip Generic Code 0 1 Bit 0 0 Description 4-Bit Factory Chip Revision Code On the AD7734, these bits will read back as 02h. Test Register 24 Bits, Read/Write Register, Address 03h This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register. Rev. 0 | Page 16 of 32 AD7734 ADC Status Register 8 Bits, Read-Only Register, Address 04h, Default Value 00h In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to 0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to the channel data register. Writing to the mode register resets all the bits to 0. In calibration modes, all the register bits are reset to 0 while a calibration is in progress; all the register bits are set to 1 when the calibration is complete. The RDY pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I/O port register. The RDY0 bit corresponds to Channel 0, the RDY1 bit corresponds to Channel 1, and so on. Bit Mnemonic Default Bit 7 – 0 Bit 6 – 0 Bit 5 – 0 Bit 4 – 0 Bit 3 RDY3 0 Bit 2 RDY2 0 Bit 1 RDY1 0 Bit 0 RDY0 0 Checksum Register Channel Data Registers 16 Bits, Read/Write Register, Address 05h 16 Bit/24 Bit, Read-Only Registers, Address 08h–0Bh, Default Width 16 Bits, Default Value 8000h This register is described in the Using the AD7734/AD7734/AD7738 Checksum Register application note (www.analog.com/UploadedFiles/Application_Notes/71751876 AN626_0.pdf). ADC Zero-Scale Calibration Register 24 Bits, Read/Write Register, Address 06h, Default Value 800000h The register holds the ADC zero-scale calibration coefficient. The value in this register is used in conjunction with the value in the ADC full-scale calibration register and the corresponding channel zero-scale and channel full-scale calibration registers to scale digitally all channels’ conversion results. The value in this register is updated automatically following the execution of an ADC zero-scale self-calibration. Writing this register is possible in the idle mode only (see the Calibration section for more details). These registers contain the most up-to-date conversion results corresponding to each analog input channel. The 16-bit or 24bit data width can be configured by setting the 24/16 bit in the mode register. The relevant RDY bit in the channel status register goes high when the result is updated. The RDY bit will return low once the data register reading has begun. The RDY pin can be configured to indicate when any channel has unread data or waits until all enabled channels have unread data. If any channel data register read operation is in progress when a new result is updated, no update of the data register will occur. This avoids having corrupted data. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for more details). ADC Full-Scale Register 24 Bits, Read/Write Register, Address 07h, Default Value 800000h This register holds the ADC full-scale coefficient. The user is advised not to change the default configuration of this register. Rev. 0 | Page 17 of 32 AD7734 Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 10h–13h, Default Value 800000h 24 Bits, Read/Write Registers, Address 18h–1Bh, Default Value 200000h These registers hold the particular channel zero-scale calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding channel fullscale calibration register, the ADC zero-scale calibration register, and the ADC full-scale register to digitally scale the particular channel conversion results. The value in this register is updated automatically following the execution of a channel zero-scale system calibration. These registers hold the particular channel full-scale calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding channel zero-scale calibration register, the ADC zero-scale calibration register, and the ADC full-scale register to digitally scale the particular channel conversion results. The value in this register is updated automatically following the execution of a channel full-scale system calibration. Writing this register is possible in the idle mode only (see the Calibration section for more details). The format of the channel zero-scale calibration register is a sign bit and 22 bits unsigned value. Writing this register is possible in the idle mode only (see the Calibration section for more details). Channel Status Registers 8 Bits, Read-Only Register, Address 20h–23h, Default Value 20h × Channel Number These registers contain individual channel status information and some general AD7734 status information. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for more details). Bit Mnemonic Default Bit 7 0 Bit 6 Bit 5 CH1 CH0 Channel Number Bit 4 0/P0 0 Bit 7–5 Mnemonic CH1–CH0 4 0/P0 3 RDY/P1 2 NOREF 1 0 SIGN OVR Description These bits reflect the channel number. This can be used for current channel identification and easier operation of the dump mode and continuous read mode. When the status option bit of the corresponding channel setup register is reset to 0, this bit is read as a zero. When the status option bit is set to 1, this bit reflects the state of the P0 pin, whether it is configured as an input or an output. When the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the selected channel RDY bit in the ADC status register. When the status option bit is set to 1, this bit reflects the state of the P1 pin, whether it is configured as an input or an output. This bit indicates the reference input status. If the voltage between the REFIN(+) and REFIN(–) pins is less than NOREF, the trigger voltage and a conversion is executed, then the NOREF bit goes to 1. The voltage polarity at the analog input. It will be 0 for a positive voltage and 1 for a negative voltage. This bit reflects either the overrange or the underrange on the analog input. The bit is set to 1 when the analog input voltage goes over or under the nominal voltage range (see the Analog Input’s Extended Voltage Range section). Rev. 0 | Page 18 of 32 Bit 3 RDY/P1 0 Bit 2 NOREF 0 Bit 1 SIGN 0 Bit 0 OVR 0 AD7734 Channel Setup Registers 8 Bits, Read/Write Register, Address 28h–2Bh, Default Value 00h These registers are used to configure the selected channel, to configure its input voltage range, and to set up the corresponding channel status register. Bit Mnemonic Default Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 Stat OPT 0 Bit 3 ENABLE 0 Bit 2 0 0 Bit 1 RNG1 0 Bit 0 RNG0 0 Bit 7–5 4 Mnemonic 0 Stat OPT 3 ENABLE 2 1–0 0 RNG1–RNG0 Description These bits must be 0 for proper operation. Status Option. When this bit is set to 1, the P0 and P1 bits in the channel status register will reflect the state of the P0 and P1 pins. When this bit is reset to 0, the RDY bit in the channel status register will reflect the channel corresponding to the RDY bit in the ADC status register. Channel Enable. Set this bit to 1 to enable the channel in the continuous conversion mode. A single conversion will take place regardless of this bit’s value. This bit must be 0 for proper operation. This is the channel input voltage range (see Table 15). Table 15. RNG1 0 0 1 1 RNG0 0 1 0 1 Nominal Input Voltage Range ±10 V 0 V to +10 V ±5 V 0 V to +5 V Channel Conversion Time Registers 8 Bits, Read/Write Register, Address 30h–33h, Default Value 91h The conversion time registers enable or disable chopping and configure the digital filter for a particular channel. This register value affects the conversion time, frequency response, and noise performance of the ADC. Bit Mnemonic Default Bit 7 CHOP 1 Bit 7 6–0 Description Chopping Enable Bit. Set to 1 to apply chopping mode for a particular channel. CHOP = 1, single conversion or continuous conversion with one channel enabled. Conversion Time (µs) = (FW × 128 + 248)/MCLK Frequency (MHz), the FW range is 2 to 127. Mnemonic CHOP FW Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FW (7-Bit Filter Word) 11h Bit 1 CHOP = 1, continuous conversion with two or more channels enabled. Conversion Time (µs) = (FW × 128 + 249)/MCLK Frequency (MHz), the FW range is 2 to 127. CHOP = 0, single conversion or continuous conversion with one channel enabled. Conversion Time (µs) = (FW × 64 + 206)/MCLK Frequency (MHz), the FW range is 3 to 127. CHOP = 0, continuous conversion with two or more channels enabled. Conversion Time (µs) = (FW × 64 + 207)/MCLK Frequency (MHz), the FW range is 3 to 127. Rev. 0 | Page 19 of 32 Bit 0 AD7734 Mode Register 8 Bits, Read/Write Register, Address 38h–3Bh, Default Value 00h The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets the RDY pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits. The AD7734 contains only one mode register. The two LSBs of the address are used for writing to the mode register to specify the channel selected for the operation determined by the MD2 to MD0 bits. Only the address 38h must be used for reading from the mode register. Bit Mnemonic Default Bit 7 MD2 0 Bit 7–5 Mnemonic MD2–MD0 4 CLKDIS 3 DUMP 2 Cont RD 1 24/16 BIT 0 CLAMP Description Mode Bits. These three bits determine the AD7734 operation mode. Writing a new value to the mode bits will exit the part from the mode in which it has been operating and place it in the newly requested mode immediately. The function of the mode bits is described in more detail below. Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7734 continues to have internal clocks and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7734 clock is stopped and no conversions can take place when the CLKDIS bit is active. The AD7734 digital interface can still be accessed using the SCLK pin. DUMP Mode. When this bit is reset to 0, the channel status register and channel data register will be addressed and read separately. When the DUMP bit is set to 1, the channel status register will be followed immediately by a read of the channel data register regardless of whether the status or data register has been addressed through the communication register. The continuous read mode will always be dump mode reading of the channel status and data register, regardless of the dump bit value (see the Digital Interface Description section for more details). When this bit is set to 1, the AD7734 will operate in the continuous read mode (see the Digital Interface Description section for more details). The Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits wide. When set to 0, the channel data registers will be 16 bits wide. This bit determines the channel data register’s value when the analog input voltage is outside the nominal input voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped either to all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. When the CLAMP bit is reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage range (see the Analog Input’s Extended Voltage Range section). MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Bit 6 MD1 0 Bit 5 MD0 0 Mode Idle Mode Continuous Conversion Mode Single Conversion Mode Power-Down (Standby) Mode ADC Zero-Scale Self-Calibration For Future Use Channel Zero-Scale System Calibration Channel Full-Scale System Calibration Bit 4 CLKDIS 0 Bit 3 DUMP 0 Bit 2 Cont RD 0 Bit 1 24/16 BIT 0 Bit 0 CLAMP 0 Address Used for Mode Register Write Specifies: The First Channel to Start Converting Channel to Convert Channel Conversion Time Used for the ADC Self-Calibration Channel to Calibrate Channel to Calibrate Rev. 0 | Page 20 of 32 AD7734 MD2 MD1 MD0 Operating Mode 0 0 0 Idle Mode The default mode after power-on or reset. The AD7734 automatically returns to this mode after any calibration or after a single conversion. 0 0 1 Continuous Conversion Mode The AD7734 performs a conversion on the specified channel. After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7734 continues converting on the next enabled channel. The part will cycle through all enabled channels until it is put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by the corresponding channel conversion time registers. 0 1 0 Single Conversion Mode The AD7734 performs a conversion on the specified channel. After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. Requesting a single conversion ignores the channel setup register enable bits; a conversion will be performed even if that channel is disabled. 0 1 1 Power-Down (Standby) Mode The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7734 digital interface can still be accessed. The CLKDIS bit works separately, and the MCLKOUT mode is not affected by the power-down (standby) mode. 1 0 0 ADC Zero-Scale Self-Calibration Mode A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is complete, the contents of the ADC zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. 1 0 1 For Future Use. 1 1 0 Channel Zero-Scale System Calibration Mode A zero-scale system calibration is performed on the selected channel. An external system zero-scale voltage should be provided at the AD7734 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding channel zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. 1 1 1 Channel Full-Scale System Calibration Mode A full-scale system calibration is performed on the selected channel. An external system full-scale voltage should be provided at the AD7734 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding channel full-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. Rev. 0 | Page 21 of 32 AD7734 DIGITAL INTERFACE DESCRIPTION The RESET pin can be used to reset the AD7734. When not used, connect this pin to DVDD. Hardware The AD7734 serial interface can be connected to the host device via the serial interface in several different ways. The CS pin can be used to select the AD7734 as one of several circuits connected to the host serial interface. When CS is high, the AD7734 ignores the SCLK and DIN signals and the DOUT pin goes to the high impedance state. When the CS signal is not used, connect the CS pin to DGND. The RDY pin can be polled for high-to-low transition or can drive the host device interrupt input to indicate that the AD7734 has finished the selected operation and/or new data from the AD7734 is available. The host system can also wait a designated time after a given command is written to the device before reading. Alternatively, the AD7734 status can be polled. When the RDY pin is not used in the system, it should be left as an open circuit. (Note that the RDY pin is always an active digital output, i.e., it never goes into a high impedance state.) The AD7734 interface can be reduced to just two wires connecting the DIN and DOUT pins to a single bidirectional data line. The second signal in this 2-wire configuration is the SCLK signal. The host system should change the data line direction with reference to the AD7734 timing specification (see the Bus Relinquish Time in Table 2). The AD7734 cannot operate in the continuous read mode in 2-wire serial interface configuration. All the digital interface inputs are Schmitt-Triggered; therefore, the AD7734 interface features higher noise immunity and can be easily isolated from the host system via optocouplers. Figure 13, Figure 14, and Figure 15 outline some of the possible host device interfaces: SPI without using the CS signal (Figure 13), a DSP interface (Figure 14), and a 2-wire configuration (Figure 15). DVDD DVDD AD7734 DVDD AD7734 68HC11 SS RESET 8xC51 RESET SCLK SCK SCLK P3.1/TXD DOUT MISO DOUT P3.0/RXD DIN MOSI DIN INT RDY CS CS DGND DGND Figure 13. AD7734 to Host Device Interface, SPI Figure 15. AD7734 to Host Device Interface, 2-Wire Configuration DVDD AD7734 ADSP-2105 RESET SCLK SCLK DOUT DR DIN DT RDY INT CS TFS RFS Figure 14. AD7734 to Host Device Interface, DSP Rev. 0 | Page 22 of 32 AD7734 Reset CS The AD7734 can be reset by the RESET pin or by writing a reset sequence to the AD7734 serial interface. SCLK DIN The reset sequence is N × 0 + 32 × 1, which could be the data sequence 00h + FFh + FFh + FFh + FFh in a byte-oriented interface. The AD7734 also features a power-on reset with a trip point of 2 V and goes to the defined default state after power-on. It is the system designer’s responsibility to prevent an unwanted write operation to the AD7734. The unwanted write operation could happen when a spurious clock appears on the SCLK while the CS pin is low. It should be noted that on system power-on, if the AD7734 interface signals are floating or undefined, the part can be inadvertently configured into an unknown state. This could be easily overcome by initiating either a hardware reset event or a 32 ones reset sequence as the first step in the system configuration. Access the AD7734 Registers All communications to the part start with a write operation to the communications register followed by either reading or writing the addressed register. In a simultaneous read-write interface (such as SPI), write 0 to the AD7734 while reading data. DOUT WRITE COMMUNICATIONS REGISTER Figure 16. Serial Interface Signals—Registers Access Single Conversion and Reading Data When the mode register is being written, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous state. When the single conversion command is written to the mode register, the ADC starts the conversion on the channel selected by the address of the mode register. After the conversion is completed, the data register is updated, the mode register is changed to idle mode, the relevant RDY bit is set, and the RDY pin goes low. The RDY bit is reset and the RDY pin returns high when the relevant channel data register is being read. Figure 17 shows the digital interface signals executing a single conversion on Channel 0, waiting for the RDY pin to go low, and reading the Channel 0 data register. Figure 16 shows the AD7734 interface read sequence for the ADC status register. CS SCLK DIN 38h 40h 48h DOUT (00h) (00h) DATA DATA RDY WRITE COMMUNICATIONS REGISTER WRITE MODE REGISTER CONVERSION TIME READ ADC STATUS REGISTER WRITE COMMUNICATIONS REGISTER READ DATA REGISTER Figure 17. Serial Interface Signals—Single Conversion Command and 16-Bits Data Reading Rev. 0 | Page 23 of 32 AD7734 Dump Mode When the DUMP bit in the mode register is set to 1, the channel status register will be read immediately by a read of the channel data register, regardless of whether the status or the data register has been addressed through the communications register. The DIN pin should not be high while reading 24-bit data in dump mode; otherwise, the AD7734 will be reset. Figure 18 shows the digital interface signals executing a single conversion on Channel 0, waiting for the RDY pin to go low, and reading the Channel 0 status register and data register in the dump mode. Continuous Conversion Mode When the mode register is being written, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous state. When the continuous conversion command is written to the mode register, the ADC starts conversion on the channel selected by the address of the mode register. After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7734 continues converting on the next enabled channel. The part will cycle through all enabled channels until put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by the corresponding channel conversion time registers. The RDY bit is reset when the relevant channel data register is being read. The behavior of the RDY pin depends on the RDYFN bit in the I/O port register. When the RDYFN bit is 0, the RDY pin goes low when any channel has unread data. When the RDYFN bit is set to 1, the RDY pin will only go low if all enabled channels have unread data. If an ADC conversion result has not been read before a new ADC conversion is completed, the new result will overwrite the previous one. The relevant RDY bit goes low and the RDY pin goes high for at least 163 MCLK cycles (~26.5 µs), indicating when the data register is updated, and the previous conversion data is lost. If the data register is being read as an ADC conversion completes, the data register will not be updated with the new result (to avoid data corruption) and the new conversion data is lost. Figure 19 shows the digital interface signal’s sequence for the continuous conversion mode with Channels 0 and 1 enabled and the RDYFN bit set to 0. The RDY pin goes low and the data register is read after each conversion. Figure 20 shows a similar sequence but with the RDYFN bit set to 1. The RDY pin goes low and all data registers are read after all conversions are completed. Figure 21 shows the RDY pin when no data are read from the AD7734. CS SCLK DIN 38h 48h 48h DOUT (00h) (00h) (00h) STATUS DATA DATA RDY WRITE COMMUNICATIONS REGISTER WRITE MODE REGISTER CONVERSION TIME WRITE COMMUNICATIONS REGISTER READ CHANNEL STATUS READ DATA REGISTER Figure 18. Serial Interface Signals—Single Conversion Command, 16-Bits Data Reading, Dump Mode START CONTINUOUS CONVERSION READ DATA CH0 READ DATA CH1 READ DATA CH0 READ DATA CH1 CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION SERIAL INTERFACE RDY CH0 CONVERSION Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0 Rev. 0 | Page 24 of 32 AD7734 START CONTINUOUS CONVERSION READ READ DATA DATA CH1 CH0 READ READ DATA DATA CH1 CH0 SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 20. Continuous Conversion, CH0 and CH1, RDYFN = 1 START CONTINUOUS CONVERSION SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 21. Continuous Conversion, CH0 and CH1, No Data Read CS SCLK DIN 38h 48h 48h DOUT 00h 00h 00h 00h 00h 00h STATUS DATA DATA STATUS DATA DATA RDY WRITE COMM. REGISTER WRITE MODE REGISTER WRITE COMM. REGISTER CONVERSION ON CH0 COMPLETE READ CH0 STATUS READ CH0 DATA CONVERSION ON CH1 COMPLETE READ CH1 STATUS READ CH1 DATA Figure 22. Continuous Conversion, CH0 and CH1, Continuous Read Continuous Read (Continuous Conversion) Mode When the Cont RD bit in the mode register is set, the first write of 48h to the communications register starts the continuous read mode. As shown in Figure 22, subsequent accesses to the part sequentially read the channel status and data registers of the last completed conversion without any further configuration of the communications register being required. Note that the continuous conversion bit in the mode register should be set when entering the continuous read mode. Note that the continuous read mode is a dump mode reading of the channel status and data registers regardless of the dump bit value. Use the channel bits in the channel status register to check/recognize which channel data is actually being shifted out. Note that the last completed conversion result is being read. Therefore the RDYFN bit in the I/O port register should be 0, and reading the result should always start before the next conversion is completed. The AD7734 will stay in continuous read mode as long as the DIN pin is low while the CS pin is low; therefore, write 0 to the AD7734 while reading in continuous read mode. To exit continuous read mode, take the DIN pin high for at least 100 ns after a read is complete. (Write 80h to the AD7734 to exit continuous reading.) Taking the DIN pin high does not change the Cont RD bit in the mode register. Therefore, the next write of 48h starts the continuous read mode again. To completely stop the continuous read mode, write to the mode register to clear the Cont RD bit. Rev. 0 | Page 25 of 32 AD7734 CIRCUIT DESCRIPTION The AD7734 is a sigma-delta ADC that is intended for the measurement of wide dynamic range, low frequency signals in industrial process control, instrumentation, and PLC systems. It contains thin film resistor dividers, a multiplexer, an input buffer, a sigma-delta (or charge balancing) ADC, a digital filter, a clock oscillator, a digital I/O port, and a serial communications interface. Analog Front End The AD7734 features four single-ended analog inputs. The onchip thin film resistor dividers allow ±10 V, ±5 V, 0 V to +10 V, and 0 V to +5 V input signals to be connected directly to the analog input pins. The resistor divider input stage is followed by the multiplexer and then by a wide bandwidth, fast settling time differential input buffer capable of driving the dynamic load of a high speed sigma-delta modulator. If the BIAS pins are in normal configuration, the AIN pin absolute voltage up to ±16.5 V does not degrade the adjacent channel’s performance. An AIN absolute voltage over ±16.5 V results in current flowing through the internal protection diodes located behind the thin film resistors and the adjacent channel can be affected. The AIN pins are “overvoltage tolerant.” However, the absolute maximum AIN voltage of ±50 V must never be exceeded. Note that the OVR bit in the channel status register is generated digitally from the conversion result and indicates the sigmadelta modulator (nominal) overrange. The OVR bit DOES NOT indicate exceeding the AIN pin absolute voltage limits. Figure 23 shows the AD7734 analog input internal structure. PROTECTION DIODES AIN ±10V In normal circuit configuration, the BIAS0 to BIAS3 and BIASHI pins are connected to the 2.5 V (reference) voltage source and the BIASLO pin is connected to 0 V. This ensures that the differential signal seen by the internal input buffer is within its absolute/common-mode range of AGND + 200 mV to AVDD – 300 mV. AVDD 7R 108.5kΩ BUFFER MUX BIAS 2.5V 1R 15.5kΩ 2.1875V ± 1.25V AGND The AD7734 AIN voltage should be within the specified nominal (up to ±10 V) input range, otherwise the performance on channel might degrade (see the Analog Input’s Extended Voltage Range section). Rev. 0 | Page 26 of 32 Figure 23. Simplified Analog Input Internal Structure AD7734 Analog Input’s Extended Voltage Range The AD7734 output data code span corresponds to the nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. The sigma-delta modulator was designed to fully cover a ±11.6 V analog input voltage; outside this range, the performance might degrade more rapidly. The adjacent channels are not affected by up to ±16.5 V analog input voltage (Figure 8). When the CLAMP bit in the mode register is set to 1, the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. As shown in Table 16 and Table 17, when CLAMP = 0, the data reflects the analog input voltage outside the nominal voltage range. In this case, the SIGN and OVR bits in the channel status register should be considered along with the data register value to decode the actual conversion result. Note that the OVR bit in the channel status register is generated digitally from the conversion result and indicates the sigmadelta modulator (nominal) overrange. The OVR bit DOES NOT indicate exceeding the AIN pin’s absolute voltage limits Table 16. Extended Input Voltage Range, Nominal Voltage Range ±10 V, 16 Bits, CLAMP = 0 Input (V) 11.60039 10.00061 10.00031 10.00000 0.00031 0.00000 –0.00031 –10.00000 –10.00031 –10.00061 –11.60040 Data (hex) 147B 0001 0000 FFFF 8001 8000 7FFF 0000 FFFF FFFE EB85 SIGN 0 0 0 0 0 0 1 1 1 1 1 Table 17. Extended Input Voltage Range, Nominal Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0 Input (V) 11.60006 10.00031 10.00015 10.00000 0.00015 0.00000 –0.00015 Data (hex) 28F5 0001 0000 FFFF 0001 0000 0000 SIGN 0 0 0 0 0 0 1 OVR 1 1 1 0 0 0 1 Chopping With chopping enabled, the multiplexer repeatedly reverses the ADC inputs. Every output data result is then calculated as an average of two conversions, the first with the positive and the second with the negative offset term included. This effectively removes any offset error of the input buffer and sigma-delta modulator. However, chopping is applied only behind the input resistor divider stage; therefore, chopping does not eliminate the offset error and drifts caused by the resistors. Figure 24 shows the channel signal chain with chopping enabled. OVR 1 1 1 0 0 0 0 0 1 1 1 AIN BI AS MULTIPLEXER BUFFER Σ−∆ MODULATOR + SCALING ARITHMETIC - (CALIBRATIONS) DIGITAL FILTER BI ASHI BIASLO CHOP f MCLK/2 f MCLK/2 CHOP Figure 24. Channel Signal Chain Diagram with Chopping Enabled Rev. 0 | Page 27 of 32 DIGITAL INTERFACE OUTPUT DATA AT THE SELECTED DATA RATE AD7734 Multiplexer, Conversion, and Data Output Timing The specified conversion time includes one or two settling and sampling periods and a scaling time. The RDY pin goes high during the scaling time, regardless of its previous state. The relevant RDY bit is set in the ADC status register and in the channel status register, and the RDY pin goes low when the channel data register is updated and the channel conversion cycle is finished. If in continuous conversion mode, the part will automatically continue with a conversion cycle on the next enabled channel. With chopping enabled (Figure 25), a conversion cycle starts with a settling time of 43 MCLK cycles or 44 MCLK cycles (~7 µs with a 6.144 MHz MCLK) to allow the circuits following the multiplexer to settle. The sigma-delta modulator then samples the analog signals and the digital filter processes the digital data stream. The sampling time depends on FW, i.e., on the channel conversion time register contents. After another settling of 42 MCLK cycles (~6.8 µs), the sampling time is repeated with a reversed (chopped) analog input signal. Then, during the scaling time of 163 MCLK cycles (~26.5 µs), the two results from the digital filter are averaged, scaled using the calibration registers, and written into the channel data register. Note that every channel can be configured independently for conversion time and chopping mode. The overall cycle and effective per channel data rates depend on all enabled channel settings. Sigma-Delta ADC The AD7734 core consists of a charge balancing sigma-delta modulator and a digital filter. The architecture is optimized for fast, fully settled conversion. This allows for fast channel-tochannel switching while maintaining inherently excellent linearity, high resolution, and low noise. With chopping disabled (Figure 26), there is only one sampling time preceded by a settling time of 43 MCLK cycles or 44 MCLK cycles and followed by a scaling time of 163 MCLK cycles. MULTIPLEXER – CHANNEL 0 + CHANNEL 1 – CHANNEL 1 RDY SETTLING TIME SAMPLING TIME SETTLING TIME SAMPLING TIME SCALING TIME CONVERSION TIME Figure 25. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled MULTIPLEXER CHANNEL 0 CHANNEL 1 RDY SETTLING TIME SAMPLING TIME SCALING TIME CONVERSION TIME Figure 26. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled Rev. 0 | Page 28 of 32 AD7734 Frequency Response Voltage Reference Inputs The sigma-delta modulator runs at ½ the MCLK frequency, which is effectively the sampling frequency. Therefore, the Nyquist frequency is ¼ the MCLK frequency. The digital filter, in association with the modulator, features the frequency response of a first order low-pass filter. The –3 dB point is close to the frequency of 1/channel conversion time. The roll-off is –20 dB/dec up to the Nyquist frequency. If chopping is enabled, the input signal is resampled by chopping. Therefore, the overall frequency response features notches close to the frequency of 1/channel conversion time. The top envelope is again the ADC response of –20 dB/dec. The typical frequency response plots are given in Figure 27 and Figure 28. The plots are normalized to 1/channel conversion time. 0 CHOP = 1 –20 GAIN – dB The output noise performance outlined in Table 4 through Table 9 is for an analog input of 0 V and is unaffected by noise on the reference. To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7734. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7734. Recommended reference voltage sources for the AD7734 include the AD780, ADR421, REF43, and REF192. Note that in a typical connection, the voltage reference must be capable of sinking current flowing out of the BIAS pins through the internal resistors if a positive voltage is applied to the analog input. The AD780 meets this requirement. If the voltage reference used in an application is not capable of sinking current, an external resistor (5 kΩ) should be connected in parallel to the REFIN pins. –10 –30 –40 –50 –60 0.1 The AD7734 has a differential reference input, REF IN(+) and REF IN(–). The common-mode range for these inputs is from AGND to AVDD. The nominal differential reference voltage for specified operation is 2.5 V. Both reference inputs feature dynamic load. Therefore, the reference inputs should be connected to a low impedance reference voltage source. External resistance/capacitance combinations may result in gain errors on the part. 1.0 10.0 NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY × CONVERSION TIME) Figure 27. Typical ADC Frequency Response, Chopping Enabled 0 Reference Detect The AD7734 includes on-chip circuitry to detect if the part has a valid reference for conversions. If the voltage between the REFIN(+) and REFIN(–) pins goes below the NOREF trigger voltage (0.5 V typ.) and the AD7734 is performing a conversion, the NOREF bit in the channel status register is set. –10 CHOP = 1 GAIN – dB –20 –30 –40 –50 –60 0.1 1.0 10.0 NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY × CONVERSION TIME) Figure 28. Typical ADC Frequency Response, Chopping Disabled Rev. 0 | Page 29 of 32 AD7734 I/O Port The AD7734 P0 pin can be used as a general-purpose digital I/O pin. The P1 pin (SYNC/P1) can be used as a generalpurpose digital I/O pin or to synchronize the AD7734 with other devices in the system. When the SYNC bit in the I/O port register is set and the SYNC pin is low, the AD7734 does not process any conversion. If it is put into single conversion mode, continuous conversion mode, or any calibration mode, the AD7734 waits until the SYNC pin goes high and then starts operation. This allows conversion to start from a known point in time, i.e., the rising edge of the SYNC pin. The digital P0 and P1 voltage is referenced to the analog supplies. When configured as inputs, the pins should be tied high or low. Calibration The AD7734 provides zero-scale self-calibration, and zero- and full-scale system calibration capability that can effectively reduce the offset error and gain error to the order of the noise. After each conversion, the ADC conversion result is scaled using the ADC calibration registers and the relevant channel calibration registers before being written to the data register. For unipolar ranges: duration is the same as the conversion time configured on the selected channel. A longer conversion time gives less noise and yields a more exact calibration; therefore, use at least the default conversion time to initiate any calibration. ADC Zero-Scale Self-Calibration The ADC zero-scale self-calibration can reduce the offset error in the chopping disabled mode. If repeated after a temperature change, it can also reduce the offset drift error in the chopping disabled mode. The zero-scale self-calibration is performed on internally shorted ADC inputs. The negative analog input terminal on the selected channel is used to set the ADC zero-scale calibration common mode. Therefore, either the negative terminal of the selected differential pair or the AINCOM on the single-ended channel configuration should be driven to a proper commonmode voltage. It is strongly recommended that the ADC zero-scale calibration register should only be updated as part of a zero-scale selfcalibration. Per Channel System Calibration If the per channel system calibrations are used, these should be initiated in the following order: a channel zero-scale system calibration, followed by a channel full-scale system calibration. Data = ((ADC result – ADC ZS Cal. reg.) × ADC FS Reg./200000h – Ch. ZS Cal. reg.) × Ch. FS Cal. reg./200000h For bipolar ranges: Data = ((ADC result – ADC ZS Cal. reg.) × ADC FS Reg./400000h + 800000h – Ch. ZS Cal. reg.) × Ch. FS Cal. reg./200000h The system calibration is affected by the ADC zero-scale and full-scale calibration registers. Therefore, if both self-calibration and system calibration are used in the system, an ADC full-scale self-calibration should be performed first, followed by a system calibration cycle. While executing a system calibration, the fully settled system zero-scale voltage signal or system full-scale voltage signal must be connected to the selected channel analog inputs. Where the ADC result is in the range of 0 to FFFFFFh. Note that the channel zero-scale calibration register has the format of a sign bit and a 22-bit channel offset value. It is strongly recommended that the user not change the ADC full-scale register. To start any calibration, write the relevant mode bits to the AD7734 mode register. After the calibration is complete, the contents of the corresponding calibration registers are updated, all RDY bits in the ADC status register are set, the SYNC pin goes low, and the AD7734 reverts to idle mode. The calibration The per channel calibration registers can be read, stored, or modified and written back to the AD7734. Note that when writing the calibration registers the AD7734 must be in idle mode. Note that outside the specified calibration range, calibration is possible but the performance may degrade (see the System Calibration section in Table 1). Rev. 0 | Page 30 of 32 AD7734 DVDD AVDD + 10µF ANALOG INPUTS 0.1µF AVDD AIN0(+) 4 TO 20mA 7R MCLKIN BIAS0(+) R=15.5kΩ 500R 0V TO 10V –10V TO +10V 0V TO 5V AIN1 7R BIAS1 R AIN2 7R BIAS2 R AIN3 7R BIAS3 R CLOCK GENERATOR +VIN + 10µF VOUT +2.5V AD780 0.01µF 10µF 33pF DVDD BUFFER RESET BIASHI R BIASLO 7R AD7734 REFIN(+) SERIAL INTERFACE AND CONTROL LOGIC REFIN(–) + MCLKOUT 24-BIT Σ-∆ ADC MUX SCLK DIN DOUT RDY CS AGND DGND Figure 29. Typical Connections for the AD7734 Application Rev. 0 | Page 31 of 32 10µF 6.144MHz 33pF AVDD TEMP + 0.1µF DVDD HOST SYSTEM AD7734 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 1 6.40 BS C 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.10 0.30 COPLANARITY 0.19 0.10 SEATING PLANE 0.20 0.09 88 08 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 30. 28-Lead This Shrink Small Outline Package [TSSOP] (RU-28)—Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table 18. Ordering Guide AD7734 Products AD7734BRU Temperature Package –40°C to +105°C Package Description TSSOP-28 © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. C03071-0-2/03(0) Rev. 0 | Page 32 of 32 Package Outline RU-28