ETC UCC3809N-1

application
INFO
available
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
Economy Primary Side Controller
FEATURES
DESCRIPTION
• User Programmable Soft Start With
Active Low Shutdown
The UCC3809 family of BCDMOS economy low power integrated circuits
contains all the control and drive circuitry required for off-line and isolated
DC-to-DC fixed frequency current mode switching power supplies with
minimal external parts count. Internally implemented circuits include
undervoltage lockout featuring startup current less than 100µA, a user accessible voltage reference, logic to ensure latched operation, a PWM comparator, and a totem pole output stage to sink or source peak current. The
output stage, suitable for driving N-Channel MOSFETs, is low in the off
state.
• User Programmable Maximum Duty
Cycle
• Accessible 5V Reference
• Undervoltage Lockout
• Operation to 1MHz
• 0.4A Source/0.8A Sink FET Driver
Oscillator frequency and maximum duty cycle are programmed with two
resistors and a capacitor. The UCC3809 family also features full cycle soft
start.
• Low 100µA Startup Current
The family has UVLO thresholds and hysteresis levels for off-line and
DC-to-DC systems as shown in the table to the left.
PART
TURN ON
TURN OFF
NUMBER THRESHOLD THRESHOLD
UCCX809-1
10V
8V
UCCX809-2
15V
8V
The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP
(N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and
MSOP packages make the device ideal for applications where board
space and height are at a premium.
TYPICAL APPLICATION DIAGRAM
RSTART
VIN
FB
1V
1
1V
NOISE
FILTER
REF
5V
REF
+5V
FEEDBACK
8
CREF
6µA
SS
2
CURRENT
SENSE
SLOPE
COMP
0.5V
7
15/8V
10/8V
DISABLE
UVLO
RT1
OSC
RT2
17.5V
CVDD
PWM
LATCH
3
CLK
OUT
R
Q
6
S
4
CT
VOUT
VDD
CSS
GND
5
VREF
UDG-99036
SLUS166A - NOVEMBER 1999
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS*
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V
IVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
IOUT (tpw < 1µs and Duty Cycle < 10%) . . . . . . . . –0.4A to 0.8A
RT1, RT2, SS . . . . . . . . . . . . . . . . . . . . . . –0.3V to REF + 0.3V
IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15mA
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
SOIC-8, DIL-8 (Top View)
D, N and J Packages
* Values beyond which damage may occur.
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
TSSOP-8 (Top View)
PW Package
MSOP-8 (Top View)
P Package
1
FB
REF
8
1
FB
REF
8
2
SS
VDD
7
2
SS
VDD
7
3
RT1
OUT
6
3
RT1
OUT
6
4
RT2
GND
5
4
RT2
GND
5
ORDERING INFORMATION
UCC1809-X
UCC2809-X
UCC3809-X
Temperature Range Available Packages
–55°C to +125°C
J
–40°C to +85°C
N, D, P, PW
0°C to +70°C
N, D, P, PW
UCC
809
–
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 12V. TA = TJ.
PARAMETER
Supply Section
VDD Clamp
IVDD
IVDD Starting
Undervoltage Lockout Section
Start Threshold (UCCx809-1)
UVLO Hysteresis (UCCx809-1)
Start Threshold (UCCx809-2)
UVLO Hysteresis (UCCx809-2)
Voltage Reference Section
Output Voltage
Line Regulation
Load Regulation
Comparator Section
IFB
Comparator Threshold
OUT Propagation Delay (No Load)
TEST CONDITIONS
IVDD = 10mA
No Load
MIN
TYP
MAX
UNIT
16
17.5
600
19
900
100
V
µA
µA
10.4
V
V
V
V
9.4
1.65
14.0
6.2
IREF = 0mA
VDD = 10V to 15V
IREF = 0mA to 5mA
4.75
Output Off
0.9
VFB = 0.8V to 1.2V at TR = 10ns
2
15.6
5
2
2
–100
0.95
50
5.25
1
100
V
mV
mV
nA
V
ns
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 12V. TA = TJ.
PARAMETER
Soft Start Section
ISS
VSS Low
Shutdown Threshold
Oscillator Section
Frequency
Frequency Change with Voltage
CT Peak Voltage
CT Valley Voltage
CT Peak to Peak Voltage
Output Section
Output VSAT Low
Output VSAT High
Output Low Voltage During UVLO
Minimum Duty Cycle
Maximum Duty Cycle
Rise Time
Fall Time
TEST CONDITIONS
VDD = 16V, VSS = 0V; –40°C to +85°C
VDD = 16V, VSS = 0V; < –40°C; >+85°C
VDD = 7.5V, ISS = 200µA
RT1 = 10k, RT2 = 4.32k, CT = 820pF
VDD = 10V to 15V
MIN
TYP
MAX
UNIT
–4.9
–4.0
–7.0
–7.0
0.44
0.48
–9.1
–10.0
0.2
0.52
µA
µA
V
V
90
100
0.1
3.33
1.67
1.67
110
kHz
%/V
V
V
V
1.54
IOUT = 80mA (dc)
IOUT = –40mA (dc), VDD – OUT
IOUT = 20mA (dc)
VFB = 2V
COUT = 1nF
COUT = 1nF
0.8
0.8
0
70
35
18
1.80
1.5
1.5
1.5
V
V
V
%
%
ns
ns
PIN DESCRIPTIONS
FB: This pin is the summing node for current sense
feedback, voltage sense feedback (by optocoupler) and
slope compensation. Slope compensation is derived
from the rising voltage at the timing capacitor and can be
buffered with an external small signal NPN transistor.
External high frequency filter capacitance applied from
this node to GND is discharged by an internal 250Ω on
resistance NMOS FET during PWM off time and offers
effective leading edge blanking set by the RC time
constant of the feedback resistance from current sense
resistor to FB input and the high frequency filter
capacitor capacitance at this node to GND.
RT2: This pin connects to timing resistor RT2 and
controls the negative ramp time of the internal oscillator
(Tf = 0.74 • (CT + 27pF) • RT2). The negative threshold
of the internal oscillator is sensed through inactive timing
resistor RT1 which connects to pin RT1 and timing
capacitor CT.
SS: This pin serves two functions. The soft start timing
capacitor connects to SS and is charged by an internal
6µA current source. Under normal soft start SS is
discharged to at least 0.4V and then ramps positive to
1V during which time the output driver is held low. As SS
charges from 1V to 2V soft start is implemented by an
increasing output duty cycle. If SS is taken below 0.5V,
the output driver is inhibited and held low. The user
accessible 5V voltage reference also goes low and IVDD
< 100µA.
GND: Reference ground and power ground for all
functions.
OUT: This pin is the high current power driver output. A
minimum series gate resistor of 3.9 is recommended to
limit the gate drive current when operating with high bias
voltages.
VDD: The power input connection for this device. This
pin is shunt regulated at 17.5V which is sufficiently below
the voltage rating of the DMOS output driver stage. VDD
should be bypassed with a 1µF ceramic capacitor.
REF: The internal 5V reference output. This reference is
buffered and is available on the REF pin. REF should be
bypassed with a 0.47µF ceramic capacitor.
RT1: This pin connects to timing resistor RT1 and
controls the positive ramp time of the internal oscillator
(Tr = 0.74 • (CT + 27pF) • RT1). The positive threshold
of the internal oscillator is sensed through inactive timing
resistor RT2 which connects to pin RT2 and timing
capacitor CT.
3
C1
150µF
–VIN
ON/OFF
+VIN
PGND1
R2
1.1K
R1
5.1k
C2
150µF
Q1
2N2222A
C4
0.01µF
C5
1nF
R3
12.1K
TP1
PGND1
C3
1µF
R4
6.19K
R5
470
6
5
OUT
GND
RT1
RT2
3
4
R18
3.01K
Q4
2N2222A
C22
0.1µF
R20
5.62K
7
VDD
SS
2
U1
8
REF
UCC3809
FB
1
C6
330pF
C8
1µF
D1
5231B
C9
0.1µF
C7
0.47µF
R12
27K
D4
1N5240
R9
2K
3W
R6
1K
R10
10
D2
1N5245
R11
680
Q2
2N2907A
R13
1.1K
2
4
R7
15K
C15
0.015µF
D3
SF24
R8
0.15
3W
Q3
IRF640
5:1
R19
5.1K
3W
C10
0.22µF
T1
80µH
U3
1
5
H11AV1
1
2
3
R15
10K
C14
470pF
C16
330µF
6.3V
C13
0.1µF
U2
MBR2535CTL
U4
TL431
R14
750
C17
330µF
6.3V
R16
12.1K
1%
R17
12.1K
1%
C18
330µF
6.3V
–VOUT
C19
330µF
6.3V
+VOUT
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION
UDG-99179
Figure 1. Isolated 50W flyback converter utilizing the UCC3809. The switching frequency is 70kHz, Vin = -32V
to -72V, Vout = +5V, Iout = 0A to 10A
4
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION (cont.)
The Typical Application Diagram shows an isolated
flyback converter utilizing the UCC3809. Note that the
capacitors CREF and CVDD are local decoupling capacitors for the reference and IC input voltage, respectively.
Both capacitors should be low ESR and ESL ceramic,
placed as close to the IC pins as possible, and returned
directly to the ground pin of the chip for best stability.
REF provides the internal bias to many of the IC functions and CREF should be at least 0.47µF to prevent REF
from drooping.
5.0V reference) sensed through RT1. The R input to the
oscillator latch, R(OSC), is also level sensitive and resets
the CLK signal low when CT crosses the 1.67V threshold, turning off Q2 and turning on Q1, initiating another
charging cycle.
Figure 3 shows the waveforms associated with the oscillator latch and the PWM latch (shown in the Typical Application Diagram). A high CLK signal not only initiates a
discharge cycle for CT, it also turns on the internal
NMOS FET on the FB pin causing any external capacitance used for leading edge blanking connected to this
pin to be discharged to ground. By discharging any external capacitor completely to ground during the external
switch’s off-time, the noise immunity of the converter is
enhanced allowing the user to design in smaller RC components for leading edge blanking. A high CLK signal
also sets the level sensitive S input of the PWM latch,
S(PWM), high, resulting in a high output, Q(PWM), as
shown in Figure 3. This Q(PWM) signal will remain high
until a reset signal, R(PWM) is received. A high R(PWM)
signal results from the FB signal crossing the 1V threshold, or during soft start or if the SS pin is disabled.
FB Pin
The basic premise of the UCC3809 is that the voltage
sense feedback signal originates from an optocoupler
that is modulated by an external error amplifier located
on the secondary side. This signal is summed with the
current sense signal and any slope compensation at the
FB pin and compared to a 1V threshold, as shown in the
Typical Application Diagram. Crossing this 1V threshold
resets the PWM latch and modulates the output driver
on-time much like the current sense comparator used in
the UC3842. In the absence of a FB signal, the output
will follow the programmed maximum on-time of the oscillator.
Assuming the UVLO threshold is satisfied, the OUT signal of the IC will be high as long as Q(PWM) is high and
S(PWM), also referred to as CLK, is low. The OUT signal will be dominated by the FB signal as long as the FB
signal trips the 1V threshold while CLK is low. If the FB
signal does not cross the 1V threshold while CLK is low,
the OUT signal will be dominated by the maximum duty
cycle programmed by the user. Figure 3 illustrates the
various waveforms for a design set up for a maximum
duty cycle of 70%.
When adding slope compensation, it is important to use
a small capacitor to AC couple the oscillator waveform
before summing this signal into the FB pin. By correctly
selecting the emitter resistor of the optocoupler, the voltage sense signal can force the FB node to exceed the
1V threshold when the output that is being compared exceeds a desired level. Doing so drives the UCC3809 to
zero percent duty cycle.
Oscillator
The following equation sets the oscillator frequency:
−1
FOSC = [0.74 • (CT + 27 pF ) • (RT 1 + RT 2)]
VREF
D MAX = 0.74 • RT 1 • (CT + 27 pF ) • FOSC
Q1
Referring to Figure 2 and the waveforms in Figure 3,
when Q1is on, CT charges via the RDS(on) of Q1 and
RT1. During this charging process, the voltage of CT is
sensed through RT2. The S input of the oscillator latch,
S(OSC), is level sensitive, so crossing the upper threshold (set at 2/3 VREF or 3.33V for a typical 5.0V reference) sets the Q output (CLK signal) of the oscillator
latch high. A high CLK signal results in turning off Q1
and turning on Q2. CT now discharges through RT2 and
the RDS(on) of Q2. CT discharges from 3.33V to the
lower threshold (set at 1/3 VREF or 1.67V for a typical
3
S
3.33V
Q
CLK
RT1
4
R
1.67V
RT2
CT
OSCILLATOR
LATCH
Q2
OSC
UDG-97195
Figure 2. UCC3809 oscillator.
5
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION (cont.)
CT CT
CHARGING DISCHARGING
3.33V
1.67V
CT
S(OSC)
R(OSC)
Q(OSC)=CLK
=S(PWM)
1V
FB
R(PWM)
Q(PWM)
70%
ON
30%
OFF
OUT
FB SIGNAL DOMINANT
MAX. DUTY CYCLE DOMINANT
UDG-99037
Figure 3. Waveforms associated with the oscillator latch and the PWM latch.
The recommended value for CT is 1nF for frequencies in
the 100 kHz or less range and smaller CT for higher frequencies. The minimum recommended values of RT1
and RT2 are 10kΩ and 4.32kΩ, respectively. Using these
values maintains a ratio of at least 20:1 between the
RDS(on) of the internal FETs and the external timing resistors, resulting in minimal change in frequency over
temperature. Because of the oscillator's susceptibility to
capacitive coupling, examine the oscillator frequency by
looking at the common RT1-RT2-CT node on the circuit
board as opposed to looking at pins 3 and 4 directly. For
good noise immunity, RT1 and RT2 should be placed as
close to pins 3 and 4 of the IC as possible. CT should be
returned directly to the ground pin of the IC with minimal
stray inductance and capacitance.
Figure 4. Oscillator frequency vs. CT (RT1 = 10k,
RT2 = 4.32k)
6
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION (cont.)
Synchronization
changed.
Both of the synchronization schemes shown in Figure 5
can be successfully implemented with the internal oscillator of the UCC3809. Both schemes allow access to the
timing ramp needed for slope compensation and have
minimal impact on the programmed maximum duty cycle.
In the absence of a sync pulse, the PWM controller will
run independently at the frequency set by RT1, RT2, and
CT. This free running frequency must be approximately
15 to 20% lower than the sync pulse frequency to insure
the free running oscillator does not cross the comparator
threshold before the desired sync pulse.
Option II uses the synchronization pulse to superimpose
the sync voltage onto the peak of the CT waveform. This
triggers the internal 3.33V comparator, initiating a discharge cycle. The sync pulse is summed with the free
running oscillator waveform at the CT node, resulting in a
spike on top of the CT peak voltage.
ADDITIONAL INFORMATION
Please refer to the following Unitrode application topics
for additional information.
[1] Application Note U-165, Design Review: Isolated 50W
Flyback Converter with the UCC3809 Primary Side Controller by Lisa Dinwoodie.
Option I uses the synchronization pulse to pull pin 3 low,
triggering the internal 1.67V comparator to reset the RS
latch and initiate a charging cycle. The valley voltage of
the CT waveform is higher when synchronized using this
configuration, decreasing the ramp charge and discharge
times, thereby increasing the operating frequency; otherwise the overall shape of the CT voltage waveform is un-
[2] Design Note DN-89, Comparing the UC3842,
UCC3802, and UCC3809 Primary Side PWM Controllers
by Lisa Dinwoodie.
1k
3
SYNC
PULSE
2N2222A
+5V
3
UCC3809
OSCILLATOR
RT1
UCC3809
OSCILLATOR
4
SYNC
PULSE
RT2
2N2222A
RT1
4
RT2
424
CT
0.1µF
424
OPTION I
CT
24
OPTION II
UDG-99006
Figure 5. UCC3809 synchronization options.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
7
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated