To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3874 group is the 8-bit microcomputer based on the 740 family core technology. The 3874 group includes data link layer communication control circuit, A-D converters, D-A converter, automatic data transfer serial I/O, UART, and watchdog timer etc. The various microcomputers in the 3874 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3874 group, refer to the section on group expansion. FEATURES ●Basic machine-language instructions ...................................... 71 ●Minimum instruction execution time ................................. 0.32 µs (at 6.4 MHz oscillation frequency, in double-speed mode) ●Memory size ROM ............................................................... 16 K to 60 K bytes RAM ............................................................... 1024 to 2048 bytes ●Programmable input/output ports ............................................ 72 ●Input port .................................................................................... 1 ●Interrupts ................................................. 27 sources, 16 vectors (Interrupt source discrimination register exists, included key input interrupt) ●Timer 1, timer 2, timer 3 ................................................. 8-bit ✕ 3 ●Timer X, timer Y............................................................ 16-bit ✕ 2 ●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized) ●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized) ●Serial I/O3 ...................................................................... 8-bit ✕ 1 (Clock-synchronized automatic data transfer/arbitrary bit transfer function available) ●A-D converter ................................................. 8-bit ✕ 8 channels ●D-A converter ................................................... 8-bit ✕ 1 channel ●Data link layer communication control circuit ............................ 1 ●Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) ●Watchdog timer ............................................................ 20-bit ✕ 1 ●Power source voltage ................................................ 3.0 to 5.5 V ●Power dissipation In double-speed mode ...................................................... 90 mW In high-speed mode .......................................................... 60 mW (at 32 kHz oscillation frequency, at 5 V power source voltage) In low-speed mode .......................................................... 180 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) ●Operating temperature range .................................... –40 to 85°C (Extended operating temperature version and automotive version) APPLICATION Automotive comfort control for audio system, air conditioning etc., automotive body electronics control, household appliances, and other consumer applications, etc. MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION 43 42 41 44 46 45 47 50 49 48 51 53 52 55 54 56 58 57 60 59 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 PIN CONFIGURATION (TOP VIEW) P31 P30 61 40 62 39 P87/SSTB3 P86/SBUSY3 P85/SRDY3 P84/SCLK3 P83/SIN3 P82/SOUT3 P81 P80/DA VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 63 38 64 37 65 36 66 35 67 68 34 33 69 32 31 70 M38747MCT-XXXGP 71 30 72 29 73 28 74 27 75 26 76 25 77 24 78 23 79 80 22 20 19 17 18 15 16 13 14 12 11 9 10 7 8 5 6 3 4 1 P60/AN0 P77/ADT P76/BUSIN P75/BUSOUT P74 P73 P72/SCLK2 P71/SOUT2 P70/SIN2 P57/RTP1 P56/RTP0 P55/CNTR1 P54/CNTR0 P53/INT5 P52/INT4 P51/INT3 P50/TOUT P47/SRDY1 P46/SCLK1 P45/TXD 2 21 Package type : 80P6S-A Fig. 1 M38747MCT-XXXGP pin configuration 2 P16 P17 P20/KW0 P21/KW1 P22/KW2 P23/KW3 P24/KW4 P25/KW5 P26/KW6 P27/KW7 VSS XOUT XIN P40/XCOUT P41/XCIN RESET P97/INT0 P42/INT1 P43/INT2 P44/RXD MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 41 43 42 45 44 47 46 49 48 51 50 53 52 55 54 56 58 57 60 59 62 61 64 63 P30 P31 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 PIN CONFIGURATION (TOP VIEW) 24 P20/KW0 P21/KW1 P44/RxD P43/INT2 P46/SCLK1 P45/TxD P72/SCLK2 P71/SOUT2 P70/SIN2 P57/RTP1 P56/RTP0 P55/CNTR1 P54/CNTR0 P53/INT5 P52/INT4 P51/INT3 P50/TOUT P47/SRDY1 P76/BUSIN P75/BUSOUT P74 P73 P62/AN2 P61/AN1 P60/AN0 P77/ADT 22 P42/INT1 23 25 20 80 21 26 P63/AN3 18 27 79 19 28 78 16 29 77 17 30 76 14 31 75 15 32 74 12 33 73 13 34 72 11 35 71 9 36 70 10 69 P22/KW2 P23/KW3 P24/KW4 P25/KW5 P26/KW6 P27/KW7 VSS XOUT XIN P40/XCOUT P41/XCIN RESET P97/INT0 7 37 8 38 68 5 67 6 P85/SRDY3 P84/SCLK3 P83/SIN3 P82/SOUT3 P81 P80/DA VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 3 39 4 40 66 1 65 2 P87/SSTB3 P86/SBUSY3 Package type : 80D0 Fig. 2 M38749EFFS pin configuration 3 4 Fig. 3 Functional block diagram 29 Main-clock output X OUT I/O port P9 24 INT0 P9(1) Reset P8(8) I/O port P8 2 3 5 6 I/O port P7 4 P7(8) ADT 7 8 9 72 73 A-D converter (8) VREF AVSS Serial I/O3 automatic transfer controller Serial I/O2(8) Local data bus Serial I/O3 automatic transfer RAM 63 64 65 66 67 68 69 70 D-A converter (8) X COUT φ X CIN Sub-clock Sub-clock input output Clock generating circuit 28 Main-clock input X IN I/O port P6 74 75 76 77 78 79 80 1 P6(8) Reset 71 Data bus 30 VSS (0V) I/O port P5 10 11 12 13 14 15 16 17 P5(8) INT5,INT4, INT3 I/O port P2 31 32 33 34 35 36 37 38 I/O port P3 55 56 57 58 59 60 61 62 I/O port P4 18 19 20 21 22 23 26 27 RAM I/O port P1 39 40 41 42 43 44 45 46 P1(8) P0(8) I/O port P0 47 48 49 50 51 52 53 54 Timer 3(8) Timer 2(8) Timer Y(16) Timer X(16) Timer 1(8) ROM Key-on wake-up P2(8) RTP1,RTP0 CNTR1,CNTR0 TOUT PS PC L S Y X A P3(8) XCOUT X CIN INT2,INT1 PC H C P U P4(8) Serial I/O1(8) Data link layer communication control circuit (5V) VCC BUSIN,BUSOUT Watchdog timer 25 Reset input RESET FUNCTIONAL BLOCK DIAGRAM (Package : 80P6S-A) MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL BLOCK MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1 Pin description (1) Pin Name Functions Function except a port function VCC, VSS Power source input VREF Reference voltage input AVSS Analog power source input RESET Reset input XIN Clock input XOUT Clock output •Connect to VSS. •Reset input pin for active “L.” •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. P00–P07 P10–P17 P20–P27 P30–P37 I/O port P0 I/O port P1 I/O port P2 I/O port P3 •Feedback resistor is built in between XIN pin and XOUT pin. •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. P4 0/XCOUT, P41/X CIN P42/INT1 , I/O port P4 P43/INT2 P44 /RXD, P45/T XD, P46 /SCLK1 , P47/S RDY1 P50/T OUT P51/INT3 – P53/INT5 P54 /CNTR0, I/O port P5 P55 /CNTR1 P56 /RTP0, P57 /RTP1 •Apply voltage of 3.0 V – 5.5 V to Vcc, and 0 V to Vss. •Reference voltage input pin for A-D and D-A conver ters. •Analog power source input pin for A-D and D-A converters. •8-bit I/O port with the same function as port P0. •CMOS compatible input level. •CMOS 3-state output structure. •Sub-clock generating circuit I/O pins connect a resonator. (This circuit cannot be operated by an external clock.) •Interrupt input pins •Serial I/O1 function pins •8-bit I/O port with the same function as port P0. •CMOS compatible input level. •CMOS 3-state output structure. •Timer 2 output pin •Interrupt input pins •Timer X, timer Y function pins •Real time port function pins 5 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 2 Pin description (2) Pin P60/AN 0– P67/AN 7 Name I/O port P6 P70/S IN2, P71/S OUT2, P72/S CLK2 P73, P7 4 P75/BUSOUT , P76/BUSIN P77 /ADT P80/DA P81 P82/S OUT3, P83/S IN3, P84 /SCLK3 , P85/S RDY3 P86 /SBUSY3, P87/S STB3 P97/INT0 6 Functions Function except a port function •8-bit I/O port with the same function as port P0. •A-D converter input pins •CMOS compatible input level. •CMOS 3-state output structure. •8-bit I/O port with the same function as port P0. •Serial I/O2 function pins •CMOS compatible input level. •CMOS 3-state output structure. I/O port P7 •8-bit I/O port with the same function as port P0. •Data link layer communication control pins •A-D trigger input pin •D-A converter output pin •Serial I/O3 function pins I/O port P8 Input port P9 •1-bit input port. •CMOS compatible input level. •Interrupt input pin MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M3874 7 M C T- XXX GP Package type GP : 80P6S-A FS : 80D0 ROM number Omitted in some types. D– : Extended operating temperature version F– : Extended operating speed version of “D–” T– : Automotive version ROM/PROM size 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C: 49152 bytes D: 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 4 Part numbering 7 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER • EPROM or One time PROM version • Mask ROM version Main clock input oscillation frequency f(X IN) (MHz) Main clock input oscillation frequency f(X IN) (MHz) 3874 group main clock input oscillation frequency in double-speed mode 6.4 MHz 5 MHz 4.0 V 4.5 V 5.5 V Power source voltage V CC (V) 6.4 MHz 4.0 V Power source voltage V CC (V) In low-speed mode, middle-speed mode, and high-speed mode, characteristic of main clock input oscillation frequency guarantee limit is not different. Fig. 5 Main clock input oscillation frequency in double-speed mode 8 5.5 V MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION (Extended operating temperature version) The 3874 group (extended operating temperature version) is designed for automotive comfort and amusement control such as audio, air-conditioner etc., household appliances, and other consumer applications. Mitsubishi plans to expand the 3874 group (extended operating temperature version) as follows: Memory Type Support for mask ROM, One Time PROM, and EPROM versions Memory Size ROM/PROM size ............................................... 48 K to 60 K bytes RAM size .......................................................... 1024 to 2048 bytes Packages 80P6S-A .................................. 0.65 mm-pitch plastic molded QFP 80D0 ....................... 0.8 mm-pitch ceramic LCC (EPROM version) Memory Expansion Plan of 3874 group (Extended operating temperature version) Mass product ROM size (bytes) 60K M38749MFF/EFD 56K 52K Mass product M38747MCF 48K 44K 40K 36K 32K 28K 24K 20K 16K 1024 1536 2048 RAM size (byte) Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped during the development. Fig. 6 Memory expansion plan (Extended operating temperature version) Currently planning products are listed below. As of March 1998 Table 3 Support products Product name (P) ROM size (bytes) ROM size for User in ( ) RAM size (bytes) 80P6S-A M38749EFDGP M38749EFFS Package 61440 (61310) 2048 49152 (49022) 1024 80D0 Remarks One Time PROM version (blank) EPROM version (for software development, operating temperature = –20 to 85°C) M38749MFF M38747MCF 80P6S-A Mask ROM version 9 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION (Automotive version) ROM/PROM size ............................................... 16 K to 60 K bytes RAM size .......................................................... 1024 to 2048 bytes The 3874 group (automotive version) is designed for automotive body electronics control. Mitsubishi plans to expand the 3874 group (automotive version) as follows: Packages 80P6S-A .................................. 0.65 mm-pitch plastic molded QFP Memory Type Support for mask ROM and One Time PROM versions Memory Size Memory Expansion Plan of 3874 group (Automotive version) ROM size (byte) Mass product 60K M38749EFT *Supported only PROM version shipped after writing 56K 52K Mass product 48K M38747MCT 44K 40K 36K 32K 28K Mass product 24K 20K M38747M6T Mass product 16K M38747M4T 1536 1024 2048 RAM size (byte) Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped during the development. Fig. 7 Memory expansion plan (Automotive correspondence version) Currently planning products are listed below. Table 4 Support products Product name M38749EFT M38747MCT M38747M6T M38747M4T 10 As of March 1998 (P) ROM size (bytes) ROM size for User in ( ) 61440 (61310) 49152 (49022) 24576 (24446) 16384 (16254) RAM size (bytes) Package One Time PROM version 2048 1048 Remarks 80P6S-A Mask ROM version MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3874 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit etc. The CPU mode register is allocated at address 003B 16. b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : Page 0 1 : Page 1 XCOUT drivability selection bit 0 : Low drive 1 : High drive Port X C switch bit 0 : I/O port function 1 : X CIN–XCOUT oscillating function Main clock (X IN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(X IN)/2 (high-speed mode) 0 1 : φ = f(X IN)/8 (middle-speed mode) 1 0 : φ = f(X CIN)/2 (low-speed mode) 1 1 : φ = f(X IN) (double-speed mode) Note: When setting b7 to b3, refer to notes of Figure 71. Fig. 8 Structure of CPU mode register 11 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) 1024 1536 2048 Address XXXX16 000016 SFR area 043F16 063F16 083F16 Zero page 004016 RAM 010016 020016 Serial I/O3 automatic transfer RAM area 030016 XXXX16 Not used YYYY16 ROM area Reserved ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 Fig. 9 Memory map diagram 12 (128 bytes) ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 002016 Timer X (low-order) (TXL) 000116 Port P0 direction register (P0D) 002116 Timer X (high-order) (TXH) 000216 Port P1 (P1) 002216 Timer Y (low-order) (TYL) 000316 Port P1 direction register (P1D) 002316 Timer Y (high-order) (TYH) 000416 Port P2 (P2) 002416 Timer 1 (T1) 000516 Port P2 direction register (P2D) 002516 Timer 2 (T2) 000616 Port P3 (P3) 002616 Timer 3 (T3) 000716 Port P3 direction register (P3D) 002716 Timer X mode register (TXM) 000816 Port P4 (P4) 002816 Timer Y mode register (TYM) 000916 Port P4 direction register (P4D) 002916 Timer 123 mode register (T123M) 000A16 Port P5 (P5) 002A16 Communication mode register (BUSM) 000B16 Port P5 direction register (P5D) 002B16 Transmit control register (TXDCON) 000C16 Port P6 (P6) 002C16 Transmit status register (TXDSTS) 000D16 Port P6 direction register (P6D) 002D16 Receive control register (RXDCON) 000E16 Port P7 (P7) 002E16 Receive status register (RXDSTS) 000F16 Port P7 direction register (P7D) 002F16 Bus interrupt source discrimination control register (BICOND) 001016 Port P8 (P8) 003016 Control field selection register (CFSEL) 001116 Port P8 direction register (P8D) 003116 Control field register (CF) 001216 Port P9 (P9) 003216 Transmit/Receive FIFO (TRFIFO) 001316 Serial I/O3 register/Transfer counter (SIO3) 003316 PULL UP register (PULLU) 001416 Serial I/O3 control register 1 (SIO3CON1) 003416 A-D control register (ADCON) 001516 Serial I/O3 control register 2 (SIO3CON2) 003516 A-D/D-A conversion register (AD) 001616 Serial I/O3 control register 3 (SIO3CON3) 003616 Interrupt source discrimination register 2 (IREQD2) 001716 Serial I/O3 automatic transfer data pointer (SIO3DP) 003716 Interrupt source discrimination control register 2 (ICOND2) 001816 Transmit/Receive buffer register (TB/RB) 003816 Interrupt source discrimination register 1 (IREQD1) 001916 Serial I/O1 status register (SIO1STS) 003916 Interrupt source discrimination control register 1 (ICOND1) 001A16 Serial I/O1 control register (SIO1CON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART control register (UARTCON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator (BRG) 003C16 Interrupt request register 1 (IREQ1) 001D16 Serial I/O2 control register (SIO2CON) 003D16 Interrupt request register 2 (IREQ2) 001E16 Watchdog timer control register (WDTCON) 003E16 Interrupt control register 1 (ICON1) 001F16 Serial I/O2 register (SIO2) 003F16 Interrupt control register 2 (ICON2) Fig. 10 Memory map of special function register (SFR) 13 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS The I/O ports P0–P8 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 5 I/O port function (1) Pin P00 –P07 Name Port P0 Input/Output I/O Structure Input/output, individual bits •CMOS compatible input level •CMOS 3-state output P10–P17 Por t P1 Input/output, individual bits •CMOS compatible input level •CMOS 3-state output P20–P27 Port P2 Input/output, individual bits •CMOS compatible input level •CMOS 3-state output P30–P37 Port P3 Input/output, individual bits •CMOS compatible input level •CMOS 3-state output P40/X COUT P41/X CIN Port P4 Input/output, individual bits •CMOS compatible input level •CMOS 3-state output P42/INT1, P43/INT2 P44/R XD P45/T XD P46/S CLK1 Non-Port Function • K ey i n p u t ( k ey - o n wake-up) interrupt input •PULL UP register (2) •CPU mode register (1) •Sub-clock generating circuit I/O •CPU mode register (3) (4) •External interrupt input •Interrupt edge selection register •Serial I/O1 control register •Serial I/O1 status register •UART control register •PULL UP register (5) •Timer 2 output •Timer 123 mode register (10) •External interrupt input •Interrupt edge selection register (5) •Timer X function I/O •Timer Y function I/O •Timer X mode register (11) •Timer Y mode register •Timer X mode register (12) •Serial I/O1 function I/O Por t P5 Input/output, individual bits P51/INT3 , P52/INT4 , P53/INT5 P54 /CNTR0 P55 /CNTR1 P56 /RTP0 •CMOS compatible input level •CMOS 3-state output •Real time port function output P57 /RTP1 P60/AN 0– P67/AN 7 14 Port P6 Input/output, individual bits •CMOS compatible input level •CMOS 3-state output Ref.No. (1) P47/SRDY1 P50 /TOUT Related SFRs •Real time port function output •A-D converter input (6) (7) (8) (9) (13) •Timer Y mode register •A-D control register (14) MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 6 I/O port function (2) Pin P70/S IN2 Name Por t P7 P71/SOUT2 P72 /SCLK2 Input/Output I/O Function Non-Port Function Related SFRs Ref.No. Input/output, individual bits •CMOS compatible input level •CMOS 3-state output •Serial I/O2 function I/O •Serial I/O2 control register •PULL UP register (15) •Communication mode register •Transmit control register •Transmit status register •Receive control regiser (18) P73 ,P74 (16) (17) (1) P75/BUS OUT •Data link layer communication control I/O P76/BUS IN (19) •Receive status register •Bus interrupt source discrimination control register •Control field selection register •Control field register •Transmit/Receive FIFO P77/ADT P80/DA Port P8 P81 Input/output, individual bits •CMOS compatible input level •CMOS 3-state output P82/SOUT3 •A-D trigger input •A-D control register (20) •D-A function output •A-D control register (21) •Serial I/O3 register/ Transfer counter •Serial I/O3 control register 1 (22) •Serial I/O3 control register 2 •Serial I/O3 control register 3 •Serial I/O3 automatic transfer data pointer (25) •Interrupt edge selection register (28) (1) •Serial I/O3 function I/O P83/S IN3 P84/S CLK3 P85/SRDY3 P86/SBUSY3 P87/S STB3 P97/INT0 Port P9 Input •CMOS compatib le input level •External interrupt input (23) (24) (26) (27) Note: Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate. 15 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Pull-up Control P20–P26 , TXD, S CLK1, S OUT2, and SCLK2 can perform pull-up control by setting “1” to the pull-up register (address 003316 ). P2 0–P2 7’s pull-up is valid in the input mode, and TXD, S CLK1 , SOUT2, and SCLK2 s’ pull-up is valid in the output mode. b7 b0 Pull-up register (PULLU : address 0033 16) P26, P27 pull-up P25 pull-up P22–P24 pull-up P20, P21 pull-up TXD, S CLK1 pull-up SOUT2, SCLK2 pull-up Not used (returns “0” when read) (Do not write “1” to these bits.) Fig.11 Structure of Pull-up Register 16 0: No pull-up 1: Pull-up MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P0,P1,P3,P73,P74,P81 (2) Port P2 P2 pull-up Direction register Direction register Data bus Port latch Data bus Port latch Key input interrupt input (3) Port P40 (4) Port P41 Port XC switch bit Port XC switch bit Direction register Data bus Direction register Port latch Port latch Data bus Oscillator Sub-clock generating circuit input Port P41 Port XC switch bit (5) Ports P42,P43,P51,P52,P53 (6) Port P44 Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch INT1–INT5 interrupt input Direction register Data bus Port latch Serial I/O1 input Fig. 12 Port block diagram (1) 17 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (7) Port P45 (8) Port P46 TXD pull-up P45/TXD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch Serial I/O1 output SCLK1 pull-up Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Direction register Port latch Data bus Serial I/O1 clock output Serial I/O1 clock input (9) Port P47 (10) Port P50 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Direction register Data bus Port latch Data bus Serial I/O1 ready output (11) Port P54 Port latch TOUT output control bit Timer output (12) Port P55 Direction register Direction register Data bus Port latch Pulse output mode Timer output CNTR0 interrupt input Event count input Pulse width measurement gate input Fig. 13 Port block diagram (2) 18 Data bus Port latch CNTR1 interrupt input Event count input Reload input MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (14) Port P6 (13) Ports P56, P57 Direction register Direction register Data bus Port latch Data bus Real time port control bit Data for real time port Port latch A-D converter input Analog input pin selection bit (15) Port P70 Direction register Data bus Port latch Serial I/O2 input (16) Port P71 SOUT2 output signal in operating SCLK2 pin selection bit SOUT2 output control bit SOUT2 pull-up P-channel output disable bit SOUT2 pin selection bit Direction register Data bus Port latch Serial I/O2 output Fig. 14 Port block diagram (3) 19 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (17) Port P72 SCLK2 pin selection bit SCLK2 pull-up P71/SOUT2 • P72/SCLK2 P-channel output disable bit Direction register Data bus Port latch Serial I/O2 clock output Serial I/O2 clock input (18) Port P75 (19) Port P76 Data link layer communication control circuit valid signal (output from sub-CPU) Data link layer communication control circuit valid signal (output from sub-CPU) Direction register Port latch Data bus Data link layer communication control circuit transmit output Direction register Data bus Data link layer communication control circuit receive input (21) Port P80 (20) Port P77 Direction register Direction register Data bus Port latch Port latch ADT interrupt input Data bus Port latch D-A converter output D-A ON When the direction register is “0,” the schmidt input pin is connected to port. Fig. 15 Port block diagram (4) 20 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (22) Port P82 (23) Port P83 P82/SOUT3 • P84/SCLK3 P-channel output disable bit Transfer mode selection bit Serial transfer selection bit Serial I/O disabled SOUT3 output control bit Serial transfer selection bit Serial I/O disabled Direction register Direction register Data bus Data bus Port latch Port latch Serial I/O3 input Serial I/O3 output (25) Port P85 (24) Port P84 P82/SOUT3 • P84/SCLK3 Serial I/O3 synchronous P-channel output disable bit clock selection bit Internal synchronous clock Serial transfer selection bit Serial I/O disabled P85/SRDY3 • P86/SBUSY3 pin control bit SRDY3 output P85/SRDY3 • P86/SBUSY3 pin control bit SRDY3 input Serial transfer selection bit Serial I/O disabled Direction register Direction register Data bus Port latch Data bus Serial I/O3 clock output Serial I/O3 clock input (26) Port P86 Port latch Serial I/O3 ready output Serial I/O3 ready input (27) Port P87 P85/SRDY3 • P86/SBUSY3 pin control bit SBUSY3 output P85/SRDY3 • P86/SBUSY3 pin control bit SBUSY3 input Serial transfer selection bit Serial I/O disabled Serial I/O3 synchronous clock selection bit SSTB3,SSTB3 output Serial I/O disabled Direction register Data bus Direction register Port latch Data bus Port latch Serial I/O3 busy output Serial I/O3 busy input Fig. 16 Port block diagram (5) 21 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (28) Port P97 Data bus INT0 interrupt input Fig. 17 Port block diagram (6) 22 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupt Factor Determination Interrupts occur by 27 sources: 10 external, 16 internal, and 1 software. The interrupt request bit for each vector of “multiple factors/one vector interrupt” is set to “1” when the interrupt disable flag (I) is “0” and one of the factor interrupt enable bits is “1” and the corresponding factor interrupt request bit changes from “0” to “1”. At this time, if the vector interrupt enable bit is “1”, the interrupt occurs. (Note that the interrupt request bit for each vector and the factor interrupt request bit are both edge sense.) When 2 or more interrupt requests of interrupt factors assigned to one interrupt vector are generated at the same time, confirm the interrupt request bits for each interrupt factor assigned to the vector, and process according to the priority. If the interrupt request bit for the interrupt factor is “1” and the interrupt enable bits for interrupt factor and each vector are both “1”; for example, when an interrupt of another interrupt factor assigned to the same vector occurs while an interrupt processing routine is executed, the interrupt occurs again after returning. Clear the interrupt request bits which are not necessary or which have been already processed before executing the interrupt flag clear (CLI) or interrupt processing routine return (RTI) instruction. The interrupt request bits for each interrupt factor are not cleared by hardware after an interrupt vector address branching. Clear these bits by software in the interrupt processing routine. Use the LDM, STA, etc. instructions to do it. Do not use the read- modifywrite instruction; for example, the CLB. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. The interrupt control circuit consists of two types of interrupts: “one factor/one vector interrupt” and “multiple factors/one vector interrupt”. The configuration is shown in Figure 18. Interrupt Operation When an interrupt occurs, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit for each vector is cleared. (The corresponding interrupt request bit for each interrupt factor is not cleared.) 3. The interrupt jump destination address of interrupt which has the highest priority is loaded to the program counter. ■ Notes When the active edge of an external interrupt (INT0–INT5, CNTR0, CNTR1) is set, the corresponding interrupt request bit may also be set. Therefore, take following sequence: (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register (in case of CNTR0: Timer X mode register; in case of CNTR 1: Timer Y mode register). (3) Clear the set interrupt request bit to “0”. (4) Enable the external interrupt which is selected. 23 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 7 Interrupt vector addresses and priority Interrupt Sources Priority Vector Addresses (Note 1) High Low FFFD 16 FFFC 16 FFFB16 FFFA16 Reset (Note 2) INT0 1 2 INT1 3 FFF916 FFF816 Receive bus interrupt source 1 4 FFF716 FFF616 Receive bus interrupt source 2 Receive bus interrupt source 3 Transmit bus interrupt source 1 5 FFF516 FFF416 Transmit bus interrupt source 2 Transmit bus interrupt source 3 Timer X Timer Y Timer 2 Timer 3 6 7 8 9 10 FFF316 FFF116 FFEF16 FFED16 FFEB 16 FFF216 FFF016 FFEE 16 FFEC16 FFEA 16 Serial I/O3 interrupt CNTR0 11 FFE916 FFE816 CNTR1 12 FFE716 FFE616 Timer 1 INT3 13 14 FFE516 FFE316 FFE416 FFE216 INT2 INT4 INT5 ADT 15 FFE116 FFE016 Interrupt Request Generating Conditions Remarks At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) The condition which the receive bus interrupt factor request bit becomes “1” is defined according to each communication protocol specification confirmation. When receive bus source 1 request bit “1” from “0” When receive bus source 2 request bit “1” from “0” When receive bus source 3 request bit “1” from “0” When transmit bus source 1 request bit “1” from “0” When transmit bus source 2 request bit “1” from “0” When transmit bus source 3 request bit “1” from “0” At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow interrupt becomes interrupt becomes interrupt becomes interr upt becomes interr upt becomes interr upt becomes At detection of either rising or falling edge of INT2 input At completion of serial I/O3 data transmission/reception At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of INT5 input At falling of ADT pin input A-D converter At completion of A-D converter Serial I/O2 interrupt Key input (keyon wake-up) Serial I/O1 receive Serial I/O1 transmit At completion of serial I/O2 data transmission/reception At falling of port P2 0 to P2 5 (at input) input logical level AND BRK instruction 16 17 FFDF 16 FFDD 16 FFDE16 FFDC16 The condition which the transmit bus interrupt factor request bit becomes “1” is defined according to each communication protocol specification confirmation. At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At BRK instruction execution External interrupt (active edge selectable) Valid only when serial I/O3 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid only when ADT interrupt is selected External interrupt (falling valid) Valid only when A-D converter interrupt is selected Valid only when serial I/O2 is selected External interrupt (falling valid) Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: Either ADT interrupt or A-D converter interrupt can be used. Both ADT interrupt and A-D converter interrupt cannot be used. 24 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Multiple factors/one vector interrupt Interrupt request of interrupt factor: IDREQINYZ D Q Interrupt request bit for interrupt factor Interrupt request bit for each vector: IREQY Interrupt request from multiple factors: IDREQY T R Clear instruction by user program D Interrupt enable bit for interrupt factor D Q T SYNC Internal system clock φ STP Instruction D Q T R Q T R R Interrupt request get control signal: IREQGET Clear instruction by user program Interrupt disable flag (I) Hardware clear signal by occurrence of interrupt Clear instruction by user program Interrupt enable bit for each vector One factor/one vector interrupt Interrupt request bit for each vector: IREQX D Interrupt Request IREQINX Q T R D Q T R Interrupt request get control signal: IREQGET Hardware clear signal by occurrence of interrupt Clear instruction by user program Interrupt enable bit for each vector Interrupt occurrence Interrupt disable flag (I) BRK Instruction Reset Fig.18 Interrupt control diagram 25 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing to Interrupt Request Acceptance The cycle number of internal system clock required from occurrence to acceptance of an interrupt request depends on the type of interrupt: “multiple factors/one vector” or “one factor/one vector”. For “one factor/one vector interrupt”, the CPU starts processing the management after interrupt acceptance at the next instruction execution timing (rising edge of SYNC signal) immediately after the interrupt request is generated. For “multiple factors/one vector interrupt”, the CPU starts processing the management after interrupt acceptance at the second instruction execution timing (rising edge of SYNC signal) after the interrupt request for interrupt factor determination is generated. In other words, “multiple factors/one vector interrupt” required one instruction execution cycle number (2 to 16 cycles of internal system clock) more than that of “one factor/one vector interrupt” to begin the interrupt sequence. Figure 18 shows the interrupt control diagram and Figure 19 shows the timing from occurrence to acceptance of interrupt request. For “one factor/one vector interrupt”, the interrupt request is generated at Timing (A) and the processing after acceptance begins at Timing (B). For “multiple factors/one vector interrupt”, the interrupt factor determination request is generated at Timing (C), the interrupt request is generated at Timing (D), and the processing after acceptance begins at Timing (E). 26 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal system clock φ SYNC Address bus S,SPS PC Data bus Not used S-1,SPS PCH S-2,SPS PCL PS Interrupt request signal input IREQINx Interrupt request signal IREQx IRGET (A) Management after interrupt acceptance (B) (a) One factor/one vector interrupt Internal system clock φ SYNC Address bus PC Data bus Not used Interrupt source determination request signal input IDREQIN Y Interrupt request signal from interrupt source IDREQY Interrupt request signal IREQY IRGET (C) (D) 2 to 16 cycles of φ Management after interrupt acceptance (E) (b) Multiple factors/one vector interrupt Fig.19 Timing from occurrence to acceptance of interrupt 27 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT5 active edge selection bit Not used (returns “0” when read) b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) INT0 interrupt request bit INT1 interrupt request bit Receive bus interrupt request bit Transmit bus interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit INT2 interrupt request bit CNTR0, serial I/O3 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT3, INT4, INT5 interrupt request bit ADT/A-D converter, serial I/O2 interrupt request bit Key input, serial I/O1 receive, serial I/O1 transmit interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) 0 : No interrupt request issued 1 : Interrupt request issued b7 0 : Interrupts disabled 1 : Interrupts enabled b0 Interrupt source discrimination register 1 (IREQD1 : address 003816) 0 : Interrupts disabled 1 : Interrupts enabled b7 INT3 interrupt request bit INT4 interrupt request bit INT5 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Key input interrupt request bit Serial I/O2 interrupt request bit ATD/A-D converter interrupt request bit b0 Interrupt source discrimination register 2 (IREQD2 : address 003616) CNTR0 interrupt request bit Serial I/O3 interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued Fig. 20 Structure of interrupt-related registers 28 b0 Interrupt source discrimination control register 1 (ICOND1 : address 003916) INT3 interrupt enable bit INT4 interrupt enable bit INT5 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Key input interrupt enable bit Serial I/O2 interrupt enable bit ADT/A-D converter interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued b7 Interrupt control register 2 (ICON2 : address 003F16) INT2 interrupt enable bit CNTR0, serial I/O3 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT3, INT4, INT5 interrupt enable bit ADT/A-D converter, serial I/O2 interrupt enable bit Key input, serial I/O1 receive, serial I/O1 transmit interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) INT0 interrupt enable bit INT1 interrupt enable bit Receive bus interrupt enable bit Transmit bus interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 b0 0 : Interrupt disabled 1 : Interrupt enabled b7 b0 Interrupt source discrimination control register 2 (ICOND2 : address 003716) CNTR0 interrupt enable bit Serial I/O3 interrupt enable bit Not used (return “0” when read) 0 : Interrupt disabled 1 : Interrupt enabled MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Key Input Interrupt A Key input interrupt request is generated by applying “L” level to any pin of por t P2 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P24. Port PXx “L” level output PULL UP register Bit 0 = “0” Port P27 direction register = “1” ✽ ✽✽ P27 output Key input interrupt request Port P27 latch Port P26 direction register = “1” ✽ ✽✽ P26 output Port P26 latch PULL UP register Bit 1 = “0” ✽ ✽✽ P25 output Port P25 latch PULL UP register Bit 2 = “1” ✽ ✽✽ P24 input Port P25 direction register = “1” Port P24 direction register = “0” Port P24 latch Port P23 direction register = “0” ✽ ✽✽ ✽ ✽✽ P23 input Port P2 Input reading circuit Port P23 latch Port P22 direction register = “0” P22 input Port P22 latch PULL UP register Bit 3 = “1” ✽ ✽✽ ✽ ✽✽ P21 input P20 input Port P21 direction register = “0” Port P21 latch Port P20 direction register = “0” Port P20 latch ✽ P-channel transistor for pull-up ✽✽ CMOS output buffer Fig. 21 Connection example when using key input interrupt and port P2 block diagram 29 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS responding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. The 3874 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0016 ” or “0000 16”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- Real time port control bit “1” Data bus Q D P56/RTP 0 P56 data for real time port Latch P56 direction register “0” P56 latch Real time port control bit “1” Q D P57/RTP 1 P57 data for real time port Real time port control bit “0” Latch P57 direction register “0” P57 latch Timer X mode register write signal “1” XIN/16 (XCIN /16 in φ = XCIN/2) P54 /CNTR0 Timer X stop control bit Timer X operating mode bit “00”,“01”,“11” CNTR0 active edge switch bit “0” Timer X write control bit Timer X (low) latch (8) Timer X (high) latch (8) Timer X (low) (8) Timer X (high) (8) “10” “1” Pulse width measurement mode CNTR0 active edge switch bit “0” Timer X interrupt Pulse output mode QS T “1” Q P54 direction register Pulse width HL continuously measurement mode P54 latch Rising edge detection Pulse output mode Period measurement mode Falling edge detection P55 /CNTR1 CNTR1 active edge switch bit “0” XIN /16 (XCIN /16 in φ = XCIN /2) Timer Y stop control bit Timer Y (low) latch (8) “00”,“01”,“11” Timer Y (high) latch (8) Timer Y (low) (8) “10” Timer Y operating mode bit “1” XIN /16 (X CIN /16 in φ = XCIN /2) Timer 1 count source selection bit “0” Timer 1 latch (8) XCIN Timer 1 (8) “1” TOUT output active edge switch bit “0” P50/TOUT “1” P50 latch P50 direction register TOUT output control bit XIN /16(XCIN/16 in φ = XCIN /2) Timer 2 count source selection bit Timer 2 latch (8) “0” Timer 2 (8) “1” XIN /16 (XCIN /16 in φ = XCIN /2) 30 Timer 2 write control bit Timer 1 interrupt Timer 2 interrupt TOUT output control bit QS T Q “0” Timer 3 latch (8) Timer 3 (8) “1” Timer 3 count source selection bit Fig. 22 Timer block diagram Timer Y interrupt Timer Y (high) (8) Timer 3 interrupt MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN )/16 in system clock φ = XCIN / 2). (2) Pulse Output Mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the direction register of corresponding port to output mode. (3) Event Counter Mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. (4) Pulse Width Measurement Mode The count source is f(X IN)/16 (or f(X CIN)/16 in system clock φ = XCIN/2. If CNTR0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. ■ Notes b7 b0 Timer X mode register (TXM : address 0027 16) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P56 data for real time port P57 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Count at rising edge in event counter mode Start from “H” output in pulse output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for CNTR 0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNTR 0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop Fig. 23 Structure of timer X mode register ● Timer X write control If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. When the value is to be written in latch only, if the value is written to the latch at timer X underflows, the value is consequently loaded in the timer X and the latch at the same time. Unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. ● CNTR0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. ● Real time port control Data for the real time port are output from ports P56 and P57 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1”, data are output independent of the timer X operation.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. 31 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in system clock φ = XCIN / 2). (2) Period Measurement Mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR1 interrupt. b7 b0 Timer Y mode register (TYM : address 0028 16) Not used (return “0” when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. (4) Pulse Width HL Continuously Measurement Mode CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. ■ Note ● CNTR 1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 32 Fig. 24 Structure of timer Y mode register MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. ● Timer 2 write control When the timer 2 write control bit is “1”, and the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. When the timer 2 write control bit is “0”, and the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. ● Timer 2 output control An inversion signal from T OUT pin is output each time timer 2 underflows. In this case, set the port P50 direction register to the output mode. ■ Note ● Timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. b7 b0 Timer 123 mode register (T123M :address 0029 16) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) 1 : f(XCIN ) Not used (return “0” when read) Note : Internal clock φ is f(XCIN)/2 in the low-speed mode. Fig. 25 Structure of timer 123 mode register 33 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O Serial I/O1 (1) Clock Synchronous Serial I/O1 Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register (address 001816). Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Data bus Serial I/O1 control register Address 0018 16 Receive buffer register (RB) Receive shift register P44 /RXD Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Shift clock Clock control circuit P46 /SCLK1 XIN Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit Baud rate generator P47 /SRDY1 F/F 1/4 Address 001C 16 1/4 Clock control circuit Falling-edge detector Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Shift clock P45 /TXD Transmit shift register Transmit buffer register (TB) Transmit buffer empty flag (TBE) Address 0019 16 Serial I/O1 status register Address 0018 16 Data bus Fig. 26 Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial I/O1 output T XD D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O1 input R XD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal S RDY1 Write signal to receive/transmit buffer register (address 0018 16) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the T XD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 27 Operation of clock synchronous serial I/O1 function 34 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- Data bus Address 0018 16 P44 /RXD Serial I/O control register Address 001A16 Receive buffer register OE Character length selection bit 7 bits STdetector Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 8 bits PE FE UART control register Address 001B16 SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46 /SCLK1 XIN BRG count source selection bit 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C 16 ST/SP/PA generator Transmit shift register shift completion flag (TSC) 1/16 P45 /TXD Transmit shift register Transmit interrupt source selection bit Transmit interrupt request (TI) Character length selection bit Transmit buffer register Address 0018 16 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 0019 16 Data bus Fig. 28 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial I/O output T XD TBE=0 TSC=1✽ TBE=1 ST D0 D1 SP ST D0 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) Receive buffer read signal ✽ Generated RBF=0 RBF=1 Serial I/O input R XD ST D0 D1 D1 SP ST D0 D1 SP at 2nd bit in 2-stop-bit mode RBF=1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 29 Operation of UART serial I/O function 35 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Transmit Buffer/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit (bit 7) of the Serial I/O1 control register also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B 16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of a data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/T XD pin and P46/S CLK1 pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 36 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O1 status register (SIO1STS : address 0019 16 ) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty b0 b0 Serial I/O1 control register (SIO1CON : address 001A 16) BRG count source selection bit (CSS) 0: f(XIN ) 1: f(XIN )/4 Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clockk synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. Overrun error flag (OE) 0: No error 1: Overrun error SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as S RDY1 output pin Parity error flag (PE) 0: No error 1: Parity error Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Framing error flag (FE) 0: No error 1: Framing error Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Not used (returns “1” when read) Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full b7 b7 UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 –P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44 –P47 operate as serial I/O pins) Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45 /TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return “1” when read) Fig. 30 Structure of serial I/O1 control register 37 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O2 b7 The Serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. b0 Serial I/O2 control register (SIO2CON : address 001D 16) Serial I/O2 internal synchronous clock selection bits b2 b1 b0 [Serial I/O2 Control Register (SIO2CON)] 001D16 000 001 010 011 100 101 110 111 : f(XIN)/8 or f(XCIN)/8 : f(XIN)/16 or f(XCIN)/16 : f(XIN)/32 or f(XCIN)/32 : f(XIN)/64 or f(XCIN)/64 : : Do not set The serial I/O2 control register contains 8 bits which control various serial I/O functions. SOUT2 pin selection bit 0 : I/O port 1 : SOUT2 output pin : f(XIN)/128 or f(XCIN)/128 : f(XIN)/256 or f(XCIN)/256 P71/SOUT2 • P72/SCLK2 P-channel output disable bit In output mode 0 : CMOS 3 state 1 : N-channel open-drain output Serial I/O2 transfer direction selection bit 0 : LSB first 1 : MSB first SCLK2 pin selection bit 0 : External clock (S CLK2 function as an I/O port.) 1 : Internal clock (S CLK2 function as an output port.) SOUT2 output control bit (when serial data is not transferred) 0 : Output active 1 : High-impedance Fig. 31 Structure of serial I/O2 control register Data bus XCIN 1/16 Divider “10” 1/8 Main clock divide ratio selection bit CM7 XIN “00,01,11” SCLK2 pin selection bit “1” 1/32 1/64 1/128 1/256 SCLK2 External clock “0” “0” Serial I/O2 internal synchronous clock selection bits P72 latch P72/SCLK2 “1” SCLK2 pin selection bit “0” P71/SOUT2 SOUT2 P71 latch “1” pin selection bit P70/SIN2 Fig. 32 Block diagram of serial I/O2 38 Serial I/O2 counter (3) Serial I/O2 register (8) Serial I/O2 interrupt request MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ●Serial I/O2 Operation When writing to the serial I/O2 register (001F 16), the serial I/O2 counter is set to “7”. After the write is completed, data is output from the SOUT2 pin each time the transfer clock goes from “H” to “L”. In addition, each time the transfer clock goes from “L” to “H”, the contents of the serial I/O2 register are shifted by 1 bit data is simultaneously received from the SIN2 pin. When selecting an internal clock as the transfer clock source, the serial I/O2 counter goes to “0” by counting the transfer clock 8 times, and the transfer clock stops at “H”, and the interrupt request bit is set to “1”. In addition, the SOUT2 pin becomes the high-impedance state after the completion of data transfer. (Bit 7 of the serial I/O2 control register does not go to “1” and only the SOUT2 pin becomes the high-impedance state.) When selecting an external clock as the transfer clock source, the interrupt request bit is set when counting the transfer clock 8 times. However, the transfer clock does not stop, so that control the clock externally. The SOUT2 pin does not become the high-impedance state after completion of data transmit. In order to set the SOUT2 pin to the high-impedance state when selecting an exter nal clock, set “1” to bit 7 of the ser ial I/O2 control register after completion of data transmit. Also, make sure that SCLK2 is at “H” for this process. When the next data is transmitted (falling of transfer clock), bit 7 of the serial I/O2 control register goes to “0” and the SOUT2 pin goes to an active state. Synchronous clock Transfer clock Serial I/O2 register write signal (Note) Serial I/O2 output SOUT2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Note: When selecting an internal clock after completion of data transmit, the S OUT2 pin becomes the high-impedance state. Interrupt request bit set Fig. 33 Serial I/O2 timing (LSB first) 39 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER The P85 /SRDY3, P8 6/SBUSY3 , and P87 /SSTB3 pins all have the handshake input/output signal function and can perform active logic high/low selection. Serial I/O3 Serial I/O3 has the following modes: 8-bit serial I/O, arbitrary bits from 1 to 256 serial I/O, up to 256-byte auto-transfer serial I/O. The 8-bit serial I/O transfers through serial I/O3 register (address 0013 16). The arbitrary bits and auto-transfer serial I/O modes transfer through the 256-byte serial I/O3 auto-transfer RAM (addresses 020016 to 02FF16 ). Main address bus Local address bus Serial I/O3 automatic transfer RAM (020016 to 02FF16) Main data bus Local data bus Serial I/O3 automatic transfer data pointer Address decoder Transfer counter Serial I/O3 automatic transfer controller XCIN Serial I/O3 automatic transfer interval register Main clock division ratio selection bits “10” 1/4 1/8 XIN 1/16 “00,01” P87/SSTB3 Divider P87 latch “00,01,11” (P87/SSTB3 pin control bits) “10,11” P86 latch P85/SRDY3• P86/SBUSY3 pin control bits “0” P86/SBUSY3 P85/SRDY3• P86/SBUSY3 pin control bits P85/SRDY3 “1” P85 latch “1” Serial I/O3 internal Serial I/O3 synchronous clock synchronous clock selection bits “00,10,11” selection bits Synchronous circuit “01” External clock P84 latch 1/64 1/128 1/256 1/512 SCLK3 “0” 1/32 Serial transfer status flag “0” P84/SCLK3 “1” “0” Serial transfer selection bits P83 latch Serial I/O3 counter P82/SOUT3 “1” Serial transfer selection bits P83/SIN3 Fig. 34 Block diagram of serial I/O3 40 Serial I/O3 register (8) Serial I/O3 interrupt request MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O3 control register 1 (SIO3CON1 (SC31) : address 0014 16) Serial transfer selection bits 00 : Serial I/O disabled (P8 2 to P87 pins are I/O ports.) 01 : 8-bit serial I/O 10 : Arbitrary bit serial I/O 11 : Automatic transfer serial I/O (8-bit) Serial I/O3 synchronous clock selection bits (P8 7/SSTB3 pin control bits) 00 : Internal synchronous clock (P8 7 pin is I/O port.) 01 : External synchronous clock (P8 7 pin is I/O port.) 10 : Internal synchronous clock (P8 7 pin is SSTB3 output.) 11 : Internal synchronous clock (P8 7 pin is SSTB3 output.) Serial I/O initialization bit 0 : Serial I/O initialization 1 : Serial I/O enabled Transfer mode selection bit 0 : Full duplex (transmit/receive) mode (P8 3 pin is SIN3 I/O.) 1 : Transmit-only mode (P8 3 pin is I/O port.) Serial I/O3 transfer direction selection bit 0 : LSB First 1 : MSB First Automatic transfer RAM transmit/receive address selection bit 0 : Transmit/Receive address match 200 16 to 2FF16 (Set automatic transfer data pointer to 00 16 to FF16.) 1 : Transmit address 200 16 to 27F16 Receive address 280 16 to 2FF16 (Set automatic transfer data pointer to 00 16 to 7F16.) b7 b0 Serial I/O3 control register 2 (SIO3CON2 (SC32) : address 0015 16) P85/SRDY3 • P86/SBUSY3 pin control bits 0000: P85, P86 pins are I/O ports. 0001: Unused 0010: P85 pin is SRDY3 output, P86 pin is I/O port. 0011: P85 pin is SRDY3 output, P86 pin is I/O port. 0100: P85 pin is I/O port, P8 6 pin is SBUSY3 input. 0101: P85 pin is I/O port, P8 6 pin is SBUSY3 input. 0110: P85 pin is I/O port, P8 6 pin is SBUSY3 output. 0111: P85 pin is I/O port, P8 6 pin is SBUSY3 output. 1000: P85 pin is SRDY3 input, P86 pin is SBUSY3 output. 1001: P85 pin is SRDY3 input, P86 pin is SBUSY3 output. 1010: P85 pin is SRDY3 input, P86 pin is SBUSY3 output. 1011: P85 pin is SRDY3 input, P86 pin is SBUSY3 output. 1100: P85 pin is SRDY3 output, P86 pin is SBUSY3 input. 1101: P85 pin is SRDY3 output, P86 pin is SBUSY3 input. 1110: P85 pin is SRDY3 output, P86 pin is SBUSY3 input. 1111: P85 pin is SRDY3 output, P86 pin is SBUSY3 input. SBUSY3 output • S STB3 output function selection bit (valid in automatic transfer mode) 0: Functions as signal for each 1-byte 1: Functions as signal for each transfer data set Serial transfer status flag 0: Serial transfer complete 1: Serial transfer in-progress SOUT3 output control bit (when serial data is not transferred) 0: Output active 1: Output high impedance P82/SOUT3 • P84/SCLK3 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Fig. 35 Structure of serial I/O3 control registers 1 and 2 41 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ●Serial I/O3 Operation An internal or external synchronous clock can be selected as the serial transfer synchronous clock by the serial I/O3 synchronous clock selection bits of the serial I/O3 control register 1. Since the internal synchronous clock has its own built-in divider, 8 types of clocks can be selected by the serial I/O3 internal synchronous clock selection bits of the serial I/O3 control register 3. Either I/O port or handshake I/O signal function can be selected for the P8 5/S RDY3, P86 /SBUSY3, and P87 /S STB3 pins by the serial I/O3 synchronous clock selection bits (P8 7/S STB3 pin control bits) of the serial I/O3 control register 1 or the P85 /SRDY3•P86 /SBUSY3 pin control bits of the serial I/O3 control register 2. CMOS output or N-channel open-drain output can be selected for the SCLK3 and SOUT3 output pins by the P82/S OUT3 • P84 /SCLK3 Pchannel output disable bit of the serial I/O3 control register 2. The SOUT3 output control bit of the serial I/O3 control register 2 can be used to select the status of the SOUT3 pin when serial data is not transferred; either output active or high-impedance. However, when selecting an external synchronous clock, the S OUT3 pin can go to the high-impedance status by setting the SOUT3 output control bit to “1” when S CLK3 input is at “H” after transfer completion. When the next serial transfer begins and SCLK3 goes to “L”, the S OUT3 output control bit is automatically reset to “0” and goes to an output active status. b7 Regardless of selecting an internal or external synchronous clock, the serial transfer has both a full duplex mode as well as a transmit-only mode. These modes are set by the transfer mode selection bit of serial I/O3 control register 1. LSB first or MSB first can be selected for the input/output order of the serial transfer bit string by the serial I/O3 transfer direction selection bit of serial I/O3 control register 1. In order to use serial I/O3, the following process must be followed after all of the above set have been completed: First, select any one of 8-bit serial I/O, arbitrary bit serial I/O, or auto-transfer serial I/O by setting the serial transfer selection bits of the serial I/O3 control register 1. Then, enable the serial I/O by setting the serial I/O initialization bit of the serial I/O3 control register 1 to “1”. Whether using an internal or external synchronous clock, set the serial I/O initialization bit to “0” when terminating a serial transfer during the transmission. b0 Serial I/O3 control register 3 (SIO3CON3 (SC33) : address 0016 16) Auto-transfer interval set bit 00000: 2 cycles of transfer clock 00001: 3 cycles of transfer clock : 11110: 32 cycles of transfer clock 11111: 33 cycles of transfer clock Written to latch Read from decrement counter Serial I/O3 internal synchronous clock selection bits 000: f(XIN)/4 or f(XCIN)/4 001: f(XIN)/8 or f(XCIN)/8 010: f(XIN)/16 or f(X CIN)/16 011: f(XIN)/32 or f(X CIN)/32 100: f(XIN)/64 or f(X CIN)/64 101: f(XIN)/128 or f(X CIN)/128 110: f(XIN)/256 or f(X CIN)/256 111: f(XIN)/512 or f(X CIN)/512 Fig. 36 Structure of serial I/O3 control register 3 42 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) 8-bit serial I/O mode Address 001316 is the serial I/O3 register. When selecting an internal synchronous clock, serial transfer of the 8-bit serial I/O starts by the write signal to the serial I/O3 register (address 001316 ). The serial transfer status flag of the serial I/O3 control register 2 indicates the serial I/O3 register status. The flag is set to “1” by a serial I/O3 register write, which triggers a transfer start. After the 8-bit transfer is completed, the flag is reset to “0” and a serial I/O3 interrupt request occurs simultaneously. When an external synchronous clock is selected, the contents of the serial I/O3 register are continually shifted while the transfer clock inputs to SCLK3. In this case, control the clock externally. (2) Auto-transfer serial I/O mode Since read and write to the serial I/O3 register are controlled by the serial I/O3 automatic transfer controller, address 001316 functions as the transfer counter (in byte units). In order to make a serial transfer through the serial I/O3 automatic transfer RAM (addresses 020016 to 02FF16), it is necessary to set the serial I/O3 automatic transfer data pointer before transferring data. The automatic transfer data pointer set bits indicate the loworder 8 bits of the star t data stored address. The automatic transfer RAM transmit/receive address select bit can divide the 256-byte serial I/O3 automatic transfer RAM into two areas: 128byte transmit data area and 128-byte receive data area. When an internal synchronous clock is selected and any of the following conditions apply, the transfer interval between each 1-byte data can be set by the automatic transfer interval set bits of the serial I/O3 control register 3: 1. The handshake signal is not used. 2. The handshake signal’s S RDY3 output, S BUSY3 output, and SSTB3 output are used independently. 3. The handshake signal’s output is used in groups: SRDY3/S STB3 output or SBUSY3/S STB3. There are 32 values among 2 and 33 cycles of the transfer clock. When the automatic transfer interval setting is valid and SBUSY3 output is used, and the S BUSY3 and S STB3 output function as sig- b7 nal for each transfer data set by the SBUSY3 output•SSTB3 output function selection bit, there is the transfer interval before the first data is transmitted/received, as well as after the last data is transmitted/received. When using S STB3 output, regardless of the contents of the S BUSY3 output • SSTB3 output function selection bit, this transfer interval become 2 cycles longer than the value set for each 1-byte data. In addition, when using the combined output of S BUSY3 and SSTB3 as the signal for each transfer data set, the transfer interval after completion of transmission/receipt of the last data become 2 cycles longer than the set value. When selecting an exter nal synchronous clock, the automatic transfer interval cannot be set. After all of the above bit settings have been completed, and an internal synchronous clock has been selected, serial automatic transfer starts when the value of the number of transfer bytes, decremented by 1, is written to the transfer counter (address 001316). When an external synchronous clock is selected, write the value of the transfer bytes, decremented by 1, to the transfer counter, and input the transfer clock to S CLK3 after 5 or more cycles of internal clock φ. Set the transfer interval of each 1-byte data transmission to 5 or more cycles of the internal clock φ after the rising edge of the last bit of a 1-byte data. Regardless of internal or external synchronous clock, the automatic transfer data pointer and transfer counter are both decremented after receipt of each 1-byte data is completed and it is written to the automatic transfer RAM. The serial transfer status flag is set to “1” by writing to the transfer counter which triggers the start of transmission. After the last data is written to the automatic transfer RAM, the serial transfer status flag is set to “0” and a serial I/O3 interrupt request occurs simultaneously. The write values of the automatic transfer data pointer set bits and the automatic transfer interval set bits are kept in the latch. As a transfer counter write occurs, each value is transferred to its corresponding decrement counter. b0 Serial I/O3 automatic transfer data pointer (SIO3DP : address 0017 16) Automatic transfer data pointer set bits Indicates the low-order 8 bits of the address stored the start data on the serial I/O3 automatic transfer RAM. Write: kept in latch Read: from decrement counter Fig. 37 Structure of serial I/O3 automatic transfer data pointer 43 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (3) Arbitrary bit serial I/O mode Since read and write of the serial I/O3 register are controlled by the serial I/O3 automatic transfer controller, address 001316 functions as the transfer counter (in byte units). After the serial I/O3 automatic transfer data pointer and automatic transfer interval set bits have been set, and an internal synchronous clock selected, serial automatic transfer starts when the value of the number of transfer bits decremented by 1 is written to the transfer counter (address 0013 16), just as in the automatic transfer serial I/O. When selecting an external synchronous clock, write the value of the transfer bits decremented by 1 to the transfer counter, then input the transfer clock to SCLK3 after 5 or more cycles of internal clock φ. The transfer interval after each 8-bit data transfer must be 5 or more cycles of internal clock φ after the rising edge of the last bit of the 8-bit data. When selecting an internal synchronous clock, the automatic transfer interval can be specified regardless of the contents of the selected handshake signal. In this case, when the automatic transfer interval setting is valid and SBUSY3 output is used there are the transfer interval before the first data is transmitted/received, as well as after the last data is transmitted/received just as in the automatic transfer serial I/O mode. When using S STB3 output, this transfer interval become 2 cycles longer than the value set for each 8-bit data. In addition, when using the combined output of SBUSY3 and SSTB3, the transfer interval after completion of transmission/receipt of the last data become 2 cycles longer than the set value. When selecting an external synchronous clock, the automatic transfer interval cannot be specified. Regardless of internal or external synchronous clock, the automatic transfer data pointer is decremented after each 8-bit data is received and then written to the auto-transfer RAM. The transfer counter is decremented with the transfer clock. The serial transfer status flag is set to “1” by writing to the transfer counter which triggers the start of transmission. After the last data is written to the automatic transfer RAM, the serial transfer status flag is set to “0” and a serial I/O3 interrupt request occurs simultaneously. The write values of the automatic transfer data pointer set bits and the automatic transfer interval set bits are kept in the latch. As a transfer counter write occurs, each value is transferred to its corresponding decrement counter. If the last data does not fill 8 bits, the receive data stored in the serial I/O3 automatic transfer RAM become the closest MSB odd bit if the transfer direction select bit is set to LSB first, or the closest LSB odd bit if the transfer direction select bit is set to MSB first. Automatic transfer RAM 2FF16 Automatic transfer data pointer 25216 5216 25116 Transfer counter 25016 0416 24F16 24E16 20016 SIN3 SOUT3 Serial I/O3 register Fig. 38 Automatic transfer serial I/O operation 44 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Automatic transfer RAM (before transfer) Automatic transfer data pointer 1516 MSB Transfer counter Transmit bit string Start bit LSB 21516 0 0 1 1 0 1 0 1 21416 – – 1 0 1 0 1 1 SOUT3 0D 16 1 0 1 0 1 1 0 0 1 1 0 1 0 1 Odd bit LSB first Automatic transfer RAM (after transfer) Receive bit string Start bit MSB 1 0 1 0 0 1 1 0 0 1 0 1 1 0 SIN3 LSB first Odd bit LSB 21516 1 0 0 1 0 1 1 0 21416 1 0 1 0 0 1 – – *according to automatic transfer interval setting SCLK3 (Internal synchronous clock selected) SOUT3 SIN3 Serial transfer status flag Transfer counter D16 C16 B16 A16 9 8 7 6 5 4 3 2 1 0 Transfer counter write Automatic transfer data pointer 1516 1416 Automatic transfer RAM Serial I/O3 register Serial I/O3 register Automatic transfer RAM * When using the S STB3 output signal, this become 2 transfer clock cycles longer than the set interval. Fig. 39 Arbitrary bit serial I/O operation 45 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Handshake Signal ● SSTB3 output signal The SSTB3 output is a signal to inform an end of transmission/reception to the serial transfer destination . The S STB3 output signal can be used only when the internal synchronous clock is selected. In the initial status, that is, in the status in which the serial I/O initialization bit (b4) is reset to “0”, the SSTB3 output goes to “L”, and the SSTB3 output goes to “H”. At the end of transmit/receive operation, when the data of the serial I/O3 register is all output from SOUT3 , pulses which are the SSTB3 output of “H” and the S STB3 output of “L” are output in the period of 1 cycle of the transfer clock. After that, each pulse is returned to the initial status in which S STB3 output goes to “L” and the SSTB3 output goes to “H”. Furthermore, after 1 cycle, the serial transfer status flag (b5) is reset to “0”. In the automatic transfer serial I/O mode, whether making the SSTB3 output active at an end of each 1-byte data or after completion of transfer of all data can be selected by the SBUSY3 output • SSTB3 output function selection bit (b4 of address 001516 ) of serial I/O3 control register 2. SSTB3 SCLK3 SBUSY3 SCLK3 SOUT3 Fig. 41 SBUSY3 input operation (internal synchronous clock) When the external synchronous clock is selected, input an “H” level signal into the SBUSY3 input and an “L” level signal into the SBUSY3 input in the initial status in which transfer is stopped. At this time, the transfer clocks to be input in SCLK3 become invalid. During serial transfer, the transfer clocks to be input in SCLK3 become valid, enabling a transmit/receive operation, while an “L” level signal is input into the SBUSY3 input and an “H” level signal is input into the SBUSY3 input. When changing the input values in to the S BUSY3 input and the SBUSY3 input in these operations, change them while the SCLK3 input is in a high state. When the high impedance of the SOUT3 output is selected by the SOUT3 output control bit (b6), the S OUT3 output becomes active, enabling serial transfer by inputting a transfer clock to SCLK3, while an “L” level signal is input into the SBUSY3 input and an “H” level signal is input into the SBUSY3 input. SOUT3 SBUSY3 Fig. 40 SSTB3 output operation ● SBUSY3 input signal The SBUSY3 input is a signal which receives a request for a stop of transmission/reception from the serial transfer destination. When the internal synchronous clock is selected, input an “H” level signal into the S BUSY3 input and an “L” level signal into the SBUSY3 input in the initial status in which transfer is stopped. When starting a transmit/receive operation, input an “L” level signal into the S BUSY3 input and an “H” level signal into the SBUSY3 input in the period of 1.5 cycles or more of the transfer clock. Then, transfer clocks are output from the SCLK3 output. When an “H” level signal is input into the S BUSY3 input and an “L” level signal into the SBUSY3 input after a transmit/receive operation is started, this transmit/receive operation are not stopped immediately and the transfer clocks from the S CLK3 output are not stopped until the specified number of bits is transmitted and received. The handshake unit of the 8-bit serial I/O is 8 bits and that of the arbitrary bit serial I/O is the bit number adding “1” to the set value to the transfer counter, and that of the automatic transfer serial I/O is 8 bits. 46 SCLK3 Invalid SOUT3 (Output high-impedance) Fig. 42 SBUSY3 input operation (external synchronous clock) ● S BUSY3 output signal The SBUSY3 output is a signal which requests a stop of transmission/reception to the serial transfer destination. In the automatic transfer serial I/O mode, regardless of the internal or external synchronous clock, whether making the SBUSY3 output active at transfer of each 1-byte data or during transfer of all data can be selected by the S BUSY3 output • S STB3 output function selection bit (b4). In the initial status, that is, the status in which the serial I/O initialization bit (b4) is reset to “0”, the SBUSY3 output goes to “H” and the SBUSY3 output goes to “L”. MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic transfer serial I/O mode (S BUSY3 output function outputs in 1-byte units), the SBUSY3 output goes to “L” and the SBUSY3 output goes to “H” before 0.5 cycle (transfer clock) of the timing at which the transfer clock from the SCLK3 output goes to “L” at a start of transmit/receive operation. In the automatic transfer serial I/O mode (the SBUSY3 output function outputs all transfer data), the SBUSY3 output goes to “L” and the SBUSY3 output goes to “H” when the first transmit data is written into the serial I/O3 register (address 0013 16). When the external synchronous clock is selected, the SBUSY3 out- put goes to “L” and the S BUSY3 output goes to “H” when transmit data is written into the serial I/O3 register to start a transmit operation, regardless of the serial I/O transfer mode. At termination of transmit/receive operation, the S BUSY3 output returns to “H” and the SBUSY3 output returns to “L”, the initial status, when the serial transfer status flag is set to “0”, regardless of selecting the internal or external synchronous clock. Furthermore, in the automatic transfer serial I/O mode (S BUSY3 output function outputs in 1-byte units), the S BUSY3 output goes to “H” and the SBUSY3 output goes to “L” each time 1-byte of receive data is written into the automatic transfer RAM. SBUSY3 SBUSY3 Serial transfer status flag Serial transfer status flag SCLK3 SCLK3 SOUT3 Write to Serial I/O3 register Fig. 43 SBUSY3 output operation (internal synchronous clock, 8-bits serial I/O) Fig. 44 SBUSY3 output operation (external synchronous clock, 8-bits serial I/O) Automatic transfer interval SCLK3 Serial I/O3 register →Automatic transfer RAM Automatic transfer RAM →Serial I/O3 register SBUSY3 Serial transfer status flag SOUT3 Fig. 45 SBUSY3 output operation in automatic transfer serial I/O mode (internal synchronous clock, S BUSY3 output function outputs each 1-byte) 47 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● SRDY3 output signal The SRDY3 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. In the initial status, that is, when the serial I/O initialization bit (b4) is reset to “0”, the SRDY3 output goes to “L” and the S RDY3 output goes to “H”. After transmitted data is stored in the serial I/O3 register (address 001316 ) and a transmit/receive operation becomes ready, the SRDY3 output goes to “H” and the SRDY3 output goes to “L”. When a transmit/receive operation is started and the transfer clock goes to “L”, the SRDY3 output goes to “L” and the SRDY3 output goes to “H”. ● SRDY3 input signal The SRDY3 input signal becomes valid only when the SRDY3 input and the SBUSY3 output are used. The SRDY3 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. When the internal synchronous clock is selected, input a low level signal into the SRDY3 input and a high level signal into the S RDY3 input in the initial status in which the transfer is stopped. Transfer interval When an “H” level signal is input into the S RDY3 input and an “L” level signal is input into the S RDY3 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK3 output and a transmit/receive operation is started. After the transmit/receive operation is started and an “L” level signal is input into the SRDY3 input and an “H” level signal into the SRDY3 input, this operation cannot be immediately stopped. After the specified number of bits are transmitted and received, the transfer clocks from the SCLK3 output is stopped. The handshake unit of the 8-bit serial I/O and that of the automatic transfer serial I/O are of 8 bits. That of the arbitrary bit serial I/O is the bit number adding “1” to the set value to the transfer counter. When the external synchronous clock is selected, the SRDY3 input becomes one of the triggers to output the SBUSY3 signal. To start a transmit/receive operation (S BUSY3 output to “L”, S BUSY3 output to “H”), input an “H” level signal into the SRDY3 input and an “L” level signal into the S RDY3 input, and also write transmit data into the serial I/O3 register. Automatic transfer interval Transfer interval SCLK3 Serial I/O3 register → Automatic transfer RAM Automatic transfer RAM → Serial I/O3 register SBUSY3 Serial transfer status flag SOUT3 Fig. 46 SBUSY3 output operation in arbitrary bit serial I/O mode (internal synchronous clock) SRDY3 SRDY3 SCLK3 SCLK3 Write to serial I/O3 register SOUT3 Fig. 47 SRDY3 Output Operation 48 Fig. 48 SRDY3 Input Operation (internal synchronous clock) MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A: SCLK3 SCLK3 SRDY3 SRDY3 SBUSY3 Write to serial I/O3 register SRDY3 SBUSY3 SBUSY3 A: SCLK3 B: Internal synchronous clock selection External synchronous clock selection B: Write to serial I/O3 register Fig. 49 Handshake operation at serial I/O3 mutual connecting (1) A: SCLK3 SCLK3 SRDY3 SRDY3 SBUSY3 Write to serial I/O3 register SRDY3 SBUSY3 SBUSY3 A: Internal synchronous clock selection SCLK3 B: External synchronous clock selection B: Write to serial I/O3 register Fig. 50 Handshake operation at serial I/O3 mutual connecting (2) 49 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D ATA L I N K L AY E R C O M M U N I C AT I O N CONTROL CIRCUIT The 3874 Group has a built-in data link layer communication control circuit. This data link layer communication control circuit is applicable for multi-master serial bus communication control used only with data lines through an external driver/receiver. The data link layer communication control circuit consists of following. •Communication mode register (address 002A16 ) •Transmit control register (address 002B16 ) •Transmit status register (address 002C16) •Receive control register (address 002D16 ) •Receive status register (address 002E16 ) •Bus interrupt factor determination control register (address 002F16) •Control field select register (address 003016) •Control field data register (address 003116 ) •Transmit/Receive FIFO (address 003216) This function is realized by hardware and firmware so that communication protocol can be partially modified according to the user’s specification. The following are the standard communication rate and functions which the data link layer communication control circuit can perform. •Communication rate: Approx. 40 kbps The communication rate depends on frame or bit protocol. •Synchronous method: Half-duplex asynchronous •Modification method: PWM method, NRZ, etc. •Communication functions: ➀Bus arbitration (CSMA/CD method, etc.) ➁Error detection (parity, acknowledge, CRC, etc.) ➂Frame, data retry The transmission signal is output from the BUS OUT pin and input to the BUS IN pin. Detailed specifications for communication protocol, bit assignment, function, etc. of each register are defined according to each communication protocol specification confirmation. 50 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data Bus Bus interrupt source control signal Bus interrupt source determination control register (address 002F 16) Control field selection register (address 0030 16) To interrupt request register Local data bus Local address Control field register (address 0031 16 ) * Register crowd 14 bytes Local address (addresses 00 16 to 0D 16) Communication mode register (address 002A 16) Bus interrupt request signal Transmit control register (address 002B 16) Transmit status register (address 002C 16) Receive control register (address 002D 16) Receive status register (address 002E 16) Transmit/Receive FIFO (address 0032 16) Transmit FIFO (8 bytes) Receive FIFO (16 bytes) BUS IN/BUS OUT input/output control circuit * Each register name is defined according to the communication protocol specifications. BUS IN BUS OUT Fig. 51 Data link layer communication control circuit block example 51 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Communication Mode Register (BUSM)] 002A16 The communication mode register (address 002A16) has 6 bits and consists of all the control bits for the communication mode. b7 b0 Communication mode register (BUSM : address 002A 16) Arbitrary bits: defined according to each communication protocol specification confirmation. Not used (Always write “00” to these bits.) Fig. 52 Structure of communication mode register 52 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Transmit Control Register (TXDCON)] 002B16 The transmit control register (address 002B16) has 7 bits and consists of the transmit control and transmit status flags. b7 [Transmit Status Register (TXDSTS)] 002C16 The transmit status register (address 002C16) has 8 bits and consists of the transmit error flag and transmit interrupt request flag. b0 Transmit control register (TXDCON : address 002B 16) Arbitrary bits: defined according to each communication protocol specification confirmation. Not used (return “0” when read) Arbitrary bits: defined according to each communication protocol specification confirmation. Fig. 53 Structure of transmit control register b7 b0 Transmit status register (TXDSTS : address 002C 16) Arbitrary bits: defined according to each communication protocol specification confirmation. Transmit bus Interrupt source 1 request bit Transmit bus Interrupt source 2 request bit Arbitrary bits: defined according to each communication protocol specification confirmation. Transmit bus Interrupt source 3 request bit Note: Bits 0 to 3, bit 5, and bit 7 can be cleared only by software. When a transmit bus interrupt source request bit is “1,” an interrupt request occurs. The name and function of each transmit bus interrupt source is defined according to the communication protocol specification confirmation. Fig. 54 Structure of transmit status register 53 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Receive control register (RXDCON)] 002D 16 [Receive status register (RXDSTS)] 002E16 The receive control register has 7 bits and consists of the receive control and receive status flags. The receive status register has 8 bits and consists of the receive error flag and receive interrupt request flags. b7 b0 Receive control register (RXDCON : address 002D 16) Arbitrary bits: defined according to each communication protocol specification confirmation. Not used (return “0” when read) Arbitrary bits: defined according to each communication protocol specification confirmation. Fig. 55 Structure of receive control register b7 b0 Receive status register (RXDSTS : address 002E 16) Arbitrary bits: defined according to each communication protocol specification confirmation. Receive bus interrupt source 1 request bit Receive bus interrupt source 2 request bit Arbitrary bits: defined according to each communication protocol specification confirmation. Receive bus interrupt source 3 request bit When a receive bus interrupt source request bit is “1”, an interrupt request occurs. The name and function of each receive bus interrupt source is defined according to the communication protocol specification confirmation. Fig. 56 Structure of receive status register 54 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Control field selection register (CFSEL)] 003016 [Control field register (CF)] 003116 The control field data select the control field selection register (address 0030 16) value as the pointer. The data can be confirmed b7 and changed by a read/write of the control field register (address 003016 ). For example, when reading/writing the local address “0016,” the control field selection register is set to “0016 ” and the control field register is read/written. b0 Control field selection register (CFSEL : address 0030 16) Control field selection bits b3 b2 b1 b0 0 0 0 0 : 0 0 0 1 : 0 0 1 0 : 0 0 1 1 : 0 1 0 0 : 0 1 0 1 : 0 1 1 0 : Arbitrary bits: defined according to each communication 0 1 1 1 : protocol specification confirmation. 1 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : Disabled 1 1 1 1 : Disabled Not used (write “0” to these bits.) Fig. 57 Structure of control field selection register 55 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Bus interrupt source determination control register (BICOND)] 002F16 the section concerning interrupts for details about priority and vector addresses. The bus interrupt source determination control register (address 002F16) has 6 bits and controls bus-related interrupts. Refer to b7 b0 Bus interrupt source determination control register (BICOND : address 002F 16) Transmit bus interrupt source 1 enable bit Transmit bus interrupt source 2 enable bit Not used (return “0” when read) Transmit bus interrupt source 3 enable bit Receive bus interrupt source 1 enable bit Receive bus interrupt source 2 enable bit Receive bus interrupt source 3 enable bit Not used (return “0” when read) 0: Interrupt disabled 1: Interrupt enabled The name and function of each transmit/receive bus interrupt source is defined according to the communication protocol specification confirmation. Fig. 58 Structure of bus interrupt source determination control register 56 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER [A-D/D-A Conversion Register (AD)] 003516 The A-D/D-A conversion register is a register (at reading) that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. Note that the comparator is constructed linked to a capacitor, so set f(X IN) to at least 500 kHz during A-D conversion. Use a CPU system clock dividing the main clock XIN. b7 b0 [A-D Control Register (ADCON)] 0034 16 A-D control register (ADCON : address 0034 16) The A-D control register controls the A-D/D-A conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. Writing “0” to this bit starts the A-D conversion. When bit 5, which is the AD external trigger valid bit, is set to “1”, this bit enables A-D conversion even by a falling edge of an ADT input. Set “0” (input port) to the direction register corresponding the ADT pin. Bit 6 is the interrupt source selection bit. Writing “0” to this bit, A-D conver ter interrupt request occurs at completion of A-D conversion. Writing “1” to this bit the interrupt request occurs at falling edge of an ADT input. Analog input pin selection bits 000: P60/AN0 001: P61/AN1 010: P62/AN2 011: P63/AN3 100: P64/AN4 101: P65/AN5 110: P66/AN6 111: P67/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed VREF input switch bit 0: OFF 1: ON Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages. AD external trigger valid bit 0: AD external trigger invalid 1: AD external trigger valid Channel Selector Interrupt source selection bit 0: Interrupt request at A-D conversion completed 1: Interrupt request at ADT input falling The channel selector selects one of the input ports P6 7/AN7 to P60/AN0 and inputs it to the comparator. Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D/ D-A conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to “1”. DA output enable bit 0: DA output disabled 1: DA output enabled Fig. 59 Structure of A-D control register Data bus b0 b7 A-D control register P77/ADT 3 ADT/A-D interrupt request A-D control circuit P60/AN0 P62/AN2 P63/AN3 P64/AN4 P65/AN5 Channel selector P61/AN1 Comparator A-D conversion register 8 Resistor ladder P66/AN6 P67/AN7 AVSS VREF Fig. 60 Block diagram of A-D converter 57 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A CONVERTER The 3874 group has an on-chip D-A converter with 8-bit resolution and 1 channel. The D-A conversion is performed by setting the value in the A-D/D-A conversion register. The result of D-A converter is output from DA pin by setting the DA output enable bits to “1”. When using the D-A converter, the corresponding port direction register bit (P8 0/DA) should be set to “0” (input status). The output analog voltage V is determined by the value n (base 10) in the A-D/D-A conversion register as follows: Data bus D-A conversion register (8) R-2R resistor ladder DA output enable bit P80/DA V=VREF ✕ n/256 (n=0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to “0016”, the DA output enable bits are cleared to “0”, and P80 /DA pin becomes high impedance. The DA output is not buffered, so connect an external buffer when driving a low-impedance load. When using D-A converter, set 4.0 V or more to VCC. Fig. 61 Block diagram of D-A converter ■ Note When reading the A-D/D-A conversion register, the A-D conversion result is read, and the set value for D-A conversion is not read. DA output enable bit “0” P80/DA R “1” 2R MSB D-A conversion register “0” 2R R 2R R 2R R 2R R 2R R 2R 2R 2R LSB “1” AV SS VREF Fig. 62 Equivalent connection circuit of D-A converter 58 R MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and a 12-bit watchdog timer H. Watchdog Timer Initial Value Watchdog timer L is set to “FF16 ” and watchdog timer H is set to “FFF16 ” by writing to the watchdog timer control register or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog control register. Regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. Watchdog Timer Operations The watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. An internal reset occurs when watchdog timer H underflows. The reset is released after its release time. After the release, the program is restarted from the reset vector address. Usually, write to the watchdog timer control register by software before an underflow of the watchdog timer H. The watchdog timer does not function if the watchdog timer control register is not written to at least once. When bit 6 of the watchdog timer control register is kept at “0”, the STP instruction is enabled. When that is executed, both the clock and the watchdog timer stop. Count re-starts at the same time as the release of stop mode (Note). The watchdog timer does not stop while a WIT instruction is executed. In addition, the STP instruction is disabled by writing “1” to this bit again. When the STP instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. Once a “1” is written to this bit, it cannot be programmed to “0” again. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is “0”: when X CIN = 32 kHz; 524 s when X IN = 6.4 MHz; 2.6 s Bit 7 of the watchdog timer control register is “1”: when X CIN = 32 kHz; 2 s when X IN = 6.4 MHz; 10 ms Note: The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not underflow during this period. “FF16” is set when watchdog timer control register is written to. XCIN Data bus “0” “10” Main clock division ratio selection bits (Note) XIN “FF16” is set when watchdog timer control register is written to. Watchdog timer L (8) 1/16 “1” “00” “01” “11” Watchdog timer H (12) Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit RESET Internal reset Reset release time wait Note: Either double-speed, high-speed, middle-speed, or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 63 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001E 16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 64 Structure of Watchdog timer control register 59 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 3.0 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC16 (loworder byte). Make sure that the reset input voltage is 0.6 V or less for VCC of 3.0 V. Poweron RESET VCC (Note) Power source voltage 0V Reset input voltage 0V 0.2VCC Note : Reset release voltage ; Vcc=2.5 V RESET VCC Power source voltage detection circuit Fig. 65 Reset circuit example XIN φ RESET Internal reset Reset address from the vector table Address ? Data ? ? ? FFFC FFFD ADL SYNC XIN : 40 to 56 clock cycles Notes 1: The frequency relation of f(X IN) and f(φ) is f(XIN)=8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 66 Reset sequence 60 ADH,ADL ADH MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address Register contents (1) Port P0 Address 000016 0016 (31) Timer Y (low-order) 002216 FF16 (2) Port P0 direction register 000116 0016 (32) Timer Y (high-order) 002316 FF16 (3) Port P1 000216 0016 (33) Timer 1 002416 FF16 (4) Port P1 direction register 000316 0016 (34) Timer 2 002516 0116 (5) Port P2 000416 0016 (35) Timer 3 002616 FF16 (6) Port P2 direction register 000516 0016 (36) Timer X mode register 002716 0016 (7) Port P3 000616 0016 (37) Timer Y mode register 002816 0016 (8) Port P3 direction register 000716 0016 (38) Timer 123 mode register 002916 0016 (9) Port P4 000816 0016 (39) Communication mode register 002A16 0 0 0 0 ✕ ✕ ✕ 0 (10) Port P4 direction register 000916 0016 (40) Transmit control register 002B16 2016 (11) Port P5 000A16 0016 (41) Transmit status register 002C16 0016 (12) Port P5 direction register 000B16 0016 (42) Receive control register 002D16 1016 (13) Port P6 000C16 0016 (43) Receive status register 002E16 0116 (14) Port P6 direction register 000D16 0016 002F16 0016 (15) Port P7 000E16 0016 (44) Bus interrupt source discrimination control register (45) Control field selection register 003016 0016 (16) Port P7 direction register 000F16 0016 (46) PULL UP register 003316 0016 0016 (47) A-D control register 003416 0816 0016 (48) Interrupt source discrimination register 2 003616 0016 (49) Interrupt source discrimination control register 2 (50) Interrupt source discrimination register 1 003716 0016 003816 0016 003916 0016 003A16 0016 001016 (17) Port P8 Register contents (18) Port P8 direction register 001116 (19) Port P9 001216 ✕ 0 0 0 0 0 0 0 (20) Serial I/O3 control register 1 001416 0016 (21) Serial I/O3 control register 2 001516 0016 (22) Serial I/O3 control register 3 001616 0016 (51) Interrupt source discrimination control register 1 (52) Interrupt edge selection register (23) Serial I/O3 automatic transfer data pointer 001716 0016 (53) CPU mode register 003B16 4816 (24) Serial I/O1 status register 001916 8016 (54) Interrupt request register 1 003C16 0016 (25) Serial I/O1 control register 001A16 0016 (55) Interrupt request register 2 003D16 0016 (26) UART control register 001B16 E016 (56) Interrupt control register 1 003E16 0016 (27) Serial I/O2 control register 001D16 0016 (57) Interrupt control register 2 003F16 0016 (28) Watchdog timer control register 001E16 3F16 (58) Processor status register (29) Timer X (low-order) 002016 FF16 (59) Program counter (30) Timer X (high-order) 002116 FF16 (PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕ (PCH) FFFD16 contents (PCL) FFFC16 contents Notes: ✕ : Not fixed Notes: Since the initial values for other than above-mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 67 Internal status at reset 61 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 3874 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and X COUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the X IN oscillation circuit starts oscillating, and XCIN and X COUT pins function as I/O ports. When using the XCIN oscillation circuit, X CIN and X COUT pins’ pullup resistors need to be invarid. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. (2) Double-speed mode The internal clock φ is the frequency of XIN. (3) High-speed mode The internal clock φ is half the frequency of XIN . (4) Low-speed mode The internal clock φ is half the frequency of XCIN . ■ Note When switching the mode between double/middle/high-speed and low-speed, stabilize both X IN and XCIN oscillations. Sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between double/middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN ). It takes the cycle number mentioned below to switch between each mode (machine cycle = cycle of internal clock φ). Double-speed mode→Except double-speed mode 1 to 8 machine cycles High-speed mode→Except high-speed mode 1 to 4 machine cycles Middle-speed mode→Except middle-speed mode 1 machine cycle Low-speed mode→Except low-speed mode 1 to 4 machine cycles can be realized by reducing the drivability between X CIN and XCOUT. At reset or during STP instruction execution this bit is set to “1” and a reduced drivability that has an easy oscillation start is set. The sub-clock XCIN-X COUT oscillating circuit can no directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Oscillation Control (1) Stop mode When the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillators stop. The value set to the timer 1 latch and the timer 2 latch is set to timer 1 and timer 2. Either XIN or X CIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except the timer 3 count source selection bit (b4) are cleared to “0”. Set the interrupt enable bits of timer 1 and timer 2 to the disabled state (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Timer 1 latch and timer 2 latch should be set to proper values for stabilizing oscillation before executing the STP instruction. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. XCIN XCOUT Rf XIN XOUT Rd CCOUT CCIN CIN COUT Fig. 68 Ceramic resonator circuit The 3874 group operates in the previous mode while the mode is switched. (5) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. By clearing furthermore the XCOUT drivability selection bit (b3) of the CPU mode register to “0”, low power consumption operation XCIN XCOUT Rf CCIN XIN Open Rd External oscillation CCOUT circuit VCC VSS Fig. 69 External clock input circuit 62 XOUT MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCOUT XCIN “0” Port XC switch bit “1” 1/16 XOUT XIN Timer 1 count source selection bit Main clock division ratio selection bits (Note) Timer 2 count source selection bit “1” “10” 1/4 1/2 Timer 1 1/2 “0” “00,01,11” “0” Timer 2 “1” Main clock division ratio selection bits (Note) Main clock stop bit “01” Timing φ (internal clock) “00,10” “11” Q S S R STP instruction WIT instruction R Q Q S R STP instruction Reset Interrupt disable flag I Interrupt request Note: When low-speed mode is selected, set port XC switch bit (b4) to “1.” Fig. 70 System clock generating circuit block diagram 63 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset CM7 “0”←→“1” CM 6 “0”←→“1” High-speed mode (φ=3.15 MHz) CM7=0 High-speed mode CM6=0 6.3 MHz selected CM5=0 (X IN oscillating) CM4=1 (32 kHz oscillating) CM3=1 (X COUT drivability High) M C CM 6 → 0” “ ”← “1 Middle-speed mode (φ=788 kHz) CM 7=0 Middle-speed mode CM 6=1 6.3 MHz selected CM 5=0 (X IN oscillating) CM 4=1 (32 kHz oscillating) CM 3=1 (X COUT drivability High) “0”←→“1” “0 4 ”← CM → 7 ”← CM “1 → 4 ” “1 ” “0 CM 7 “0”←→“1” CM 7 CM 4 CM4 ”← CM → 6 ”← CM “1 → 4 ” “1 ” CM 7 “1”←→“0” “0 “0 Double-speed mode (φ=6.3 MHz) CM7=1 Double-speed mode CM6=1 6.3 MHz selected CM5=0 (X IN oscillating) CM4=0 (32 kHz stopped) CM3=1 (X COUT drivability High) “0”←→“1” “0 C ”← M → 7 “1 ” CM 6 “1”←→“0” Middle-speed mode (φ=788 kHz) CM7=0 Middle-speed mode CM6=1 6.3 MHz selected CM5=0 (XIN oscillating) CM4=0 (32 kHz stopped) CM3=1 (XCOUT drivability High) “0”←→“1” “0 C ”← M 0 “1 C → ”← M4 “1 ” → “0 ” CM4 “1”←→“0” High-speed mode (φ=3.15 MHz) CM 7=0 High-speed mode CM 6=0 6.3 MHz selected CM 5=0 (X IN oscillating) CM 4=0 (32 kHz stopped) CM 3=1 (X COUT drivability High) Double-speed mode (φ=6.3 MHz) CM7=1 Double-speed mode CM6=1 6.3 MHz selected CM5=0 (XIN oscillating) CM4=1 (32 kHz oscillating) CM3=1 (XCOUT drivability High) “0”←→“1” CM6 Low-speed mode (φ=16 kHz) CM7=1 Low-speed mode CM6=0 32 kHz selected CM5=0 (X IN oscillating) CM4=1 (32 kHz oscillating) CM3=1 (X COUT drivability High) “0 CM ”← 6 “1 ” CM6 “0”←→“1” CM7 “1”←→“0” “1 CM3 “0”←→“1” CM7 ”← CM “0 C → 7 ”← M “ “0 C → 6 0” ”← M “1 → 3 ” “1 ” ” “0”←→“1” 7 ”← CM3 M 1 C →“ Low-speed mode ( φ=16 kHz) CM7=1 Low-speed mode CM6=0 32 kHz selected CM5=0 (XIN oscillating) CM4=1 (32 kHz oscillating) CM3=0 (XCOUT drivability Low) “0 “1”←→“0” “0”←→“1” b7 b0 “1 ” Low-speed mode ( φ=16 kHz) CM 7=1 Low consumption mode CM 6=0 32 kHz selected CM 5=1 (X IN stopped) CM 4=1 (32 kHz oscillating) CM 3=0 (X COUT drivability Low) “1 5 ”← CM → “0 “0 C ”← M →3 ”← CM “1 →5 ” “0 ” CPU mode register (CPUM: address 003B 16) CM 3 : XCOUT drivability selection bit 0 : Low 1 : High CM 4 : Port Xc switch bit 0 : I/O port function 1 : XCIN-XCOUT oscillating function CM 5 : Main clock (X IN- XOUT) stop bit 0 : Oscillating 1 : Stopped CM 7,CM6 : Main clock division ratio selection bits CM 7 CM6 0 0 : φ=f(X IN)/2 (high-speed mode) 0 1 : φ=f(X IN)/8 (middle-speed mode) 1 0 : φ=f(X CIN)/2 (low-speed mode) (double-speed mode) 1 1 : φ=f(X IN) Notes 1: Switch the mode by the arrows shown between the mode blocks. (Do not switch between the modes directly without an arrow.) 2: All modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer operates in the wait mode. 4: When the stop mode is ended, wait time is generated automatically by connecting timer 1 and timer 2. 5: The example assumes that 6.3 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal clock. 6: We recommend that X COUT drivability selection bit is set to “1” (high) because reliance of oscillation stability is improved. Fig. 71 State transitions of system clock 64 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial I/O1 Interrupt Source Determination • Use LDM, STA, etc., instructions to clear interrupt request bits assigned to the interrupt source determination register 1, the interrupt source determination register 2, the transmit status register, or the receive status register. (Do not use read-modifywrite instructions such as CLB, SEB, etc. Use the LDM or STA instruction to clear these bits.) • Request bits of interrupt source determination registers are not automatically cleared when an interrupt occurs. After an interrupt source has been determined, and before execution of the RTI or CLI instruction, the user must clear the bit by program. (Use the LDM or STA instruction to clear.) • The interrupt assigned to the interrupt source determination registers occur 1 instruction execution later than a normal interrupt. The maximum timing is 16 machine cycles in the MUL, DIV instructions. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. • In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the S RDY output enable bit to “1”. Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. • In order to stop a transmit, set the transmit enable bit to “0” (transmit disable). Do not set only the serial I/O1 enable bit to “0”. • A receive operation can be stopped by either setting the receive enable bit to “0” or the serial I/O1 enable bit to “0”. • To stop a transmit when transferring in clock synchronous serial I/O mode, set both the transmit enable bit and the receive enable bit to “0” at the same time. • To set the serial I/O1 control register again, first set the transmit enable/receive enable bits to “0”. Next, reset the transmit/receive circuits, and, finally, reset the serial I/O1 control register. • Note when confirming the transmit shift register completion flag and controlling the data transmit after writing a transmit data to the transmit buffer. There is a delay of 0.5 to 1.5 shift clock cycles while the transmit shift register completion flag goes from “1” to “0”. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. 65 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O3 • When writing “1” to the serial I/O initialization bit of the serial I/O3 control register 1, serial I/O3 is enabled, but each register is not initialized. Set the value of each register by program. • A serial I/O3 interrupt request occurs when “0” is written to the serial I/O initialization bit during an operation in automatic transfer serial I/O mode. Disable the interrupt enable bit as necessary by program. A-D Converter/D-A Converter • The A-D/D-A conversion register functions as an A-D conversion register during a read and a D-A conversion during a write. Accordingly, the D-A conversion register set value cannot be read out. • The comparator for A-D converter uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion. • If switching the mode between low-speed and double-speed, switch the mode to middle/high-speed first, and then switch the mode to double-speed by program. Do not switch the mode from low-speed to double-speed directly. 1 to 4 machine cycles are required for switching from low-speed mode to other mode. Insert “clock switch timing wait” for switching the mode to middle/high-speed, and then switch the mode to double-speed. Table 8 lists the recommended transition process for system clock switch. Figure 72 shows the program example. Table 8 Clock switch combination Recommended transition process Low-speed→High-speed Low-speed→Middle-speed Double-speed→High-speed Double-speed→Middle-speed Double-speed→Low-speed Middle-speed→High-speed Middle-speed→Middle-speed Middle-speed→Low-speed High-speed→Double-speed High-speed→MIddle-speed High-speed→Low-speed Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency. Data Link Layer Communication Control • The data link layer communication control circuit stops after a reset. To restart or change modes, write “00XXXXX12 ” to the communication mode register. Note that bits 4 and 5 are readonly bits. • The P7 5/BUSOUT pin operates as a general-purpose pin after release from reset. As a general-purpose port, its input/output can be switched by the direction register. Clock Changes • Use the LDM, STA, etc. instructions to modify the division ratio of internal system clock φ. (Do not use read-modify-write instructions such as CLB, SEB, etc.) • Do not modify the division ratio of the internal system clock until the mode has been changed. For details concerning the number of cycles necessary to change modes, refer to the clock section in the explanation of about function blocks. • Use the LDM, STA, etc., instructions to clear interrupt request bits assigned to the interrupt source determination register 1, the interrupt source determination register 2, the transmit status register, or the receive status register. (Do not use read-modifywrite instructions such as CLB, SEB, etc.) • Before executing the CLI or RTI instruction during an interrupt processing routine, use the LDM or STA instruction to clear the interrupt request bits of interrupt source determination registers which have completed the interrupt processing. 66 Low-speed mode → Middle/High-speed mode → Double-speed mode switch LDM xx, CPUM •••Low-speed mode → Middle/High-speed mode switch NOP Clock switch timing wait NOP (1 to 4 machine cycles are required for switching mode.) LDM yy, CPUM •••Switch mode to double-speed Note: CPUM = CPU mode register (address 003B16) Fig. 72 Program example MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 73 is recommended to verify programming. DATA R E QU I R E D F O R RO M W R I T I N G ORDERS The following are necessary when ordering a ROM writing: 1.ROM Writing Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) Programming with PROM programmer Screening (Caution) (150 °C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Fig. 73 Programming and testing of One Time PROM version 67 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS Table 9 Absolute maximum ratings (extended operating temperature version and automotive version) Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10 –P17, P20–P27, P3 0–P37, P40–P47, P50 –P57, P60–P67, P7 0–P77, P80–P87, VREF Input voltage RESET, XIN Input voltage P97 Output voltage P00–P07, P10 –P17, P20–P27, P3 0–P37, P40–P47, P50 –P57, P60–P67, P7 0–P77, P80–P87, XOUT Power dissipation Operating temperature Storage temperature Conditions All voltages are based on Vss. Output transistors are cut off. Ta = 25°C Ratings –0.3 to 7.0 Unit V –0.3 to Vcc +0.3 V –0.3 to Vcc +0.3 V –0.3 to Vcc +0.3 V –0.3 to Vcc +0.3 V 500 mW °C °C –40 to 85 –60 to 150 Table 10 Recommended operating conditions (extended operating temperature version and automotive version, Vcc = 3.0 to 5.5 V, Ta = –40 to 85°C, unless otherwise noted) Symbol VCC VSS VREF AVSS VIA Parameter At operating data link layer communication control circuit Double-speed mode Power source High-speed mode voltage Middle-speed mode Low-speed mode Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN0 to AN 7 Power source voltage Min. Typ. Max. 4.0 5.0 5.5 5.5 5.0 4.0 5.5 5.0 4.0 5.5 5.0 3.0 5.5 5.0 3.0 0 VCC 2.0 VCC 3.0 0 VCC AVSS Unit V V V V V V V V V V VIH “H” input voltage P00–P07, P1 0–P17, P20–P27 , P30–P37, P40 –P47, P50–P57 , P60–P67, P7 0–P77, P80–P87 , P97 0.8VCC VCC V VIH “H” input voltage RESET, XIN 0.8VCC VCC V VIL “L” input voltage P00–P07, P1 0–P17, P20–P27 , P30–P37, P40 –P47, P50–P57 , P60–P67, P7 0–P77, P80–P87 , P97 0 0.2V CC V 0 0 0.2V CC 0.16V CC V V VIL VIL 68 “L” input voltage RESET “L” input voltage XIN MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 11 Recommended operating conditions (1) (extended operating temperature version and automotive version, Vcc = 3.0 to 5.5 V, Ta = –40 to 85°C, unless otherwise noted) Symbol Parameter Min. Limits Typ. Max. Unit ΣI OH(peak) “H” total peak output current (Note 1) P00–P07, P10 –P17, P20–P27, P3 0–P37, P80–P87 –80 mA ΣI OH(peak) “H” total peak output current P40–P47, P50 –P57, P60–P67, P7 0–P77 –80 mA ΣI OL(peak) “L” total peak output current P00–P07, P10 –P17, P20–P27, P3 0–P37, P80–P87 80 mA ΣI OL(peak) “L” total peak output current P40–P47, P50 –P57, P60–P67, P7 0–P77 80 mA ΣI OH(avg) “H” total average output current (Note 1) P00–P07, P10 –P17, P20–P27, P3 0–P37, P80–P87 –40 mA ΣI OH(avg) “H” total average output current P40–P47, P50 –P57, P60–P67, P7 0–P77 –40 mA ΣI OL(avg) “L” total average output current P00–P07, P10 –P17, P20–P27, P3 0–P37, P80–P87 40 mA ΣI OL(avg) “L” total average output current P40–P47, P50 –P57, P60–P67, P7 0–P77 40 mA I OH(peak) “H” peak output current (Note 2) P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67, P70–P77 , P80–P87 –10 mA I OL(peak) “L” peak output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67, P70–P77 , P80–P87 10 mA I OH(avg) “H” average output current (Note 3) P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67, P70–P77 , P80–P87 –5.0 mA I OL(avg) “L” average output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67, P70–P77 , P80–P87 5.0 mA f(CNTR0 ) f(CNTR1 ) Timer X, timer Y input oscillation frequency (at duty cycle of 50%) 2.5 MHz f(XIN) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Notes 4, 5) 6.4 50 MHz kHz f(XCIN ) 32.768 Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), I OH(avg) in an average value measured over 100 ms. 4: Choose an external oscillator which ensures no warps in the oscillation waveform as well as sufficient amplitude for the main clock oscillation circuit. Use according to the manufacturer’s recommended conditions. Table 12 Recommended operating conditions (2) (when ROM/PROM size is 60 Kbytes) (Vcc = 3.0 to 5.5 V, Ta = –40 to 85°C, unless otherwise noted) Symbol f(XIN) Parameter Main clock input oscillation frequency High-speed mode/Middle-speed mode Double-speed mode (4.0 ≤ VCC < 4.5V) Double-speed mode (4.5 ≤ VCC ≤ 5.5V) Min. Limits Typ. Max. 6.4 2.8VCC–6.2 6.4 Unit MHz MHz MHz Note 5: When using the microcomputer in the low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN ) < f(XIN)/3. 69 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 13 Electrical characteristics (extended operating temperature version and automotive version, Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –40 to 85°C, unless otherwise noted) Symbol VOH VOL Parameter “H” output voltage P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47, P50–P57 , P60–P67, P80 –P87 (Note) “L” output voltage P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47, P50–P57 , P60–P67, P70 –P77, P80–P87 VT+ –VT– Hysteresis INT0–INT 5, ADT, CNTR0, CNTR 1 VT+ –VT– Hysteresis RXD, SCLK1 , SIN2, SCLK2 , P20–P27 VT+–VT– Hysteresis I IH “H” input current P00–P07, P10 –P17, P20–P27 , P30–P37, P40–P47, P50 –P57, P60–P67 , P70–P77, P80–P87 I IH I IH I IH Test conditions I OH = –10 mA VCC = 4.0–5.5 V I OH = –1 mA VCC = 3.0–5.5 V I OL = 10 mA VCC = 4.0–5.5 V I OL = 1.0 mA VCC = 3.0–5.5 V Min. P97 “H” input current “H” input current RESET XIN Max. Unit VCC–2.0 V VCC–1.0 V Valid hysteresis only when these pins is used as the function RESET “H” input current Limits Typ. 2.0 V 1.0 V 0.5 V 0.5 V 0.5 V VI = VCC 5.0 µA VI = VCC VI = VCC VI = VCC 5.0 5.0 µA µA µA 4.0 I IL “L” input current P00–P07 , P10–P17, P20 –P27, P30–P37 , P40–P47 , P50–P57, P60 –P67, P70–P77 , P80–P87 VI = VSS –5.0 µA I IL I IL I IL “L” input current P97 “L” input current RESET “L” input current XIN VI = VSS VI = VSS VI = VSS –5.0 –5.0 µA µA µA VRAM RAM hold voltage When clock stopped 5.5 V –4.0 2.0 Note: When P45 /TxD, P71/SOUT2 , and P7 2/S CLK2 are CMOS output states (when not P-channel output disable states) 70 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 14 Electrical characteristics (extended operating temperature version and automotive version, Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –40 to 85°C, unless otherwise noted) Symbol I CC Parameter Power source current Test conditions Double-speed mode, at operating data link layer communication control circuit f(XIN) = 6.29 MHz f(XCIN) = 32 kHz Output transistors “off” During A-D conversion Double-speed mode, at stopping data link layer communication control circuit f(XIN) = 6.29 MHz f(XCIN) = 32 kHz Output transistors “off” During A-D conversion Double-speed mode, at stopping data link layer communication control circuit f(XIN) = 6.29 MHz (in WIT state) f(XCIN) = 32 kHz Output transistors “off” During A-D conversion High-speed mode, at operating data link layer communication control circuit f(XIN) = 6.29 MHz f(XCIN) = 32 kHz Output transistors “off” During A-D conversion High-speed mode, at stopping data link layer communication control circuit f(XIN) = 6.29 MHz f(XCIN) = 32 kHz Output transistors “off” During A-D conversion High-speed mode, at stopping data link layer communication control circuit f(XIN) = 6.29 MHz (in WIT state) f(XCIN) = 32 kHz Output transistors “off” During A-D conversion Low-speed mode (VCC = 3.0 V) f(XIN) = stopped f(XCIN) = 32 kHz Low power dissipation mode (CM 5 = 0) Output transistors “off” Low-speed mode (VCC = 3.0 V) f(XIN) = stopped f(XCIN) = 32 kHz (in WIT state) Low power dissipation mode (CM5 = 0) Output transistors “off” Ta = 25°C All oscillation stopped (Note) (in STP state) Ta = 85°C Output transistors “off” (Note) Min. Limits Typ. Max. 18.0 24.0 mA 12.0 18.0 mA 2.0 3.5 mA 12.0 19.0 mA 8.0 12.0 mA 2.0 3.5 mA 60 200 µA 20 40 µA 0.1 1.0 µA 10 µA Unit Note: The A-D conversion is inactive. (The A–D conversion complete.) VREF current is not included. 71 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 15 A-D converter characteristics (extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –40 to 85°C, unless otherwise noted) Symbol Parameter – – Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current Analog port input current t CONV RLADDER I VREF I I(AD) Test conditions Min. Limits Typ. ±1 VREF = 5.0 V 12 50 35 150 0.5 Max. 8 ±2.5 50 100 200 5.0 Unit Bits LSB tc(φ) kΩ µA µA Table 16 D-A converter characteristics (extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –40 to 85°C, unless otherwise noted) Symbol – – tsu RO I VREF 72 Parameter Resolution Absolute accuracy Setting time Output resistor Reference power source input current Test conditions Min. 1 Limits Typ. 2.5 Max. 8 1.0 3.0 4.0 3.2 Unit Bits % µs kΩ mA MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS Table 17 Timing requirements (extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted) Symbol t W(RESET) t C(X IN) t WH (XIN) t WL (XIN) t C(CNTR) t WH (CNTR) t WH (INT) t WL(CNTR) t WL (INT) t C(S CLK1) t C(S CLK2) t C(S CLK3) t WH (SCLK1 ) t WH (SCLK2 ) t WH (SCLK3 ) t WL (SCLK1) t WL (SCLK2) t WL (SCLK3) t su(Rx D-SCLK1) t su(SIN2-S CLK2) t su(RIN3-S CLK3) t h(S CLK1-Rx D) t h(S CLK2-S IN2) t h(S CLK3-S IN3) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width INT0 to INT5 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT5 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O3 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O3 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O3 clock input “L” pulse width Serial I/O1 input setup time Serial I/O2 input setup time Serial I/O3 input setup time Serial I/O1 input hold time Serial I/O2 input hold time Serial I/O3 input hold time Min. 2 159 63 63 200 80 80 80 80 800 1000 1000 370 400 400 370 400 400 220 200 200 100 200 200 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When bit 6 of address 001A 16 is “1” (clock synchronous). Divide this value by four when bit 6 of address 001A 16 is “0” (UART). 73 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 18 Switching characteristics (extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted) Parameter Symbol tWH (SCLK1) tWH (SCLK2) tWH (SCLK3) tWL (S CLK1) tWL (S CLK2) tWL (S CLK3) td (S CLK1-T XD) td (S CLK2-SOUT2) td (S CLK3-SOUT3) tV (SCLK1 -TXD) tV (SCLK2 -SOUT2) tV (SCLK3 -SOUT3) tr (S CLK1) tf (SCLK1 ) tr (S CLK2) tf (SCLK2 ) tr (S CLK3) tf (SCLK3 ) tr (CMOS) tf (CMOS) Notes 1: 2: 3: 4: 5: 6: 74 Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width (Note 1) Serial I/O3 clock output “H” pulse width (Note 5) Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width (Note 1) Serial I/O3 clock output “L” pulse width (Note 5) Serial I/O1 output delay time (Note 3) Serial I/O2 output delay time (Notes 1, 2) Serial I/O3 output delay time (Notes 5, 6) Serial I/O1 output valid time (Note 3) Serial I/O2 output valid time (Notes 1, 2) Serial I/O3 output valid time (Notes 5, 6) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time (Note 1) Serial I/O2 clock output falling time (Note 1) Serial I/O3 clock output rising time (Note 5) Serial I/O3 clock output falling time (Note 5) CMOS output rising time (Note 4) CMOS output falling time (Note 4) When P72 /SCLK2 is CMOS output. When P71 /SOUT2 is CMOS output. When P45/TXD is CMOS output. The XOUT pin is excluded. When P84 /SCLK3 is CMOS output. When P82 /SOUT3 is CMOS output. Limits Min. Typ. Max. t C(S CLK1)/2–30 t C(S CLK2)/2–30 t C(S CLK3)/2–30 t C(S CLK1)/2–30 t C(S CLK2)/2–30 t C(S CLK3)/2–30 140 140 140 –30 0 0 10 10 10 10 10 10 10 10 30 30 30 30 30 30 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Measurement output pin 100 pF CMOS output Fig. 74 Circuit for measuring output switching characteristics 75 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing diagram tC(CNTR) tWL(CNTR) tWH(CNTR) 0.8VCC 0.2VCC tWL(INT) tWH(INT) 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) XIN SCLK1 SCLK2 SCLK3 0.8VCC 0.16VCC tC(SCLK1), tC(SCLK2), tC(SCLK3) tf tWL(SCLK1), tWL(SCLK2), tWL(SCLK3) tr tWH(SCLK1), tWH(SCLK2), tWH(SCLK3) 0.8VCC 0.2VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2), tsu(SIN3-SCLK3) RXD SIN2 SIN3 th(SCLK1-RXD), th(SCLK2-SIN2), th(SCLK3-SIN3) 0.8VCC 0.2VCC td(SCLK1-TXD),td(SCLK2- SOUT2),td(SCLK3- SOUT3) TXD SOUT2 SOUT3 Fig. 75 Timing diagram (in single-chip mode) 76 tv(SCLK1-TXD), tv(SCLK2-SOUT2), tv(SCLK3-SOUT3) MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-76B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) Sub ROM number of data link layer communication control circuit EPROM type (indicate the type used) 27512 EPROM address 000016 000F16 001016 001F16 002016 C07F16 C08016 FFFD16 FFFE 16 FFFF16 Product name ASCII code : ‘M38747M4T–’ Sub ROM number ASCII code Data ROM 16K-130 bytes 27101 EPROM address 000016 000F16 001016 001F16 002016 C07F16 C08016 Product name ASCII code : ‘M38747M4T–’ Sub ROM number ASCII code Data ROM 16K-130 bytes FFFD16 FFFE 16 1FFFF16 In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16 . The reset vector is stored in addresses FFFC16 and FFFD16 . (1) Set the data in the unused area (the shaded area of the diagram) to “FF 16”. (2) The ASCII codes of the product name “M38747M4T–” must be entered in addresses 000016 to 000916. And set the data “FF16” in addresses 000A16 to 000F16. ASCII codes and addresses are listed to the next page. (3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the next page at writing. (1/3) 77 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-76B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP MITSUBISHI ELECTRIC Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 33 16 ‘8’ = 38 16 ‘7’ = 37 16 ‘4’ = 34 16 ‘7’ = 37 16 ‘M’ = 4D16 ‘4’ = 34 16 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ASCII codes ‘ 0 ’ =3016 ‘ 8 ’ =3816 ‘ 1 ’ =3116 ‘ 9 ’ =3916 ‘ 2 ’ =3216 ‘ A ’ =4116 ‘ 3 ’ =3316 ‘ B ’ =4216 ‘ 4 ’ =3416 ‘ C ’ =4316 ‘ 5 ’ =3516 ‘ D ’ =4416 ‘ 6 ’ =3616 ‘ E ’ =4516 ‘ 7 ’ =3716 ‘ F ’ =4616 ‘ T ’ =5416 ‘ - ’ =2D16 FF16 FF16 FF16 FF16 FF16 FF16 ‘ G ’ =3816 ‘ H ’ =3916 ‘ K ’ =4B16 ‘ L ’ =4C16 ‘ M’ =4D16 ‘ N ’ =4E16 ‘ P ’ =5016 ‘ Q ’ =5116 ‘ R ’ =5216 ‘ Z ’ =5A16 ‘ S ’ =5316 ‘ T ’ =5416 ‘ U ’ =5516 ‘ V ’ =5616 ‘ W ’=5716 ‘ X ’ =5816 ‘ Y ’ =5916 We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are written to addresses 001016 to 0017 16 by using the pseudo-command in the same way. EPROM type 27512 27101 The pseudo-command *=∆$0000 .BYTE∆‘M38747M4T–’ *=∆$0000 .BYTE∆‘M38747M4T–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6S) and attach it to the mask ROM confirmation form. ❈ 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator External clock input Other ( ) f(XIN) = MHz Quartz crystal Other ( ) Not use (Use for P40,P41) At what frequency? f(XcIN) = MHz (3) Which clock division ratio will you use? (possible to select plural) φ = XIN (Double-speed mode) φ = XIN /2 (High-speed mode) φ = XIN /8 (Middle-speed mode) φ = XcIN /2 (Low-speed mode) (2/3) 78 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-76B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP MITSUBISHI ELECTRIC (4) Will you use the data link layer communication control circuit? Yes No ❈ 4. Comments (3/3) 79 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-77B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) Sub ROM number of data link layer communication control circuit EPROM type (indicate the type used) 27512 EPROM address 000016 000F16 001016 001F16 002016 A07F16 A08016 FFFD16 FFFE16 FFFF16 Product name ASCII code : ‘M38747M6T–’ Sub ROM number ASCII code Data ROM 24K-130 bytes 27101 EPROM address 000016 000F16 001016 001F16 002016 A07F16 A08016 Product name ASCII code : ‘M38747M6T–’ Sub ROM number ASCII code Data ROM 24K-130 bytes FFFD16 FFFE16 1FFFF16 In the address space of the microcomputer, the internal ROM area is from address A08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF 16”. (2) The ASCII codes of the product name “M38747M6T–” must be entered in addresses 000016 to 000916 . And set the data “FF16” in addresses 000A16 to 000F 16. ASCII codes and addresses are listed to the next page. (3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the next page at writing. (1/3) 80 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-77B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP MITSUBISHI ELECTRIC Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘M’ = 4D16 ‘6’ = 3616 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ASCII codes ‘ 0 ’ =3016 ‘ 8 ’ =3816 ‘ 1 ’ =3116 ‘ 9 ’ =3916 ‘ 2 ’ =3216 ‘ A ’ =4116 ‘ 3 ’ =3316 ‘ B ’ =4216 ‘ 4 ’ =3416 ‘ C ’ =4316 ‘ 5 ’ =3516 ‘ D ’ =4416 ‘ 6 ’ =3616 ‘ E ’ =4516 ‘ 7 ’ =3716 ‘ F ’ =4616 ‘ T ’ =5416 ‘ - ’ =2D16 FF16 FF16 FF16 FF16 FF16 FF16 ‘ G ’ =3816 ‘ H ’ =3916 ‘ K ’ =4B16 ‘ L ’ =4C16 ‘ M’ =4D16 ‘ N ’ =4E16 ‘ P ’ =5016 ‘ Q ’ =5116 ‘ R ’ =5216 ‘ Z ’ =5A16 ‘ S ’ =5316 ‘ T ’ =5416 ‘ U ’ =5516 ‘ V ’ =5616 ‘ W ’=5716 ‘ X ’ =5816 ‘ Y ’ =5916 We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are written to addresses 001016 to 001716 by using the pseudo-command in the same way. EPROM type 27512 27101 The pseudo-command *=∆$0000 .BYTE∆‘M38747M6T–’ *=∆$0000 .BYTE∆‘M38747M6T–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6S) and attach it to the mask ROM confirmation form. ❈ 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator External clock input Other ( ) f(XIN) = MHz Quartz crystal Other ( ) Not use (Use for P40,P41) At what frequency? f(XcIN) = MHz (3) Which clock division ratio will you use? (possible to select plural) φ = XIN (Double-speed mode) φ = XIN /2 (High-speed mode) φ = XIN /8 (Middle-speed mode) φ = XcIN /2 (Low-speed mode) (2/3) 81 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-77B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP MITSUBISHI ELECTRIC (4) Will you use the data link layer communication control circuit? Yes No ❈ 4. Comments (3/3) 82 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-75B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) Sub ROM number of data link layer communication control circuit EPROM type (indicate the type used) 27512 EPROM address 000016 000F16 001016 001F16 002016 407F16 408016 FFFD16 FFFE 16 FFFF16 Product name ASCII code : ‘M38747MCT–’ Sub ROM number ASCII code Data ROM 48K-130 bytes 27101 EPROM address 000016 000F16 001016 001F16 002016 407F16 408016 Product name ASCII code : ‘M38747MCT–’ Sub ROM number ASCII code Data ROM 48K-130 bytes FFFD16 FFFE 16 1FFFF16 In the address space of the microcomputer, the internal ROM area is from address 408016 to FFFD 16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF 16”. (2) The ASCII codes of the product name “M38747MCT–” must be entered in addresses 000016 to 000916. And set the data “FF16” in addresses 000A16 to 000F16. ASCII codes and addresses are listed to the next page. (3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the next page at writing. (1/3) 83 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-75B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP MITSUBISHI ELECTRIC Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘M’ = 4D16 ‘C’ = 4316 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ASCII codes ‘ 0 ’ =3016 ‘ 8 ’ =3816 ‘ 1 ’ =3116 ‘ 9 ’ =3916 ‘ 2 ’ =3216 ‘ A ’ =4116 ‘ 3 ’ =3316 ‘ B ’ =4216 ‘ 4 ’ =3416 ‘ C ’ =4316 ‘ 5 ’ =3516 ‘ D ’ =4416 ‘ 6 ’ =3616 ‘ E ’ =4516 ‘ 7 ’ =3716 ‘ F ’ =4616 ‘ T ’ =5416 ‘ - ’ =2D16 FF16 FF16 FF16 FF16 FF16 FF16 ‘ G ’ =3816 ‘ H ’ =3916 ‘ K ’ =4B16 ‘ L ’ =4C16 ‘ M’ =4D16 ‘ N ’ =4E16 ‘ P ’ =5016 ‘ Q ’ =5116 ‘ R ’ =5216 ‘ Z ’ =5A16 ‘ S ’ =5316 ‘ T ’ =5416 ‘ U ’ =5516 ‘ V ’ =5616 ‘ W ’=5716 ‘ X ’ =5816 ‘ Y ’ =5916 We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are written to addresses 001016 to 001716 by using the pseudo-command in the same way. EPROM type 27512 27101 The pseudo-command *=∆$0000 .BYTE∆‘M38747MCT–’ *=∆$0000 .BYTE∆‘M38747MCT–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6S) and attach it to the mask ROM confirmation form. ❈ 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator External clock input Other ( ) f(XIN) = MHz Quartz crystal Other ( ) Not use (Use for P40,P41) At what frequency? f(XcIN) = MHz (3) Which clock division ratio will you use? (possible to select plural) φ = XIN (Double-speed mode) φ = XIN /2 (High-speed mode) φ = XIN /8 (Middle-speed mode) φ = XcIN /2 (Low-speed mode) (2/3) 84 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-75B<84A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP MITSUBISHI ELECTRIC (4) Will you use the data link layer communication control circuit? Yes No ❈ 4. Comments (3/3) 85 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-78B<84A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) Sub ROM number of data link layer communication control circuit EPROM type (indicate the type used) 27512 EPROM address 000016 000F16 001016 001F16 002016 107F16 108016 FFFD16 FFFE 16 FFFF16 Product name ASCII code : ‘M38749EFT–’ Sub ROM number ASCII code Data ROM 60K-130 bytes 27101 EPROM address 000016 000F16 001016 001F16 002016 107F16 108016 Product name ASCII code : ‘M38749EFT–’ Sub ROM number ASCII code Data ROM 60K-130 bytes FFFD16 FFFE 16 1FFFF16 In the address space of the microcomputer, the internal ROM area is from address 108016 to FFFD 16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF 16”. (2) The ASCII codes of the product name “M38749EFT–” must be entered in addresses 000016 to 000916 . And set the data “FF16” in addresses 000A16 to 000F16. The ASCII codes and addresses are listed to the next page. (3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the next page at writing. (1/3) 86 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-78B<84A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP MITSUBISHI ELECTRIC Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 33 16 ‘8’ = 38 16 ‘7’ = 37 16 ‘4’ = 34 16 ‘9’ = 39 16 ‘E’ = 45 16 ‘F’ = 46 16 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ASCII codes ‘ 0 ’ =3016 ‘ 8 ’ =3816 ‘ 1 ’ =3116 ‘ 9 ’ =3916 ‘ 2 ’ =3216 ‘ A ’ =4116 ‘ 3 ’ =3316 ‘ B ’ =4216 ‘ 4 ’ =3416 ‘ C ’ =4316 ‘ 5 ’ =3516 ‘ D ’ =4416 ‘ 6 ’ =3616 ‘ E ’ =4516 ‘ 7 ’ =3716 ‘ F ’ =4616 ‘ T ’ =5416 ‘ - ’ =2D16 FF16 FF16 FF16 FF16 FF16 FF16 ‘ G ’ =3816 ‘ H ’ =3916 ‘ K ’ =4B16 ‘ L ’ =4C16 ‘ M’ =4D16 ‘ N ’ =4E16 ‘ P ’ =5016 ‘ Q ’ =5116 ‘ R ’ =5216 ‘ Z ’ =5A16 ‘ S ’ =5316 ‘ T ’ =5416 ‘ U ’ =5516 ‘ V ’ =5616 ‘ W ’=5716 ‘ X ’ =5816 ‘ Y ’ =5916 We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are written to addresses 001016 to 001716 by using the pseudo-command in the same way. EPROM type 27512 27101 The pseudo-command *=∆$0000 .BYTE∆‘M38749EFT–’ *=∆$0000 .BYTE∆‘M38749EFT–’ Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM will not be processed. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6S) and attach it to the ROM programming confirmation form. ❈ 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? Other ( ) f(XIN) = MHz (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator Quartz crystal External clock input Other ( ) Not use (Use for P40,P41) At what frequency? f(XcIN) = MHz (3) Which clock division ratio will you use? (possible to select plural) φ = XIN (Double-speed mode) φ = XIN /2 (High-speed mode) φ = XIN /8 (Middle-speed mode) φ = XcIN /2 (Low-speed mode) (2/3) 87 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-78B<84A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP MITSUBISHI ELECTRIC (4) Will you use the data link layer communication control circuit? Yes No ❈ 4. Comments (3/3) 88 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 80P6S (80-PIN QFP) MARK SPECIFICATION FORM 80P6D, 80P6Q (80-PIN Fine-pitch QFP) Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 60 41 40 61 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi product number (6-digit, or 7-digit) 80 21 1 20 B. Customer’s Parts Number + Mitsubishi IC Catalog Name 60 41 40 61 80 21 1 20 Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s parts number can be up to 10 alphanumeric characters for capital letters, hyphens, commas, periods and so on. C. Special Mark Required 60 41 61 40 80 21 1 20 Notes 1 : If Special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated technically as close as possible. Mitsubishi product number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked for sorting the products. 2 : If special character fonts (e.g., customer’s trade mark logo) must be used in Special Mark, check the box below. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special character fonts required 89 MITSUBISHI MICROCOMPUTERS 3874 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 80P6S-A Plastic 80pin 14✕14mm body QFP EIAJ Package Code QFP80-P-1414-0.65 Weight(g) 1.11 Lead Material Alloy 42 MD e JEDEC Code HD 80 ME D b2 61 1 60 I2 HE E Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y 41 20 21 A 40 c F A2 L1 e A1 b b2 I2 MD ME L Detail F y 80D0 Dimension in Millimeters Min Nom Max – – 3.05 0.1 0.2 0 2.8 – – 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 0.65 – – 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 – – 0.1 – – 0° 10° – 0.35 – – – – 1.3 – – 14.6 – – 14.6 Glass seal 80pin QFN EIAJ Package Code – JEDEC Code – 21.0±0.2 Weight(g) 18.4±0.15 3.32MAX 0.8TYP 1.78TYP 0.6TYP 64 41 65 INDEX 90 0.5TYP 0.8TYP 12.0±0.15 1.2TYP 15.6±0.2 0.8TYP 40 25 80 24 1.2TYP 1 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials • • • • • • © 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jun. 1998. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 3874 GROUP DATA SHEET Revision Description First Edition Rev. date 980602 (1/1)