EVB72001 315MHz FSK Transmitter Evaluation Board Description General Description The TH72001 evaluation board is designed to demonstrate the optimal performance of the transmitter IC in a 50Ohm environment with the minimum of external components. The TH72001 board is populated for FSK transmission. The power amplifier is optimally matched to 50 Ohm by means of an antenna matching network for the resonant frequency of 315 MHz. Board layout data in Gerber format is available on request. Features ! ! ! ! Fully integrated PLL-stabilized VCO Frequency range from 290 MHz to 350 MHz Single-ended RF output FSK through crystal pulling allows modulation from DC to 40 kbit/s ! High FSK deviation possible for wideband data transmission ! Wide power supply range from 1.9 V to 5.5 V ! Low voltage detector P L E R Y R A ! High over-all frequency accuracy ! FSK deviation and center frequency independently adjustable ! Very low standby current ! Adjustable output power range from -15 dBm to +6 dBm ! Adjustable current consumption from 3.5 mA to 10.7 mA ! Conforms to EN 300 220 and similar standards N I IM Ordering Information Part No. EVB72001-315 Applications ! ! ! ! ! General digital data transmission Tire Pressure Monitoring System(TPMS) Remote Keyless Entry (RKE) Low-power telemetry Alarm and security systems 390127200101 Rev. 002 ! ! ! ! Page 1 of 12 Garage door openers Home automation Remote controls Local oscillator signal generation EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description Document Content 1 Theory of Operation.....................................................................................................3 1.1 General ............................................................................................................................................... 3 1.2 Block Diagram ................................................................................................................................... 3 2 Functional Description ................................................................................................4 2.1 Crystal Oscillator............................................................................................................................... 4 2.2 FSK Modulation ................................................................................................................................. 4 2.3 Crystal Pulling ................................................................................................................................... 4 2.4 Output Power Selection.................................................................................................................... 5 2.5 Lock Detection................................................................................................................................... 5 2.6 Low Voltage Detection...................................................................................................................... 5 2.7 Mode Control Logic........................................................................................................................... 6 2.8 Timing Diagrams ............................................................................................................................... 6 L E R N I IM Y R A 3 Circuit Diagram ............................................................................................................7 4 PCB Top View ..............................................................................................................8 4.1 P Board Connection ............................................................................................................................. 8 5 Board Component Values ...........................................................................................9 6 Package Information..................................................................................................10 7 Disclaimer...................................................................................................................12 390127200101 Rev. 002 Page 2 of 12 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 1 Theory of Operation 1.1 General As depicted in Fig.1, the TH72001 transmitter consists of a fully integrated voltage-controlled oscillator (VCO), a divide-by-32 divider (div32), a phase-frequency detector (PFD) and a charge pump (CP). An internal loop filter determines the dynamic behavior of the PLL and suppresses reference spurious signals. A Colpitts crystal oscillator (XOSC) is used as the reference oscillator of a phase-locked loop (PLL) synthesizer. The VCO’s output signal feeds the power amplifier (PA). The RF signal power Pout can be adjusted in four steps from Pout = –15 dBm to +6 dBm, either by changing the value of resistor RPS or by varying the voltage VPS at pin PSEL. The open-collector output (OUT) can be used either to directly drive a loop antenna or to be matched to a 50Ohm load. Bandgap biasing ensures stable operation of the IC at a power supply range of 1.9 V to 5.5 V. 1.2 Block Diagram N I IM RPS ENTX 4 P ROI 3 L E R PLL mode control 6 32 PSEL ASKDTA 5 1 PA 7 OUT antenna matching network PFD XOSC XBUF XTAL CX1 VCC Y R A CP VCO low voltage detector 2 8 VEE Fig. 1: Block diagram with external components 390127200101 Rev. 002 Page 3 of 12 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 2 Functional Description 2.1 Crystal Oscillator A Colpitts crystal oscillator with integrated functional capacitors is used as the reference oscillator for the PLL synthesizer. The equivalent input capacitance CRO offered by the crystal oscillator input pin ROI is about 18pF. The crystal oscillator is provided with an amplitude control loop in order to have a very stable frequency over the specified supply voltage and temperature range in combination with a short start-up time. 2.2 FSK Modulation FSK modulation can be achieved by pulling the crystal oscillator frequency. A CMOScompatible data stream applied at the pin FSKDTA digitally modulates the XOSC via an integrated NMOS switch. Two external pulling capacitors CX1 and CX2 allow the FSK deviation ∆f and the center frequency fc to be adjusted independently. At FSKDTA = 0, CX2 is connected in parallel to CX1 leading to the lowfrequency component of the FSK spectrum (fmin); while at FSKDTA = 1, CX2 is deactivated and the XOSC is set to its high frequency fmax. An external reference signal can be directly ACcoupled to the reference oscillator input pin ROI. Then the transmitter is used without a crystal. Now the reference signal sets the carrier frequency and may also contain the FSK (or FM) modulation. 2.3 L E R Fig. 2: Crystal pulling circuitry VCC ROI Y R A XTAL FSKSW CX2 CX1 N I IM VEE FSKDTA Description 0 fmin= fc - ∆f (FSK switch is closed) 1 fmax= fc + ∆f (FSK switch is open) Crystal Pulling P A crystal is tuned by the manufacturer to the required oscillation frequency f0 at a given load capacitance CL and within the specified calibration tolerance. The only way to pull the oscillation frequency is to vary the effective load capacitance CLeff seen by the crystal. Figure 3 shows the oscillation frequency of a crystal as a function of the effective load capacitance. This capacitance changes in accordance with the logic level of FSKDTA around the specified load capacitance. The figure illustrates the relationship between the external pulling capacitors and the frequency deviation. It can also be seen that the pulling sensitivity increases with the reduction of CL. Therefore, applications with a high frequency deviation require a low load capacitance. For narrow band FSK applications, a higher load capacitance could be chosen in order to reduce the frequency drift caused by the tolerances of the chip and the external pulling capacitors. 390127200101 Rev. 002 f XTAL L1 f max C1 C0 CL eff R1 fo f min CX1 CRO CX1+CRO CL (CX1+CX2) CRO CX1+CX2+CRO CL eff Fig. 3: Crystal pulling characteristic Page 4 of 12 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 2.4 Output Power Selection The transmitter is provided with an output power selection feature. There are four predefined output power steps and one off-step accessible via the power selection pin PSEL. A digital power step adjustment was chosen because of its high accuracy and stability. The number of steps and the step sizes as well as the corresponding power levels are selected to cover a wide spectrum of different applications. The implementation of the output power control logic is shown in figure 4. There are two matched current sources with an amount of about 8 µA. One current source is directly applied to the PSEL pin. The other current source is used for the generation of reference voltages with a resistor ladder. These reference voltages are defining the thresholds between the power steps. The four comparators deliver thermometer-coded control signals depending on the voltage level at the pin PSEL. In order to have a certain amount of ripple tolerance in a noisy environment the comparators are provided with a little hysteresis of about 20 mV. With these control signals, weighted current sources of the power amplifier are switched on or off to set the desired output power level (Digitally Controlled Current Source). The LOCK signal and the output of the low voltage detector are gating this current source. RPS PSEL & & & Y R A & N I IM & OUT Fig. 4: Block diagram of output power control circuitry L E R There are two ways to select the desired output power step. First by applying a DC voltage at the pin PSEL, then this voltage directly selects the desired output power step. This kind of power selection can be used if the transmission power must be changed during operation. For a fixed-power application a resistor can be used which is connected from the PSEL pin to ground. The voltage drop across this resistor selects the desired output power level. For fixed-power applications at the highest power step this resistor can be omitted. The pin PSEL is in a high impedance state during the “TX standby” mode. P typical values at TA = 23 °C and VCC ≥ 4 V 2.5 Power step 0 1 2 3 4 Pout / dBm < -70 -15 -6 0 6 RPS / kΩ Ω < 10 22 47 100 > 220 VPS / V 0.1 0.14 to 0.24 0.28 to 0.51 0.57 to 1.18 > 1.23 Lock Detection The lock detection circuitry turns on the power amplifier only after PLL lock. This prevents from unwanted emission of the transmitter if the PLL is unlocked. 2.6 Low Voltage Detection The supply voltage is sensed by a low voltage detect circuitry. The power amplifier is turned off if the supply voltage drops below a value of about 1.85 V. This is done in order to prevent unwanted emission of the transmitter if the supply voltage is too low. 390127200101 Rev. 002 Page 5 of 12 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 2.7 Mode Control Logic The mode control logic allows two different modes of operation as listed in the following table. The mode control pin ENTX is pulleddown internally. This guarantees that the whole circuit is shut down if this pin is left floating. 2.8 ENTX Mode Description 0 TX standby TX disabled 1 TX active TX enable Timing Diagrams After enabling the transmitter by the ENTX signal, the power amplifier remains inactive for the time ton, the transmitter start-up time. The crystal oscillator starts oscillation and the PLL locks to the desired output frequency within the time duration ton. After successful PLL lock, the LOCK signal turns on the power amplifier, and then the RF carrier can be FSK modulated. high ENTX low high LOCK low L E R high FSKDTA N I IM Y R A low P RF carrier t t on Fig. 5: Timing diagram for FSK modulation For more detailed information, please refer to the latest TH72001 data sheet revision. 390127200101 Rev. 002 Page 6 of 12 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 3 Circuit Diagram OUT CM2 LM CM1 CM3 CB1 RPS PSEL ENTX ROI Y R A XTAL CX1 CB0 1 2 3 1 2 VCC GND 1 2 3 VCC DATA GND P N I IM VCC ENTX GND OUT FSKSW L E R CX2 5 6 VCC 7 FSKDTA 8 VEE LT Fig. 6: Circuit diagram for FSK with 50 Ω matching network 390127200101 Rev. 002 Page 7 of 12 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 4 PCB Top View P CM1 Melexis LM EVB72011 / 12 / 31 / 32 (1) TX_output CM2 N I IM CM3 LT CB1 RPS 8 L E R 5 Y R A TH72001 1 4 CX2 CX1 XTAL CB0 VCC ENTX 1 VCC Data 1 VCC 1 Board size is 23 mm x 34 mm 4.1 VCC DATA Board Connection Power supply (1.9 V to 5.5 V) ENTX Mode control pin (see para. 2.4) Input for FSK data (CMOS, see para. 2.2) GND Several ground pins 390127200101 Rev. 002 Page 8 of 12 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 5 Board Component Values Part Size Value @ 315 MHz Tolerance Description *CX1 0805 TBD ±5% XOSC capacitor (∆f = ±20 kHz) *CX2 0805 TBD ±5% XOSC capacitor (∆f = ±20 kHz) CM1 0805 TBD ±5% impedance matching capacitor CM2 0805 TBD ±5% impedance matching capacitor CM3 0603 TBD ±5% impedance matching capacitor CB0 0805 1 nF ±10% blocking capacitor CB1 0603 330 pF ±10% blocking capacitor LT 0603 TBD ±5% output tank inductor LM 0603 TBD ±5% impedance matching inductor RPS 0805 see para. 2.4 ±10% power-select resistor XTAL HC49/S 9.84375 MHz fundamental wave ±30ppm calibration ±30ppm temp. *Notes: Value depends on crystal parameters Your Notes P 390127200101 Rev. 002 L E R Y R A crystal, CL = 12 pF, C0, max = 7 pF, R1 = 60 Ω N I IM Page 9 of 12 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 6 Package Information E1 E 1 2 3 D L b e Y R A α A1 A N I IM Fig. 7: SOIC8 (Shrink Small Outline Package) L E R all Dimension in mm, coplanarity < 0.1mm A A1 e b L α 5.80 1.32 0.10 1.27 0.36 0.41 0° 6.20 1.72 0.25 0.46 1.27 8° D E1 E min 4.80 3.81 max 4.98 3.99 P all Dimension in inch, coplanarity < 0.004” 390127200101 Rev. 002 min 0.189 0.150 0.2284 0.060 0.0040 0.05 0.014 0.016 0° max 0.196 0.157 0.2440 0.068 0.0098 0.050 8° Page 10 of 12 0.018 EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description Your Notes P 390127200101 Rev. 002 L E R N I IM Page 11 of 12 Y R A EVB Description Oct/02 EVB72001 315MHz FSK Transmitter Evaluation Board Description 7 Disclaimer Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifesupport or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services. © 2002 Melexis NV. All rights reserved. P L E R N I IM Y R A For the latest version of this document. Go to our website at www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: All other locations: Phone: +32 1367 0495 E-mail: [email protected] Phone: +1 603 223 2362 E-mail: [email protected] QS9000, VDA6.1 and ISO14001 Certified 390127200101 Rev. 002 Page 12 of 12 EVB Description Oct/02