IDT74FCT162H952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE FAST CMOS 16-BIT REGISTERED TRANSCEIVER FEATURES: • • • • • • • • • IDT74FCT162H952AT/CT/ET DESCRIPTION: 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage ≤ 1µA (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Bus Hold retains last active bus state during 3-state Eliminates the need for external pull up resistors Power off disable outputs permit “live insertion” Available in SSOP and TSSOP packages The FCT162H952T 16-bit registered transceiver is built using advanced dual metal CMOS technology. These high-speed, low-power devices are organized as two independent 8-bit D-type registered transceivers with separate input and output control for independent control of data flow in either direction. For example, the A-to-B Enable (xCEAB) must be low to enter data from the A port. xCLKAB controls the clocking function. When xCLKAB toggles from low-to-high, the data present on the A port will be clocked into the register. xOEAB performs the output enable function on the B port. Data flow from the B port to A port is similar but requires using xCEBA, xCLKBA, and xOEBA inputs. Full 16-bit operation is achieved by tying the control pins of the independent transceivers together. The FCT162H952T has "Bus Hold" which retains the input's last state whenever the input goes to high impedance. This prevents "floating" inputs and eliminates the need for pull-up/down resistors. FUNCTIONAL BLOCK DIAGRAM 54 31 2 CE BA 1 CE BA 30 55 2 CLKBA 1 CLKBA 28 1 2 OE AB 1 OE AB 26 3 2 CE AB 1 CE AB 2 27 2 CLKAB 1 CLKAB 29 56 2 OE BA 1 OE BA C CE 5 1A 1 D 15 2A 1 52 1B 1 C CE D 42 2B 1 C CE D C CE D TO SEVEN OTHE R CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE APRIL 2002 1 © 2002 Integrated Device Technology, Inc. DSC-5441/1 IDT74FCT162H952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol Description 1OEAB 1 56 1OEBA VTERM(2) Terminal Voltage with Respect to GND 1CLKAB 2 55 1CLKBA VTERM(3) Terminal Voltage with Respect to GND 1CEAB 3 54 1CEBA TSTG Storage Temperature –65 to +150 °C GND 4 53 GND IOUT DC Output Current –60 to +120 mA 1A 1 5 52 1B 1 1A 2 6 51 1B 2 VCC 7 50 VCC 1A 3 8 49 1B 3 1A 4 9 48 1B 4 1A 5 10 47 1B 5 GND 11 46 GND 1A 6 12 45 1B 6 1A 7 13 44 1B 7 1A 8 14 43 1B 8 2A 1 15 42 2B 1 2A 2 16 41 2B 2 2A 3 17 40 2B 3 GND 18 39 GND 2A 4 19 38 2B 4 2A 5 20 37 2 B5 2A 6 21 36 2 B6 VCC 22 35 VCC 2A 7 23 34 2 B7 2A 8 24 33 2 B8 GND 25 32 GND 2CEAB 26 31 2CEBA 2CLKAB 27 30 2CLKBA 2OEAB 28 29 2OEBA Symbol xOEBA B-to-A Output Enable Input (Active LOW) xCEAB A-to-B Clock Enable Input (Active LOW) xCEBA B-to-A Clock Enable Input (Active LOW) xCLKAB A-to-B Clock Input xCLKBA B-to-A Clock Input xAx A-to-B Data Inputs or B-to-A 3-State Outputs(1) xBx B-to-A Data Inputs or A-to-B 3-State Outputs(1) V V Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 3.5 6 pF COUT Output Capacitance VOUT = 0V 3.5 8 pF NOTE: 1. This parameter is measured at characterization but not tested. FUNCTION TABLE(1, 3) Inputs Description A-to-B Output Enable Input (Active LOW) –0.5 to 7 –0.5 to VCC+0.5 CAPACITANCE (TA = +25°C, f = 1.0MHz) PIN DESCRIPTION xOEAB Unit NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals.VCC terminals. 3. Outputs and I/O terminals for FCT162XXX. SSOP/ TSSOP TOP VIEW Pin Names Max Outputs xCEAB xCLKAB xOEAB xAx xBx H X L X B(2) X L L X B(2) L ↑ L L L L ↑ L H H X X H X Z NOTES: 1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA, and xOEBA. 2. Level of B before the indicated steady-state input conditions were established. 3. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care ↑ = LOW-to-HIGH Transition Z = High-impedance NOTE: 1. These pins have “Bus Hold”. All other pins are standard inputs, outputs or I/Os. 2 IDT74FCT162H952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10% Test Conditions(1) Min. Typ.(2) Max. Unit 2 — — V — — 0.8 V — — ±1 µA Symbol Parameter VIH Input HIGH Level Guaranteed Logic HIGH Level VIL Input LOW Level Guaranteed Logic LOW Level IIH Input Standard Input(5) HIGH Standard I/O(5) — — ±1 Current(4) Bus-hold Input — — ±100 VCC = Max. VI = VCC Bus-hold I/O IIL — — ±100 — — ±1 Standard I/O(5) — — ±1 Bus-hold Input — — ±100 Bus-hold I/O — — ±100 Input Standard Input(5) LOW Current(4) Bus-hold Input VI = GND IBHH Bus-hold Sustain IBHL Current(4) VCC = Min. IOZH High Impedance Output Current IOZL (3-State Output pins)(5, 6) VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V IOS Short Circuit Current VCC = Max., VO = GND(3) –80 –140 –250 mA VH Input Hysteresis — 100 — mV ICCL Quiescent Power Supply Current — 5 500 µA VCC = Max. VI = 2V –50 — — VI = 0.8V 50 — — VO = 2.7V — — ±1 VO = 0.5V — — ±1 — VCC = Max ICCH ICCZ µA µA VIN = GND or VCC OUTPUT DRIVE CHARACTERISTICS Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) VCC = Min. IOH = –24mA VIN = VIH or VIL VCC = Min. IOL = 24mA VIN = VIH or VIL NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Pins with Bus-hold are identified in the pin description. 5. The test limit for this parameter is ±5µA at TA = –55°C. 6. Does not include Bus-hold I/O pins. 3 Min. 60 –60 2.4 Typ.(2) 115 –115 3.3 Max. 200 –200 — Unit mA mA V — 0.3 0.55 V IDT74FCT162H952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) IC Total Power Supply Current(6) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open xOEAB or xOEBA = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz (xCLKAB) 50% Duty Cycle xOEAB = xCEAB = GND xOEBA = VCC One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz (xCLKAB) 50% Duty Cycle xOEAB = xCEAB = GND xOEBA = VCC Sixteen Bits Toggling fi = 2.5MHz 50% Duty Cycle Min. — Typ.(2) 0.5 Max. 1.5 Unit mA VIN = VCC VIN = GND — 75 120 µA/ MHz VIN = VCC VIN = GND — 0.8 1.7 mA VIN = 3.4V VIN = GND — 1.3 3.2 VIN = VCC VIN = GND — 3.8 6.5(5) VIN = 3.4V VIN = GND — 8.3 20(5) NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, I CCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 4 IDT74FCT162H952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW tSK(o) Parameter Propagation Delay xCLKAB, xCLKBA to xBx, xAx Output Enable Time xOEBA, xOEAB to xAx, xBx Output Disable Time xOEBA, xOEAB to xAx, xBx Set-up Time, HIGH or LOW xAx, xBx to xCLKAB, xCLKBA Hold Time HIGH or LOW xAx, xBx to xCLKAB, xCLKBA Set-up Time, HIGH or LOW xCEAB, xCEBA to xCLKAB, xCLKBA Hold Time HIGH or LOW xCEAB, xCEBA to xCLKAB, xCLKBA Pulse Width HIGH or LOW xCLKAB or xCLKBA(3) Condition(1) CL = 50pF RL = 500Ω Output Skew(4) FCT162H952AT FCT162H952CT FCT162H952ET Min.(2) 2 Max. 10 Min.(2) 2 Max. 6.3 Min.(2) 1.5 Max. 3.7 Unit ns 1.5 10.5 1.5 7 1.5 4.4 ns 1.5 10 1.5 6.5 1.5 3.6 ns 2.5 — 2.5 — 1.5 — ns 2 — 1.5 — 0 — ns 3 — 3 — 2 — ns 2 — 2 — 0 — ns 3 — 3 — 3 — ns — 0.5 — 0.5 — 0.5 ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Guaranteed but not tested. 4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 5 IDT74FCT162H952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V Test Switch Open Drain Disable Low Enable Low Closed All Other Tests Open 500 Ω V O UT V IN Pulse Generator D.U.T. 50pF RT 500 Ω CL DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. t RE M tSU 3V 1.5V 0V 3V 1.5V 0V LOW -HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW -HIGH PULSE 1.5V 3V 1.5V 0V tH Pulse Width Set-up, Hold, and Release Times ENAB LE SAM E PHASE INPUT TRANSITION t PLH tPH L OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPH L 3V 1.5V 0V DISABLE 3V CONTROL INPUT 1.5V t PZL V OH 1.5V V OL OUTPUT NORM ALLY LOW 3V 1.5V 0V SW ITCH CLOSED 3.5V 1.5V Propagation Delay 3.5V 0.3V t PZH OUTPUT NORM ALLY HIGH 0V tPLZ V OL tPHZ SW ITCH OPEN 0.3V V OH 1.5V 0V 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 6 IDT74FCT162H952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX FCT XXX Temp. Range Family X Bus Hold XXXX Device Type X Package PV PA Shrink Small Outline Package Thin Shrink Small Outline Package 952AT 952CT 952ET 16-Bit Registered Transceiver H Bus Hold 162 Double-Density, 5 Volt, Balanced Drive 74 - 40°C to +85°C DATA SHEET DOCUMENT HISTORY 4/11/2002 Removed B speed option CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459