ETC LXT980QC

LXT980/980A Dual-Speed, 5-Port Fast
Ethernet Repeater
Datasheet
General Description
The LXT980 is a 5-port 10/100 Class II Repeater that is fully compliant with IEEE 802.3
standards. Four ports directly support either 100BASE-TX/10BASE-T copper media or
100BASE-FX fiber media via pseudo-ECL (PECL) interfaces. The fifth port, a 10 or 100 Mbps
Media Independent Interface (MII), connects to Media Access Controllers (MACs) for bridge/
switch applications. At 100 Mbps, the MII can also be configured to interface to another PHY
device, such as the LXT970. This data sheet applies to all LXT980 products (LXT980,
LXT980A, and any subsequent variants), except as specifically noted.
The LXT980 provides auto-negotiation with parallel detection for the four PHY ports. These
ports can also be manually configured, either by hardware or software. The LXT980 provides
two internal repeater state machines—one operating at 10 Mbps and one at 100 Mbps. Once
configured, the LXT980 automatically connects each port to the appropriate repeater.
The LXT980 also provides two Inter-Repeater Backplanes (IRBs) for expansion — one
operating at 10 Mbps and one at 100 Mbps. Up to 240 ports can logically be combined into one
repeater using these buses. The LXT980 supports SNMP and RMON management via on-chip
32- and 64-bit counters. The counters and control information are accessible via a high-speed
Serial Management Interface (SMI). The device supports two Source Address Tracking registers
per port and a Source Address Matching Function.
Product Features
■
■
■
■
■
Four 10/100 ports with complete twistedpair PHYs including integrated filters and
100BASE-FX PECL interfaces.
10/100 MII port connection to either MAC
or PHY.
Independent segments for 10 and 100 Mbps
operation.
Cascadable Inter-Repeater Backplanes
(IRBs).
Hardware assist for RMON and the
Repeater MIB.
■
■
■
■
■
■
High-speed Serial Management Interface
(SMI).
Two address-tracking registers per port.
Source Address matching function.
Integrated LED drivers with user-selectable
modes.
Available in 208-pin QFP package.
Case temperature range: 0-115°C.
As of January 15, 2001, this document replaces the Level One document
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater.
Order Number: 249111-001
January 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Contents
1.0
Pin Assignments and Signal Descriptions ....................................................10
2.0
Functional Description...........................................................................................20
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.0
Application Information .........................................................................................48
3.1
Datasheet
Introduction..........................................................................................................20
2.1.1 TP/FX Port Configuration .......................................................................24
2.1.2 MII Port Configuration ............................................................................25
2.1.3 Interface Descriptions.............................................................................25
2.1.4 Repeater Operation................................................................................27
2.1.5 Management Support.............................................................................29
2.1.6 LED Drivers ............................................................................................30
Requirements ......................................................................................................30
2.2.1 Power .....................................................................................................30
2.2.2 Clock ......................................................................................................30
2.2.3 Bias Resistor ..........................................................................................30
2.2.4 Reset ......................................................................................................30
2.2.5 PROM.....................................................................................................30
2.2.6 Chip ID ...................................................................................................31
2.2.7 Management Master I/O Link .................................................................31
2.2.8 IRB Bus Pull-ups ....................................................................................31
LED Operation.....................................................................................................31
2.3.1 Blink Rates .............................................................................................32
2.3.2 Power-Up and Reset Conditions ............................................................32
2.3.3 Port LEDs ...............................................................................................32
2.3.4 Segment LEDs .......................................................................................32
2.3.5 Global LEDs ...........................................................................................33
IRB Operation......................................................................................................35
2.4.1 MAC IRB Access....................................................................................35
2.4.2 IRB Isolation ...........................................................................................35
2.4.3 MMSTRIN, MMSTROUT........................................................................36
MII Port Operation ...............................................................................................37
2.5.1 PHY Mode Operation .............................................................................38
2.5.2 MAC Mode Operation.............................................................................38
2.5.3 MII Port Timing Considerations ..............................................................39
Serial Management I/F ........................................................................................40
2.6.1 Serial Clock ............................................................................................41
2.6.2 Serial Data I/O........................................................................................41
2.6.3 Read and Write Operations....................................................................41
2.6.4 Interrupt Functions .................................................................................43
2.6.5 Address Arbitration.................................................................................44
Serial EEPROM Interface....................................................................................46
Design Recommendations ..................................................................................48
3.1.1 General Design Guidelines ....................................................................48
3.1.2 Power Supply Filtering ...........................................................................48
3.1.3 Power and Ground Plane Layout Considerations ..................................49
3.1.4 MII Terminations.....................................................................................49
3
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
3.2
3.1.5 The RBIAS Pin ....................................................................................... 50
3.1.6 The Twisted-Pair Interface ..................................................................... 50
3.1.7 The Fiber Interface................................................................................. 50
3.1.8 Magnetics Information............................................................................ 51
Typical Application Circuitry ................................................................................ 52
4.0
Test Specifications .................................................................................................. 59
5.0
Register Definitions ................................................................................................ 79
5.1
5.2
5.3
5.4
5.5
6.0
4
Counter Registers ............................................................................................... 79
5.1.1 Port Counter Registers........................................................................... 79
5.1.2 RMON Counter Registers ...................................................................... 81
Ethernet Address Registers ................................................................................ 82
5.2.1 Port Address Tracking Registers............................................................ 82
5.2.2 Search Address Registers ..................................................................... 83
Control and Status Registers .............................................................................. 83
5.3.1 Port Link Control Register ...................................................................... 83
5.3.2 General Port Control Registers .............................................................. 84
5.3.3 Port Learn and Speed Control Registers ............................................... 85
5.3.4 Port Status Registers ............................................................................. 85
5.3.5 Interrupt Status/Mask Registers ............................................................. 86
5.3.6 MII Status Register................................................................................. 87
Configuration Registers....................................................................................... 88
5.4.1 Repeater Configuration Register............................................................ 89
Auto-Negotiation Registers ................................................................................. 92
Mechanical Specifications ................................................................................... 95
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figures
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42
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater .................................. 9
Pin Assignments .................................................................................................10
Typical Managed Repeater Architectures ..........................................................21
Typical Unmanaged 100 Mbps Repeater Architectures .....................................21
Typical Hybrid Switch/Repeater Application .......................................................22
Typical Application Block Diagram .....................................................................23
IRB Block Diagram .............................................................................................36
MII (Port 5) Operation .........................................................................................38
MII Timing Issues ...............................................................................................40
Typical Serial Bus Architecture ..........................................................................41
Serial Management Frame Format ....................................................................43
Address Arbitration Mechanisms ........................................................................46
Serial EEPROM Interface ...................................................................................47
Optional R/W Serial EEPROM Interface ............................................................47
Managed 10/100 Repeater Stack .......................................................................52
Hybrid Switch/Repeater Application - for Balanced 10/100 Performance ..........52
Hybrid Switch/Repeater Application - Weighted Toward 100 Mbps Performance .
53
Unmanaged 100-Only Repeater Stack ..............................................................53
Power and Ground Connections ........................................................................54
Typical Fiber Port Interface ................................................................................55
Typical Twisted-Pair Port Interface and Power Supply Filtering ........................56
Typical 100 Mbps IRB Implementation ...............................................................57
Typical 10 Mbps IRB Implementation .................................................................57
Typical Serial Management Interface Connections ............................................58
Typical Reset Circuit ..........................................................................................58
100 Mbps Port-to-Port Delay Timing ..................................................................63
100BASE-TX Transmit Timing - PHY MODE MII ...............................................64
100BASE-TX Receive Timing - PHY Mode MII ..................................................65
100BASE-TX Transmit Timing - MAC Mode MII ................................................66
100BASE-TX Receive Timing - MAC Mode MII .................................................67
100BASE-FX Transmit Timing - PHY Mode MII .................................................68
100BASE-FX Receive Timing - PHY Mode MII ..................................................69
100BASE-FX Transmit Timing - MAC Mode MII ................................................70
100BASE-FX Receive Timing - MAC Mode MII .................................................71
10BASE-T Transmit Timing - PHY Mode MII .....................................................72
10BASE-T Receive Timing - PHY Mode MII ......................................................73
100 Mbps IRB Timing .........................................................................................74
10 Mbps IRB Receive Timing .............................................................................75
10 Mbps IRB Transmit Timing ............................................................................76
Serial Management Interface Timing .................................................................77
PROM Interface Timing ......................................................................................78
Package Specifications .......................................................................................95
5
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
6
Mode Control Signal Descriptions....................................................................... 11
PHY Mode MII Interface Signal Descriptions ...................................................... 11
MAC Mode MII Interface Signal Descriptions ..................................................... 12
Inter-Repeater Backplane Signal Descriptions ................................................... 13
Twisted-Pair Port Signal Descriptions ................................................................. 15
Fiber Port Signal Descriptions............................................................................. 15
Serial Management Interface Signal Descriptions .............................................. 15
LED Signal Descriptions ..................................................................................... 16
Power Supply and Indication Signal Descriptions ............................................... 17
PROM Interface Signal Descriptions................................................................... 18
Miscellaneous Signal Descriptions...................................................................... 18
Manual Speed Selection ..................................................................................... 24
LED Mode 1 Indications ...................................................................................... 34
LED Mode 2 Indications ...................................................................................... 34
LED Mode 3 Indications ...................................................................................... 35
IRB Signal Types ................................................................................................ 36
IRB Signal Details ............................................................................................... 37
MII (Port 5) Mode & Speed Control..................................................................... 38
Serial Management Interface Message Fields.................................................... 42
Serial Management Header Storage................................................................... 43
Serial Management Interface Command Set ...................................................... 43
Typical Serial Management Packets................................................................... 44
Magnetics Specifications..................................................................................... 51
Absolute Maximum Ratings ................................................................................ 59
Operating Conditions .......................................................................................... 59
Input Clock Requirements................................................................................... 59
I/O Electrical Characteristics ............................................................................... 60
100 Mbps IRB Electrical Characteristics ............................................................. 60
10 Mbps IRB Electrical Characteristics ............................................................... 61
100BASE-TX Transceiver Electrical Characteristics.......................................... 61
100BASE-FX Transceiver Electrical Characteristics.......................................... 61
10BASE-T Transceiver Electrical Characteristics .............................................. 62
100 Mbps Port-to-Port Delay Timing Parameters ............................................... 63
100BASE-TX Transmit Timing Parameters - PHY Mode MII.............................. 64
100BASE-TX Receive Timing Parameters - PHY Mode MII............................... 65
100BASE-TX Transmit Timing Parameters - MAC Mode MII ............................. 66
100BASE-TX Receive Timing - MAC Mode MII.................................................. 67
100BASE-FX Transmit Timing Parameters - PHY Mode MII.............................. 68
100BASE-FX Receive Timing - PHY Mode MII .................................................. 69
100BASE-FX Transmit Timing - MAC Mode MII................................................. 70
100BASE-FX Receive Timing - MAC Mode MII.................................................. 71
10BASE-T Transmit Timing Parameters - PHY Mode MII .................................. 72
10BASE-T Receive Timing Parameters - PHY Mode MII ................................... 73
100 Mbps IRB Timing Parameters1 .................................................................... 74
10 Mbps IRB Receive Timing Parameters1 ........................................................ 75
10 Mbps IRB Transmit Timing Parameters ......................................................... 76
Serial Interface Timing Characteristics 1 ............................................................ 77
PROM Interface Timing Characteristics.............................................................. 78
Register Set ........................................................................................................ 79
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Datasheet
Counter Register Bit Assignments ......................................................................79
Port Counter Registers........................................................................................80
RMON Counter Registers ...................................................................................81
Ethernet Address Register Bit Assignments .......................................................82
Port Address Tracking Registers.........................................................................82
Search Address Registers...................................................................................83
Port Link Control and Status Register Bit Assignments ......................................83
Port Link Control Register ...................................................................................83
General Port Control and Status Register Bit Assignments ................................84
General Port Control Registers ...........................................................................84
Port Learn and Speed Control Registers ............................................................85
Port Learn and Speed Control Registers ............................................................85
Port Status Register Bit Assignments .................................................................85
Port Status Registers ..........................................................................................86
Interrupt Status/Mask Register Bit Assignments .................................................86
Interrupt Status/Mask Register............................................................................86
Interrupt Status Register Bit Definitions ..............................................................87
MII Status Register Bit Assignment.....................................................................87
MII Status Register..............................................................................................88
Configuration Registers.......................................................................................88
Repeater Configuration Register Bit Assignments ..............................................90
Repeater Configuration Register Bit Definitions..................................................90
Device/Revision Register Bit Assignment ...........................................................91
Global LED Control Register Bit Assignments ....................................................91
Port LED Control Register Bit Assignments ........................................................91
LED Timer Control Register Bit Assignments .....................................................91
Address Assignment Register Bit Assignments ..................................................91
EPROM Address Register Bit Assignments........................................................91
Auto-Negotiation Registers .................................................................................92
Auto-Negotiation Link Partner Ability Registers ..................................................92
Auto-Negotiation Status Registers ......................................................................93
Auto-Negotiation Advertisement Register ...........................................................93
Auto-Negotiation Configuration Register.............................................................94
7
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Revision History
Revision
8
Date
Description
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 1. LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
100M IRB
10BASE-T
Repeater
10/100
E’net PHY
100 Mbps
Backplane
100BASE-X
Repeater
10/100
E’net PHY
Twisted Pair_I/O
10/100
E’net PHY
Twisted Pair_I/O
10/100
E’net PHY
Twisted Pair_I/O
Mode Control
Serial Mgmt
Port & Mgmt
Status Indicators
Datasheet
Twisted Pair_I/O
10 Mbps
Backplane
Serial Port
Device
Management
LED Drivers
RMON &
SNMP
Counters
Port Switching Logic
10M IRB
MII
Fiber_I/O
Fiber_I/O
Fiber_I/O
Fiber_I/O
Reversible MII
9
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
1.0
Pin Assignments and Signal Descriptions
52............ IR100CLK
51............ VCC
50............ GND
49............ IR100DAT4
48............ N/C
47............ N/C
46............ IR100DAT3
45............ IR100DAT2
44............ IR100DAT1
43............ IR100DAT0
42............ IR100DV
41............ IR100DEN
40............ IR100COL
39............ N/C
38............ IR100SNGL
37............ IR100CFSB
36............ IR100CFS
35............ VCC
34............ GND
33............ MII_RXD3
32 ........... MII_RXD2
31............ N/C
30............ MII_RXD1
29............ MII_RXD0
28............ VCC
27............ GNDA
26............ MII_RXDV
25............ MII_RXCLK
24............ MII_RXER
23............ N/C
22............ MII_TXER
21............ MII_TXCLK
20............ MII_TXEN
19............ MII_TXD0
18............ MII_TXD1
17............ MII_TXD2
16............ MII_TXD3
15............ N/C
14............ MII_COL
13............ MII_CRS
12............ VCC
11............ GND
10............ IR10CLK
9.............. IR10DAT
8.............. IR10ENA
7.............. N/C
6.............. IR10DEN
5.............. IR10CFSBP
4.............. IR10COLBP
3.............. IR10COL
2.............. GND
1.............. IR10CFS
Figure 2. Pin Assignments
RESET .......53
CLK25 .......54
IR10ISO .......55
IR100ISO .......56
VCC .......57
RECONFIG .......58
SRX .......59
STX .......60
SERCLK .......61
SER_MATCH .......62
MMSTROUT .......63
ARBOUT .......64
ARBSELECT .......65
MGR_PRES .......66
PROM_CLK .......67
PROM_CS .......68
PROM_DTOUT .......69
PROM_DTIN .......70
CHIPID0 .......71
CHIPID1 .......72
CHIPID2 .......73
AUTO_BLINK/GND .......74
GND .......75
VCC .......76
RPS_FAULT .......77
RPS_PRES .......78
MACACTIVE .......79
HOLDCOL .......80
IRQ .......81
GND .......82
GND .......83
VCC .......84
COL10_LED .......85
COL100_LED .......86
MGR_LED .......87
GND .......88
VCC .......89
ACT10_LED .......90
ACT100_LED .......91
FAULT_LED .......92
GND .......93
VCCV .......94
GNDV .......95
VCC .......96
N/C .......97
RPS_LED .......98
PORT5_SEL .......99
PORT5_SPD .......100
N/C .......101
N/C .......102
N/C .......103
GNDR .......104
LXT980 XX
XXXXXX
XXXXXXXX
Rev #
TPIP4....... 105
TPIN4....... 106
VCCR....... 107
TPOP4....... 108
GNDT....... 109
TPON4....... 110
VCCT....... 111
FIBOP4....... 112
FIBON4....... 113
SIGDET4....... 114
FIBIN4....... 115
FIBIP4....... 116
GNDR....... 117
TPIP3....... 118
TPIN3....... 119
VCCR....... 120
TPOP3....... 121
GNDT....... 122
TPON3....... 123
VCCT....... 124
FIBOP3....... 125
FIBON3....... 126
SIGDET3....... 127
FIBIN3....... 128
FIBIP3....... 129
GNDA....... 130
RBIAS....... 131
GNDR....... 132
TPIP2....... 133
TPIN2....... 134
VCCR....... 135
TPOP2....... 136
GNDT....... 137
TPON2....... 138
VCCT....... 139
FIBOP2....... 140
FIBON2....... 141
SIGDET2....... 142
FIBIN2....... 143
FIBIP2....... 144
GNDR....... 145
TPIP1....... 146
TPIN1....... 147
VCCR....... 148
TPOP1....... 149
GNDT....... 150
TPON1....... 151
VCCT....... 152
FIBOP1....... 153
FIBON1....... 154
SIGDET1....... 155
FIBIN1....... 156
Part #
LOT #
FPO #
208.......... LEDSEL0
207.......... LEDSEL1
206.......... VCC
205.......... VCC
204.......... VCC
203.......... VCC
202.......... GND
201.......... VCC
200.......... GND
199.......... MMSTRIN
198.......... ARBIN
197.......... CONFIG0
196.......... CONFIG1
195.......... CONFIG2
194.......... CONFIG3
193.......... CONFIG4
192.......... CONFIG5
191.......... CONFIG6
190.......... CONFIG7
189.......... PORT1_SPD0
188.......... PORT1_SPD1
187.......... PORT2_SPD0
186.......... PORT2_SPD1
185.......... PORT3_SPD0
184.......... PORT3_SPD1
183.......... PORT4_SPD0
182.......... PORT4_SPD1
181.......... PORT1_LED1
180.......... PORT1_LED2
179.......... PORT1_LED3
178.......... GND
177.......... PORT2_LED1
176.......... PORT2_LED2
175.......... PORT2_LED3
174.......... GND
173.......... PORT3_LED1
172.......... PORT3_LED2
171.......... PORT3_LED3
170.......... VCC
169.......... VCCV
168.......... GNDV
167.......... GND
166.......... PORT4_LED1
165.......... PORT4_LED2
164.......... PORT4_LED3
163.......... GND
162.......... PORT5_LED1
161.......... PORT5_LED2
160.......... PORT5_LED3
159.......... GND
158.......... GND
157.......... FIBIP1
Note: For Pin 74 Signal Description, see Table 9 on page 17 (LXT980) and Table 11 on page 18
Package Topside Markings
Marking
Definition
Part #
LXT980 is the unique identifier for this product family.
Rev #
Identifies the particular silicon “stepping” (Refer to Specification Update for additional stepping
information.)
Lot #
Identifies the batch.
FPO #
Identifies the Finish Process Order.
10
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 1.
Mode Control Signal Descriptions
Pin
Symbol
189
PORT1_SPD0
188
PORT1_SPD1
187
PORT2_SPD0
186
PORT2_SPD1
185
PORT3_SPD0
184
PORT3_SPD1
183
PORT4_SPD0
182
PORT4_SPD1
100
PORT5_SPD
99
PORT5_SEL
197
196
195
194
193
192
191
190
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
CONFIG7
Type1
Description
Speed Select - Ports 1 through 4. These pins set the default value of the Port
Speed Control Register for the associated port as follows:
TTL Input,
PU,
Latched on
reset
TTL Input,
PU
TTL Input,
PU
TTL Input,
PD
SPD1
SPD0
Mode
0
0
Allow 10/100 auto-negotiation/parallel detection.
0
1
Force 10BASE-T.
1
0
Force 100BASE-FX.
1
1
Force 100BASE-TX.
Speed Select - Port 5. Selects operating speed of the MII (MAC) interface. Also
selects the segment on which statistics are kept.
High = 100 Mbps. Low = 10 Mbps.
(Port 5 speed of 10 Mbps is available when PHY mode is selected.)
Mode Select - Port 5. Selects operating mode of the MII interface. Pin is
monitored at power-up and reset. Subsequent changes have no effect.
High = PHY Mode (LXT980 acts as PHY side of the MII.)
Low = MAC Mode (LXT980 acts as MAC side of the MII.)
Configuration Register Inputs. These inputs allow the user to store systemspecific information (board type, plug-in cards, status, etc.) in the Serial
Configuration Register (address AC). This register may be read remotely through
the Serial Management Interface (SMI).
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PU = Input contains pull-up.
PD = Input contains pull-down.
TTL = Transistor-Transistor Logic.
Table 2.
Pin
PHY Mode MII Interface Signal Descriptions
Symbol
Type1
Description
Output
TTL
Receive Data. The LXT980 transmits received data to the controller on these outputs. Data
is driven on the falling edge of MII_RXCLK.
29
MII_RXD0
30
MII_RXD1
32
MII_RXD2
33
MII_RXD3
26
MII_RXDV
Output
TTL
Receive Data Valid. Active High signal, synchronous to MII_RXCLK, indicates valid data
on MII_RXD<3:0>.
25
MII_RXCLK
Output
TTL
Receive Clock. MII receive clock for expansion port. This is a 2.5 or 25 MHz clock derived
from the CLK25 input (refer to Table 11).
24
MII_RXER
Output
TTL
Receive Error. Active High signal, synchronous to MII_RXCLK, indicates invalid data on
MII_RXD<3:0>.
22
MII_TXER
Input
TTL
Transmit Error. MII_TXER is a 100M-only signal. The MAC asserts this input when an
error has occurred in the transmit data stream. The LXT980 responds by sending ‘Invalid
Code Symbols’ on the line.
1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for PHY mode.
Datasheet
11
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 2.
PHY Mode MII Interface Signal Descriptions (Continued)
Pin
Symbol
Type1
21
MII_TXCLK
Output
TTL
20
MII_TXEN
Input
TTL
Transmit Enable. External controllers drive this input High to indicate that data is being
transmitted on the MII_TXD<3:0> pins. Tie this input Low if it is unused.
19
MII_TXD0
18
MII_TXD1
17
MII_TXD2
Input
TTL
Transmit Data. External controllers use these inputs to transmit data to the LXT980. The
LXT980 samples MII_TXD<3:0> on the rising edge of MII_TXCLK, when MII_TXEN is High.
16
MII_TXD3
14
MII_COL
Output
TTL
Collision. The LXT980 drives this signal High to indicate that a collision has occurred.
13
MII_CRS
Output
TTL
Carrier Sense. Active High signal indicates LXT980 is transmitting or receiving.
Description
Transmit Clock. 2.5 or 25 MHz continuous output derived from the 25 MHz input clock.
1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for PHY mode.
Table 3.
Pin
MAC Mode MII Interface Signal Descriptions
Symbol
Type1
Description
Input
TTL
Receive Data. The LXT980 receives data from the PHY on these pins. Data is sampled on
the rising edge of MII_RXCLK.
29
MII_RXD0
30
MII_RXD1
32
MII_RXD2
33
MII_RXD3
26
MII_RXDV
Input
TTL
Receive Data Valid. The PHY asserts this active High signal, synchronous to MII_RXCLK,
to indicate valid data on MII_RXD<3:0>.
25
MII_RXCLK
Input
TTL
Receive Clock. MII receive clock for expansion port. This is a 25 MHz clock.
24
MII_RXER
Input
TTL
Receive Error. The PHY asserts this active High signal, synchronous to MII_RXCLK, to
indicate invalid data on MII_RXD<3:0>.
22
MII_TXER
Output
TTL
Transmit Error. The LXT980 asserts this signal when an error has occurred in the transmit
data stream.
21
MII_TXCLK
Input
TTL
Transmit Clock. 25 MHz continuous input clock. Must be supplied from same source as
CLK25 system clock.
20
MII_TXEN
Output
TTL
Transmit Enable. The LXT980 drives this output High to indicate that data is being
transmitted on the MII_TXD<3:0> pins.
19
MII_TXD0
18
MII_TXD1
17
MII_TXD2
Output
TTL
Transmit Data. The LXT980 drives these outputs to transmit data to the PHY. The device
drives MII_TXD<3:0> on the rising edge of MII_TXCLK, when MII_TXEN is High.
16
MII_TXD3
14
MII_COL
Input
TTL
Collision. The PHY asserts this active High signal to notify the LXT980 that a collision
has occurred.
13
MII_CRS
Input
TTL
Carrier Sense. The PHY asserts this active High signal to notify the LXT980 that the PHY
is transmitting or receiving.
1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for MAC mode.
12
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 4.
Pin
Inter-Repeater Backplane Signal Descriptions
Symbol
Type1
Description
Common IRB Signals
199
MMSTRIN
63
MMSTROUT
TTL Input
PD, NC
TTL Output
Management Master Input. The Management Master (MM) daisy chain ensures that
collisions are counted correctly in multi-board applications. Attach the MMSTRIN input
of each device to the MMSTROUT output of the previous device. Ground MMSTRIN of
the first or only device.
Management Master Output. MM daisy chain output. In hot-swap applications, a
1 kΩ - 3 kΩ resistor can be used as a by-pass between MMSTRIN and MMSTROUT.
100 Mbps IRB Signals (Refer to Figure 22 on page 57)
36
IR100CFS
Analog I/O
100 Mbps IRB Collision Force Sense. A three-level signal that determines number of
active ports on the “logical” repeater. High level (5V) indicates no ports active; Mid level
(approx. 2.8V) indicates one port active; Low level (0V) indicates more than one port
active, resulting in a collision. This signal requires a 240Ω pull-up resistor, and connects
between chips on the same board.
37
IR100CFSBP
Analog I/O
NC
100 Mbps IRB Collision Force Sense - Backplane. This three-level signal functions
the same as IRCFS; however, it connects between chips with ChipID=0, on different
boards. IR100CFSBP requires a single 91Ω pull-up resistor on each stack.
38
IR100SNGL
Schmitt
CMOS I/O
PU
100 Mbps Single Driver State. This active Low signal is asserted by the device with
ChipID = 000 when a packet is being received from one or more ports. This signal
should not be connected between boards.
40
IR100COL
Schmitt
CMOS I/O
PU
100 Mbps Multiple Driver State. This active Low signal is asserted by the device with
ChipID = 000 when a packet is being received from more than one port (collision). It
should not be connected between boards.
TTL Output
OD
100 Mbps IRB Driver Enable. This output provides directional control for an external
bidirectional transceiver (‘245) used to buffer the 100 Mbps IRB in multi-board
applications. It must be pulled up by a 330Ω resistor. When there are multiple devices
on one board, tie all IR100DEN outputs together. If IR100DEN is tied directly to the DIR
pin on a ‘245, attach the on-board IR100DAT, IR100CLK, and IR100DV signals to the
“B” side of the ‘245, and connect the off-board signals to the “A” side of the ‘245.
41
IR100DEN
42
IR100DV
Schmitt
CMOS I/O
OD, PU
100 Mbps IRB Data Valid. This active Low signal indicates port activity on the
repeater. IR100DV frames the clock and data of the packet on the backplane. This
signal requires a 120Ω pull-up resistor.
43
44
45
46
49
IR100DAT0
IR100DAT1
IR100DAT2
IR100DAT3
IR100DAT4
Tri-state
Schmitt
CMOS I/O
PU
100 Mbps IRB Data. These bidirectional signals carry data on the 100 Mbps IRB. Data
is driven on the falling edge and sampled on the rising edge of IR100CLK. These
signals can be buffered between boards.
52
IR100CLK
Tri-state
Schmitt
CMOS I/O
PD
100 Mbps IRB Clock. This bidirectional, non-continuous, 25 MHz clock is recovered
from received network traffic. Schmitt triggering is used to increase noise immunity. This
signal must be pulled to VCC when idle. One 1 kΩ pull-up resistor on both side of a ‘245
buffer is recommended.
56
IR100ISO
TTL Output
100 Mbps Stack Backplane Isolate. This output allows one LXT980 per Board the
ability to enable or disable an external bidirectional transceiver (‘245). Attach the output
to the Enable input of the ‘245. The output is driven High (disable) to isolate the
100 Mbps IRB.
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PU = Input contains pull-up.
PD = Input contains pull-down.
I/O = Input / Output.
OD = Open Drain
TTL = Transistor-Transistor Logic
Even if the IRB is not used, required pull-up resistors must be installed as listed above.
Datasheet
13
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 4.
Pin
Inter-Repeater Backplane Signal Descriptions (Continued)
Symbol
Type1
Description
10 Mbps IRB Signals (Refer to Figure 23 on page 57)
10 Mbps IRB Data. Carries data on the 10 Mbps IRB. Data is driven and sampled on
the rising edge of the corresponding IRCLK. This signal must be pulled up by a 330Ω
resistor. Between boards, this signal can be buffered.
9
IR10DAT
CMOS
I/O
OD, PD
10
IR10CLK
Tri-state
Schmitt
CMOS I/O
PD
10 Mbps IRB Clock. This bidirectional, non-continuous, 10 MHz clock is recovered
from received network traffic. During idle periods, the output is high-impedanced.
Schmitt triggering is used to increase noise immunity.
6
IR10DEN
TTL Output
OD
10 Mbps IRB Driver Enable. This output provides directional control for an external
bidirectional transceiver (‘245) used to buffer the IRBs in multi-board applications. It
must be pulled up by a 330Ω resistor. When there are multiple devices on one board, tie
all IR10DEN outputs together. If IR10DEN is tied directly to the DIR pin on a ‘245, attach
the on-board IR10DAT, IR10CLK and IR10ENA signals to the “B” side of the ‘245, and
connect the off-board signals to the “A” side of the ‘245.
8
IR10ENA
CMOS I/O
OD, PU
10 Mbps IRB Enable. This active Low output indicates carrier presence on the IRB. A
330Ω pull-up resistor is required to pull the IR10ENA output High when the IRB is idle.
When there are multiple devices, tie all IR10ENA outputs together. This signal may be
buffered between boards.
3
IR10COL
CMOS I/O
OD, PU
10 Mbps IRB Collision. This output is driven Low to indicate that a collision has
occurred on the 10 Mbps segment. A 330Ω resistor is required in each box to pull this
signal High when there is no collision. This signal should not be connected between
boards and it may not be buffered.
4
IR10COLBP
CMOS I/O
OD, NC
10 Mbps IRB Collision - Backplane. This active Low output has the same function as
IR10COL, but is used between boards. Attach this signal only from the device with
ChipID = 0 to the backplane or connector, without buffering. The output must be
pulled up by one 330Ω resistor per system.
1
IR10CFS
Analog I/O
OD
10 Mbps IRB Collision Force Sense. This three-state analog signal indicates transmit
collision when driven Low. IR10CFS requires a 680Ω, 1% pull-up resistor. Do not
connect this signal between boards and do not buffer.
5
IR10CFSBP
Analog I/O
OD, NC
10 Mbps IRB Collision Force Sense - Backplane. Functions the same as IR10CFS,
but connects between boards. Attach this signal only from the device with ChipID = 0 to
the backplane or connector, without buffering. This signal requires one 330Ω, 1% pullup resistor per system.
TTL Input
PD
MAC Active. A TTL-level signal. Active High input allows external ASICs to participate
in 10 Mbps IRB. Driving data onto the IRB requires that the external ASIC assert
MACACTIVE High for one clock cycle, then assert IR10ENA Low. ASIC monitors
IR10COL (active Low) for collision. By using MACACTIVE, the repeater—not the
MAC—drives the three-level IR10CFS pin.
TTL Output
10 Mbps IRB Isolate. By using IR10 IS, one LXT980 per board can enable or disable
an external bidirectional transceiver (‘245). Attach the output to the Enable input of the
‘245. Driven High (disable) to isolate the 10 Mbps IRB.
TTL I/O
PD
Hold Collision for 10 Mbps mode. This active High signal is driven by the device with
ChipID = 0 to extend a non-local transmit collision to other devices on the same board.
The HOLDCOL signals from different boards should NOT be attached together.
79
MACACTIVE
55
IR10 ISO
80
HOLDCOL
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PU = Input contains pull-up.
PD = Input contains pull-down.
I/O = Input / Output.
OD = Open Drain
TTL = Transistor-Transistor Logic
Even if the IRB is not used, required pull-up resistors must be installed as listed above.
14
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 5.
Pin
Twisted-Pair Port Signal Descriptions
Symbol
149, 151
TPOP1, TPON1
136, 138
TPOP2, TPON2
121, 123
Type
Analog
Output
TPOP3, TPON3
108, 110
TPOP4, TPON4
146, 147
TPIP1, TPIN1
133, 134
TPIP2, TPIN2
Analog
118, 119
TPIP3, TPIN3
Input
105, 106
TPIP4, TPIN4
Table 6.
Pin
153, 154
FIBOP1, FIBON1
140, 141
FIBOP2, FIBON2
125, 126
FIBOP3, FIBON3
112, 113
FIBOP4, FIBON4
157, 156
FIBIP1, FIBIN1
144, 143
FIBIP2, FIBIN2
129, 128
FIBIP3, FIBIN3
116, 115
FIBIP4, FIBIN4
155
SIGDET1
142
SIGDET2
127
SIGDET3
114
SIGDET4
Pin
Twisted-Pair Outputs - Ports 1 through 4. These pins are the positive and
negative outputs from the respective ports’ twisted-pair line drivers. These pins
can be left open when not used.
Twisted-Pair Inputs - Ports 1 through 4. These pins are the positive and
negative inputs to the respective ports’ twisted-pair receivers. These pins can be
left open when not used.
Fiber Port Signal Descriptions
Symbol
Table 7.
Description
Type
Description
PECL Output
Fiber Outputs - Ports 1 through 4. These pins are the positive and
negative outputs from the respective ports’ PECL drivers. These pins can be
left open when not used.
PECL Input
Fiber Inputs - Ports 1 through 4. These pins are the positive and negative
inputs to the respective ports’ PECL receivers. These pins can be left open
when not used.
PECL Input
Signal Detect - Ports 1 through 4. Signal detect for the fiber ports. These
pins can be left open when not used.
Serial Management Interface Signal Descriptions
Symbol
58
RECONFIG
62
SER_MATCH
59
SRX
Type1
Description
TTL Input PD,
NC
Reconfigure. This input controls the driving of the clock signal on the high-speed
Serial Management Interface (SERCLK). When this input is High, the LXT980
drives SERCLK with a 625 kHz output. When this input is Low, SERCLK is an input
to the LXT980. In addition, a Low-to-High transition on RECONFIG causes the
LXT980 to drive 13 continuous 0s on the SMI, causing a re-arbitration to occur.
TTL Output
Serial Match. The LXT980 device with ChipID = 0 asserts this active High output
whenever it detects a message on the SMI that matches the local Hub ID. Refer to
Figure 11 on page 43.
TTL Input, PD
Serial Receive. Receive data input for high-speed serial management interface.
Must be tied to STX externally. SRX is sampled on the rising edge of SERCLK.
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PU = Input contains pull-up.
PD = Input contains pull-down
OD = Open Drain
TTL = Transistor-Transistor Logic.
Datasheet
15
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 7.
Pin
Serial Management Interface Signal Descriptions (Continued)
Symbol
Type1
Description
60
STX
TTL Output
OD
Serial Transmit. Transmit data output for high-speed serial management interface.
Must be tied to SRX externally. Data transmitted on STX is compared with data
received on SRX. In the event of a mismatch, STX is put in the high impedance
state. STX is driven on the falling edge of SERCLK.
61
SERCLK
Tri-state TTL
I/O, PD
Serial Clock. Clock for serial management interface. Depending on RECONFIG,
this pin is either a 625 kHz output or a 0 to 2 MHz input.
198
ARBIN
TTL Input, PD,
NC
64
ARBOUT
65
ARBSELECT
66
MGR_PRES
TTL Output
NC
TTL Input
PU
TTL Input
NC, PU
Arbitration In/Out. Used with Chain Arbitration. If used, tie ARBIN to ARBOUT of
the previous device. ARBIN at the top of the daisy chain can be connected to
ground or to ARBOUT of the SCC. If unused, tie ARBIN High.
Arbitration Mode Select.
0 = EEPROM based, 1 = chain based.
Manager Present. This signal is sensed at power up and hardware reset. If the
signal is High, it indicates that no local manager is present, and the LXT980
enables all ports and sets all LEDs to operate in “hardware mode”. If it is Low,
indicating that a manager is present, the LXT980 disables all ports, pending control
of network manager.
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PU = Input contains pull-up.
PD = Input contains pull-down
OD = Open Drain
TTL = Transistor-Transistor Logic.
Table 8.
Pin
LED Signal Descriptions
Symbol
208
LEDSEL0
207
LEDSEL1
181
PORT1_LED1
177
PORT2_LED1
173
PORT3_LED1
166
PORT4_LED1
162
PORT5_LED1
180
PORT1_LED2
176
PORT2_LED2
172
PORT3_LED2
165
PORT4_LED2
161
PORT5_LED2
179
PORT1_LED3
175
PORT2_LED3
171
PORT3_LED3
164
PORT4_LED3
160
PORT5_LED3
85
COL10_LED
Type1
TTL Input
PD
TTL
Output
TTL
Output
TTL
Output
TTL
Output
Description
LED Mode Select. Must be static.
00 = Mode 1, 01 = Mode 2, 10 = Mode 3
LED Driver 1 - Ports 1 through 5. Programmable LED driver.
Active Low. See “Port LEDs” on page 32.
LED Driver 2 - Ports 1 through 5. Programmable LED driver.
Active Low. See “Port LEDs” on page 32.
LED Driver 3 - Ports 1 through 5. Programmable LED driver.
Active Low. See “Port LEDs” on page 32.
10 Mbps Collision LED Driver. Active Low indicates collision on 10Mbps segment.
1. PD = Input contains pull-down.
TTL = Transistor-Transistor Logic
16
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 8.
Pin
LED Signal Descriptions (Continued)
Symbol
Type1
Description
86
COL100_LED
TTL
Output
100 Mbps Collision LED Driver. Active Low indicates collision on 100 Mbps
segment.
87
MGR_LED
TTL
Output
Manager Present LED Driver. Active Low indicates Manager present.
90
ACT10_LED
TTL
Output
10 Mbps Activity LED Driver. Active Low indicates activity on 10 Mbps segment.
91
ACT100_LED
TTL
Output
100 Mbps Activity LED Driver. Active Low indicates activity on 100 Mbps segment.
92
FAULT_LED
TTL
Output
Fault LED Driver. Active Low indicates global fault.
98
RPS_LED
TTL
Output
Redundant Power Supply LED Driver. Active Low indicates RPS fault.
1. PD = Input contains pull-down.
TTL = Transistor-Transistor Logic
Table 9.
Pin
Power Supply and Indication Signal Descriptions
Type1
Symbol
Description
12, 28, 35,
51, 57, 76,
84, 89, 96,
170, 201,
203-206
VCC
Digital
Power Supply Inputs. Each of these pins must be connected to a common
+5 VDC power supply. A de-coupling capacitor to digital ground should be
supplied for every one of these pins.
2, 11, 34,
50, 75, 82,
83, 88, 93,
158, 159,
163, 167,
174, 178,
200, 202
GND
Digital
Ground. Connect each of these pins to digital ground.
GND (LXT980
only)
Digital
Ground. Connect this pin to digital ground.
Note: For LXT980A, refer to Table 11 on page 18.
94, 169
VCCV
Analog
VCO Supply Inputs. Each of these pins must be connected to a common
+5 VDC power supply. A de-coupling capacitor to GNDV should be supplied for
every one of these pins.
95, 168
GNDV
Analog
VCO Ground.
111, 124,
139, 152
VCCT
Analog
Transmitter Supply Inputs. Each of these pins must be connected to a
common +5 VDC power supply. A de-coupling capacitor to GNDT should be
supplied for every one of these pins.
109, 122,
137, 150
GNDT
Analog
Transmitter Ground.
107, 120,
135, 148
VCCR
Analog
Receiver Supply Inputs. Each of these pins must be connected to a common
+5 VDC power supply. A de-coupling capacitor to GNDR should be supplied for
every one of these pins
104, 117,
132, 145,
GNDR
Analog
Receiver Ground.
74
1. PU = Input contains pull-up.
PD = Input contains pull-down.
TTL = Transistor-Transistor Logic.
Datasheet
17
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 9.
Power Supply and Indication Signal Descriptions (Continued)
Pin
Type1
Symbol
131
RBIAS
27, 130
GNDA
Analog
Analog
78
RPS_PRES
TTL Input
PD
77
RPS_FAULT
TTL Input
PU
Description
RBIAS. Used to provide bias current for internal circuitry. The 100 µA bias
current is provided through an external 22.1 kΩ, 1% resistor to GNDA.
Analog Ground.
Redundant Power Supply Present. Active High input indicates presence of
redundant power supply. Tie Low if not used.
Redundant Power Supply Fault. Active Low input indicates redundant power
supply fault. The state of this input is reflected in the RPS_LED output (refer to
Table 8 on page 16). Tie High if not used.
1. PU = Input contains pull-up.
PD = Input contains pull-down.
TTL = Transistor-Transistor Logic.
Table 10. PROM Interface Signal Descriptions
Type1
Pin
Symbol
67
PROM_CLK
Tri-State TTL I/O,
PD
68
PROM_CS
Tri-State
TTL Output
PROM Chip Select. Selects EPROM. Active High signal driven by chip
with ID of 0.
69
PROM_DTOUT
Tri-State
TTL Output
PROM Data Output. Selects read instruction for EPROM. Active High
signal driven only by chip with ID of 0.
70
PROM_DTIN
TTL Input, PD
Description
PROM Clock. 1 MHz clock for reading PROM data (ChipID=0).
If a PROM is not used, this pin must be tied Low.
PROM Data Input. If PROM not used, input tied Low or High.
1. PD = Input contains pull-down.
TTL = Transistor-Transistor Logic.
Table 11. Miscellaneous Signal Descriptions
Pin
Symbol
Type1
Description
Reset. This active Low input causes internal circuits, state machines, and
counters to reset (address tracking registers do not reset). On power-up,
devices should not be brought out of reset until the power supply has stabilized
and reached 4.5V. When there are multiple devices, it is recommended that all
be supplied by a common reset that is driven by an ‘LS14 or similar device.
53
RESET
Schmitt CMOS
Input
NC
54
CLK25
Schmitt CMOS
Input
25 MHz system clock. Drive with MOS levels.
71
CHIPID0
72
CHIPID1
TTL Input, PD
Chip ID. These pins assign unique ChipIDs to as many as eight devices on a
single board. One device on each board must be assigned ChipID = 0.
73
CHIPID2
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PD = Input contains pull-down.
TTL = Transistor-Transistor Logic.
18
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 11. Miscellaneous Signal Descriptions (Continued)
Pin
Symbol
Type1
Description
74
AUTO_BLINK
(LXT980A only)
TTL Input,
PD
AUTO_BLINK. Setting this pin High disables the Blink indication that shows a
“No Link” condition for PortnLED3.
Note: For LXT980, refer to Table 9 on page 17.
81
IRQ
TTL Output
OD
Interrupt request. Active Low interrupt. Refer to Table 70 and Table 71 for
criteria and clearing options.
7, 15,
23, 31,
39, 47,
48, 97,
101,
102,
103,
NC
-
No Connects. Leave these pins unconnected.
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PD = Input contains pull-down.
TTL = Transistor-Transistor Logic.
Datasheet
19
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
2.0
Functional Description
2.1
Introduction
As a fully integrated IEEE 802.3 repeater capable of 10 Mbps and 100 Mbps functionality, the
LXT980 is a very versatile device allowing great flexibility in Ethernet design solutions. Figure 3,
“Typical Unmanaged 100 Mbps Repeater Architectures” on page 21, and Figure 5 show some
typical applications, and Figure 6 shows a more complete I/O circuit. Refer to “Application
Information” on page 48 for specific circuit implementations.
This multi-port repeater provides four 10BASE-T/100BASE-TX/100BASE-FX ports. In addition,
there is a bidirectional Media Independent Interface (MII) expansion port that may be connected to
either a 10/100 MAC, or to a 100 Mbps PHY.
The LXT980 provides two repeater state machines and two Inter-Repeater Backplanes (IRB) on a
single chip—one for 10 Mbps operation and one for 100 Mbps operation. The 100 Mbps repeater
fully meets IEEE 802.3 Class II requirements. Each port’s operating speed may be selected
independent of the other ports. The auto-negotiation capability of the LXT980 allows it to poll
connected nodes and configure itself accordingly.
The LXT980 incorporates full RMON support by providing on-chip counters and hardware
assistance for a fully managed environment. The segmented backplane simplifies dual-speed
operation, and allows multiple devices to be stacked and function as one logical repeater. Up to 240
ports (192 TP ports and 48 MII ports) can be supported in a single cascade.
20
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 3. Typical Managed Repeater Architectures
LXT980
LXT980
10BASE-T
10/100
LXT980 E’net10/100
Repeater
PHY
10BASE-T
10 Mbps
Backplane
10 Mbps
Buffer
Backplane
Repeater
PHY
10 Mbps
10BASE-T E’net10/100
Backplane
Repeater
E’net PHY
100 Mbps
100BASE-T
10/100
Backplane
Repeater
PHY
100 Mbps
100BASE-T E’net10/100
10M Backplane
100M Backplane
10M Backplane
Chassis
Backplanes
Backplane
100 Mbps
Backplane
Repeater
PHY
100BASE-X E’net10/100
Repeater
E’net PHY
Device
10/100
Management
E’net10/100
PHY
Device
Serial Port
Management
Device
E’net10/100
PHY
Serial Port
Management
E’net PHY
Serial Port
10/100
E’net10/100
PHY
MII
RMON &
E’net10/100
PHY
SNMP
MII
RMON &
E’net PHY
Counters
SNMP
MII
RMON &
Counters
SNMP
LED Drivers
Counters
LED Drivers
LED Drivers
Buffer
100M Backplane
Serial
Management
SCC (8530)
MII-to-MII
Bridge
(Any 2 LXT980s)
Figure 4. Typical Unmanaged 100 Mbps Repeater Architectures
LXT980
100M Backplane
Chassis
Backplane
Buffer
100M Backplane
10 Mbps
10BASE-T
10/100
LXT980
Backplane
Repeater
E’net PHY
10 Mbps
10BASE-T
10/100
LXT980
Backplane
Repeater
E’net PHY
10 Mbps
10BASE-T
10/100
100 Mbps
100BASE-T
10/100
Backplane
Repeater
E’net PHY
Backplane
Repeater
E’net PHY
100 Mbps
100BASE-T
10/100
Backplane
Repeater
E’net PHY
100 Mbps
10/100
Device 100BASE-X
10/100
Backplane
Repeater
E’net PHY
Management
E’net PHY
Serial Port
Device
10/100
Management
E’net PHY
Serial Port
Device
10/100
10/100
Management
E’net PHY
Serial Port
E’net PHY
10/100
MII
RMON &
E’net PHY
SNMP
10/100
MII
RMON &
Counters
E’net PHY
SNMP
LED Drivers
MII
RMON &
Counters
LED Drivers
LED Banks
Datasheet
SNMP
Counters
LED Drivers
21
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 5. Typical Hybrid Switch/Repeater Application
LXT980
10 Mbps
Backplane
10M Backplane
100M Backplane
10 Mbps
10BASE-T
10/100
Backplane
Repeater
E’net PHY
100 Mbps
100BASE-T
10/100
Backplane
Repeater
E’net PHY
100 Mbps
Backplane
Serial Port
Serial
Management
to SCC (8530)
10BASE-T
10/100
LXT980 E’net PHY
Repeater
100BASE-X
10/100
Repeater
E’net PHY
Device
10/100
Management
E’net PHY
Serial Port
MII
MII Switch Connections
1 each for 10 M and 100M
MII
LED Drivers
Device
Management
10/100
E’net PHY
10/100
E’net PHY
RMON &
SNMP
Counters
RMON &
SNMP
Counters
10/100
E’net PHY
LED Drivers
22
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 6. Typical Application Block Diagram
Xfmrs
Serial Mgmt I/F
SCC
SRX
STX
8530
LXT980
RECONFIG
MG_PRSNT
MII_RXCLK
MII_RXD<3:0>
MII_RXDV
MII_RXER
MII_COL
MII_CRS
MII_TXCLK
MII_TXD<3:0>
MII_TXEN
MII_TXER
Input allows MAC
to drive IRB
(10M Only)
MACACTIVE
ChipID
assignment
CHIPID2
CHIPID1
CHIPID0
HubID
assignment
MMSTRIN
MMSTROUT
FO2
FO3
FO4
Resistor
Packs
VCC
PORT2_LED1
PORT2_LED2
PORT2_LED3
2 Independent IRBs, 10 & 100
PORT3_LED1
PORT3_LED2
PORT3_LED3
IRCOL
IRCFS
HOLDCOL
Local IRB
to onboard
LXT980
IRB10
IRDEN
ISOLATE
IRCOLBP
IRCFSBP
Port LEDs
PORT4_LED1
PORT4_LED2
PORT4_LED3
IRENA
IRDAT
IRCLK
’245
Local IRB
4 100 M
FO Ports
PORT1_LED1
PORT1_LED2
PORT1_LED3
to next
LXT980
InterModule
IRB to
stack
connector
Fiber Module
FIBOP1
FIBON1
FIBIP1
FIBIN1
SIGDET1
PROM_CS
PROM_DTOUT
PROM_CLK
PROM_DTIN
PROM
4 TP Ports
Independently
switchable to
either 10 or
100 M
backplane
TP2
TP3
TP4
SERCLK
MII
(Port 5,
PHY Mode)
RJ45s
TPOP1
TPON1
TPIP1
TPIN1
PORT5_LED1
PORT5_LED2
PORT5_LED3
ACT10_LED
COL10_LED
ACT100_LED
COL100_LED
MGR_LED
RPS_LED
FAULT_LED
Segment LEDs
Global LEDs
IRB100
Inter-Module
IRB
Datasheet
23
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
2.1.1
TP/FX Port Configuration
The LXT980 reads the hardware configuration pins at power-up, hardware reset, or software reset
(but not at repeater reset), to determine operating conditions for each of its twisted-pair (TP) or
fiber (FX) ports. Each port has its own configuration pins so that it can be individually configured.
Software can monitor or change the configuration through the Port Speed Control Register (see
Table 61 on page 85). The four possible configurations for each port are summarized in Table 12.
Table 12. Manual Speed Selection
2.1.1.1
SPD1
SPD0
Speed Selection
0
0
Allow 10/100 auto-negotiation/parallel
detection on copper media
0
1
Force port to 10BASE-T mode
1
0
Force port to 100BASE-FX mode
1
1
Force port to 100BASE-TX mode
Forced Operation
A port can be directly configured to operate in one of three modes: 100FX, 100TX, or 10BT. When
a port is configured for forced operation via hardware or software, it immediately begins operating
in the selected mode. Forced operation is the only way to enable 100FX operation. All links are
established as half-duplex only. As a repeater, the LXT980 cannot support full-duplex operation.
2.1.1.2
Auto-Negotiation
Any port can be configured to establish its link via auto-negotiation. The port and its link partner
establish link conditions by exchanging Fast Link Pulse (FLP) bursts. Each FLP burst contains 16
bits of data that advertise the port’s capabilities. The FLP bursts sent by the port are maintained in
its Auto-negotiation Advertisement Register (Table 81 on page 93). The link partner’s abilities are
stored in the auto-negotiation link partner register (Table 79 on page 92). Status can be observed in
the respective Auto-negotiation Status Register (Table 80 on page 93). Each port has its own
advertisement, link partner advertisement, and Auto-negotiation Status Registers.
When auto-negotiation is enabled, the capabilities advertised by the LXT980 are predetermined
and cannot be changed; the advertisement register is read only, except for bit 13 (remote fault). The
LXT980 always advertises 100 half duplex and 10 half duplex. it never advertises 10 or 100 fullduplex.
If the link partner does not support auto-negotiation, the LXT980 determines link state by listening
for 100 Mbps IDLE symbols or 10 Mbps link pulses. If it detects either of these signals, it
configures the port and updates the status registers appropriately.
2.1.1.3
Link Establishment and TP Port Connection
Once a port establishes link, the LXT980 automatically connects it to the appropriate repeater state
machine. If link loss is detected and auto-negotiation is enabled, the port returns to the autonegotiation state.
2.1.1.4
Changing Port Speed
In order to change port speed while operating, the following sequence is required:
24
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
• Disable the port(s) to be changed.
• Set Port Speed Control Register to desired speed.
• Perform a repeater reset (LXT980 will not read hardware configuration pins. Refer to Table 69
on page 88.)
• Re-enable the port(s).
Note:
2.1.2
The entire repeater must be reset in order to change the port speed on any port.
MII Port Configuration
At power-up or reset, the MII is configured via external pins to one of the three modes of operation:
• 100 Mbps, PHY side of interface—for interfacing to 100 Mbps MAC.
• 10 Mbps, PHY side of interface—for interfacing to 10 Mbps MAC.
• 100 Mbps, MAC side of interface—to drive fifth 100 Mbps port via an LXT970 or other MIIcompliant PHY. In this mode, the external PHY must be configured as either a 100-TX or 100FX connection.
2.1.3
Interface Descriptions
The LXT980 provides four network interface ports. Each port provides both a twisted-pair and a
fiber interface. The twisted-pair interface directly supports 100BASE-TX (100TX) and 10BASE-T
(10T) Ethernet applications. A common termination circuit is used for both media types. The fiber
interface indirectly supports 100BASE-FX (100FX) media through a PECL connection to an
external fiber-optic transceiver. Both interfaces fully comply with IEEE 802.3 standards.
2.1.3.1
Twisted-Pair Interface
The twisted-pair interface for each port consists of two differential signal pairs — one for transmit
and one for receive. The transmit signal pair is TPOP/TPON, the receive signal pair is TPIP/TPIN.
The twisted-pair interface for a given port is enabled when the port configuration is set to autonegotiate, forced 10T or forced 100TX operation. The twisted-pair interface is disabled when
100FX is selected.
The transmitter is current driven and requires magnetics with 2:1 turns ratio. A 400 Ω resistive load
should be placed across the TPOP/N pair, in parallel with the magnetics. The center tap of the
primary side of the transmit winding must be tied to a quiet VCC for proper operation. When the
twisted-pair interface is disabled, the transmitter outputs are tri-stated.
The receiver requires magnetics with a 1:1 turns ratio, and a load of 100 Ω. When the twisted-pair
port is enabled, the receiver actively biases its inputs to approximately 2.8V. When the twisted-pair
interface is disabled, no biasing is provided. A 4 kΩ load is always present across the TPIP/TPIN
pair.
When used in 100TX applications, the LXT980 sends and receives a continuous, scrambled
125 Mbaud MLT-3 waveform on this interface. In the absence of data, IDLE symbols are sent and
received in order to keep the link up.
Datasheet
25
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
When used in 10T applications, the LXT980 sends and receives a non-continuous, 10 Mbaud
Manchester-encoded waveform. To maintain link during idle periods, the LXT980 sends link
pulses every 16 ms, and expects to receive them every 10 to 20 ms. Each 10BASE-T port
automatically detects and sends link pulses, and disables its transmitter if link pulses are not
detected. Each receiver can also be configured to ignore link pulses, and leave its transmitter
enabled all the time (link pulse transmission cannot be disabled). Each 10BASE-T port can detect
and automatically correct for polarity reversal on the TPIP/N inputs. The 10BASE-T interface
provides integrated filters using Intel’s patented filter technology. These filters facilitate low-cost
system designs which meet EMI requirements.
In applications where the twisted-pair interface is not used, the inputs and outputs may be left
unconnected.
2.1.3.2
Fiber Interface
Each fiber interface consists of the FIBOP/FIBON (transmit) and FIBIP/FIBIN (receive) signal
pair. Each interface also provides a “Signal Detect” input which can be tied to the corresponding
output on the fiber transceiver for determining signal quality.
The transmit pair is biased to approximately 1.5V and generally must be AC-coupled to the
transceiver. The receive pair will accommodate an input bias in the 2V- 5V range, and can be DCcoupled to the transceiver. Refer to Figure 20 on page 55 for a typical interface circuit.
The fiber interface for each port is enabled when the speed select is set to 100FX, and is disabled in
all other cases. When a fiber port is disabled, its outputs are pulled to ground, and its inputs are tristated. The input and output pins on unused fiber ports may be left unconnected.
Each fiber port transmits and receives a continuous, 1V peak-to-peak, non-scrambled, NRZI
waveform. The LXT980 does not support scrambling or auto-negotiation on the fiber interface.
Remote Fault Reporting
The SD pin detects signal quality and reports a remote fault if the signal quality starts to degrade.
Loss of signal quality also blocks any further data from being received and causes loss of the link.
The remote fault code consists of 84 consecutive 1s followed by a single ‘0’, and is transmitted at
least three times. The LXT980 transmits the remote fault code and sets the associated interrupts
when both of the following conditions are true:
• Fiber mode is selected.
• Signal Detect indicates no signal, or the receive PLL cannot lock.
2.1.3.3
Media Independent Interface
The LXT980 supports a standard Media Independent Interface (MII). This interface can be
programmed to operate as either the PHY or the MAC side of the interface.
When the MII is operating as the MAC side of the interface (MAC mode), it always operates at
100 Mbps. When the MII is operating as the PHY side of the interface (PHY mode), it can be
programmed to operate either at 10 Mbps or at 100 Mbps. Once the MII is configured, the LXT980
automatically connects it to the corresponding internal repeater.
Note:
26
The MII does not support auto-negotiation, auto-speed, auto-link, or partition functions.
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
On the LXT980, the MII always operates as a nibble-wide (4B) interface. Symbol mode (5B
interface) is not supported on the LXT980 MII.
2.1.3.4
Serial Management Interface
The Serial Management Interface (SMI) provides system access to the status, control and statistic
gathering abilities of the LXT980. This interface is designed to allow multiple devices to be
managed from a single multi-drop (daisy-chain) connection, and to use the minimum number of
signals (2) for ease of system design.
The interface itself consists of two digital NRZ signals — clock and data. Refer to Table 7 on
page 15 for serial management I/F pin assignments and signal descriptions. Data is framed into
HDLC-like packets, with a start/stop flag, header and CRC field for error checking. Zero-bit
insertion/removal is used. The interface can operate at any speed from 0 to 2 Mbps.
Address assignment is provided via one of two arbitration mechanisms which are activated
whenever the device is powered up or reset/reconfigured. Refer to the section “Serial Management
I/F” on page 40.
2.1.4
Repeater Operation
The LXT980 contains two internal repeater state machines — one operating at 10 Mbps and the
other at 100 Mbps. The LXT980 automatically switches each port to the correct repeater, once the
operational state of that port has been determined. Each repeater connects all ports configured to
the same speed (including the MII), and the corresponding Inter-Repeater Backplane. Both
repeaters perform the standard jabber, partition, and isolate functions as required.
2.1.4.1
100 Mbps Repeater Operation
The LXT980 contains a complete 100 Mbps Repeater State Machine (100RSM) that is fully IEEE
802.3 Class II compliant. Any port configured for 100 Mbps operation is automatically connected
to the 100 Mbps Repeater. This includes any of the four media ports if they are configured for
100TX or 100FX operation, and the MII port if it is configured for 100 Mbps operation.
The 100 Mbps RSM has its own Inter-Repeater Backplane (100IRB). Multiple LXT980s can be
cascaded on the 100IRB and operate as one repeater segment. Data from any port will be
forwarded to any other port in the cascade. The 100IRB is a 5-bit symbol-mode interface. It is
designed to be stackable.
The LXT980 maintains a complete set of statistics for its local repeater segment as long as the MII
port is configured for 100 Mbps operation. These are accessible through the high-speed
management interface.
The LXT980 performs the following 100 Mbps repeater functions:
• Signal amplification, wave-shape restoration, and data-frame forwarding.
• Handling of received code violations. The LXT980 will substitute the “H” symbol for all
invalid received codes.
• SOP, SOJ, EOP, EOJ delay < 46BT; class II compliant (see Figure 26).
• Collision Enforcement. During a 100 Mbps collision, the LXT980 drives a 1010 jam signal
(encoded as Data 5 on TX links) to all ports until the collision ends. There is no minimum
enforcement time.
Datasheet
27
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
• Partition. The LXT980 partitions any port participating in excess of 60 consecutive collisions
or one long collision approximately 575.2 µs long. Once partitioned, the LXT980 continues
monitoring and transmitting to the port, but does not repeat data received from the port until it
properly un-partitions.
• Un-partition. The LXT980 supports two un-partition algorithms. The default algorithm, which
complies with the IEEE 802.3 specification, un-partitions a port only when data can be
transmitted to the port for 450-560 bit times without a collision on that port.
• The alternate un-partition algorithm is available through the management interface. The
alternate algorithm will un-partition a port on either transmit or receive of at least 450-560 bits
without collision on the partitioned port.
• Isolate. The LXT980 isolates any port transmitting more than two successive false carrier
events. A false carrier event is defined as a packet not starting with a /J/K symbol pair. Note:
this is not the same as “100IRB isolate,” which involves segmenting the backplane.
• Un-isolate. The LXT980 will un-isolate a port that remains in the IDLE state for 33000 +/25% BT or that receives a valid frame at least 450-500 BT in length.
• /T/R generation. The LXT980 can insert a /T/R symbol pair (End of Stream Delimiter) on any
incoming packet that does not include one. This feature is optional, and is enabled through the
management interface.
• Jabber. The LXT980 ignores any receiver remaining active more than 57,500 bit times. The
LXT980 exits this state when all jabbering receivers return to the idle condition.
The isolate and symbol error functions do not apply to the MII port.
2.1.4.2
10 Mbps Repeater Operation
The LXT980 contains a complete 10 Mbps Repeater State Machine (10RSM) that is fully IEEE
802.3 compliant. Any port configured for 10 Mbps operation is automatically connected to the
10 Mbps Repeater. This includes any of the four media ports if they are configured for 10BT
operation, and the MII port if it is configured for 10 Mbps operation.
The 10RSM has its own Inter-Repeater Backplane (10IRB). Multiple LXT980s can be cascaded on
the 10IRB and operate as one repeater segment. Data from any port will be forwarded to any other
port in the cascade. The 10IRB is 1-bit wide and runs at 10 MHz. It is designed to be stackable.
The LXT980 maintains a complete set of statistics on its repeater segment, as long as the MII port
is configured for 10 Mbps operation. These are accessible through the high-speed management
interface.
The LXT980 performs the following 10 Mbps repeater functions:
• Signal amplification, wave-shape restoration, and data-frame forwarding.
• Preamble regeneration. All outgoing packets will have a minimum of 56 bits of preamble and
8 bits of SFD.
• SOP, SOJ, EOP, EOJ delays meet requirements of IEEE 802.3 section 9.5.5 and 9.5.6.
• Collision Enforcement. During a 10 Mbps collision, the LXT980 drives a jam signal (“1010”)
to all ports for a minimum of 96 bit times and until the collision ends.
• Partition. The LXT980 will partition any port that participates in excess of 32 consecutive
collisions. Once partitioned, the LXT980 will continue monitoring and transmitting to the
port, but will not repeat data received from the port until it properly un-partitions.
28
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
• Un-partition. The LXT980 supports two un-partition algorithms. The default algorithm, which
complies with the IEEE 802.3 specification, un-partitions a port when data can be either
received or transmitted from the port for 450-560 bit times without a collision on that port.
• The LXT980 also provides an alternate un-partition algorithm, which is available through the
management interface. The alternate algorithm will un-partition a port only when data can be
transmitted to the port for 450-560 bit times without a collision on that port.
• Jabber. The LXT980 will assert a minimum-IFG idle period when any port remains actively
transmitting for longer than 40,000 to 75,000 bit times.
2.1.5
Management Support
2.1.5.1
Configuration and Status
The LXT980 provides management control and visibility of the following functions:
•
•
•
•
•
•
•
2.1.5.2
Reset and Zeroing of counters
Auto-negotiation (Control, Status, Advertisement, Link Partner)
Device and Board Configuration
LED Functions
Source Address Tracking (per port)
Source Address Matching (per chip)
Device/Revision ID
SNMP and RMON Support
The LXT980 provides SNMP and RMON support through its statistics gathering function.
Statistics are gathered on all data that flow through the device for each of the ports, including the
MII. The LXT980 also maintains statistics for either the entire 10 or 100 Mbps repeater, depending
on the speed setting of the MII port. (Two LXT980s are required to maintain statistics on both
repeaters. Since cascaded LXT980s operate as a single logical 10/100 repeater, any device in the
cascade maintains the same 10 or 100 repeater statistics as any other device). All statistics are
stored as 32- or 64-bit quantities. Per-port counters include:
2.1.5.3
Readable Frames
Readable Octets
FCS Errors
Alignment Errors
FramesTooLong
ShortEvents
Runts
Collisions
LateEvents
VeryLongEvents
DataRateMismatch
AutoPartitions
Broadcast
Multicast
SA Changes
Isolates
Symbol Errors
Source Address Management
The LXT980 provides two source address management functions for all ports: source address
tracking and source address matching. These functions allow a network manager to track source
addresses at each port, or to identify any port that sourced a particular source address.
Datasheet
29
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
2.1.6
LED Drivers
The LXT980 provides 23 LED drivers:
• 3 mode-selectable port LED drivers (15 total)
• 2 segment LED drivers (4 total)
• 4 global LED drivers
Refer to Table 8 on page 16 for LED Interface pin assignments and signal descriptions.
2.2
Requirements
2.2.1
Power
The LXT980 has four types of +5V power supply input pins (VCC, VCCV, VCCR, and VCCT).
These inputs may be supplied from a single power supply, although ferrites should be used to filter
the power going to the analog and digital power planes. As a matter of good practice, these supplies
should be as clean as possible. Specific operating recommendations are shown in the Test
Specifications section, Table 25 on page 59.
Each supply input should be decoupled to its respective ground. Refer to Table 9 on page 17 for
power and ground pin assignments, and to “Design Recommendations” on page 48.
2.2.2
Clock
A stable, external 25 MHz system clock source (CMOS) is required by the LXT980. This is
connected to the CLK25 pin. Refer to Test Specifications, Table 26 on page 59, for clock input
requirements.
2.2.3
Bias Resistor
The LXT980 requires a 22.1 kΩ, 1% resistor connecting its RBIAS input to ground.
2.2.4
Reset
At power-up, the reset input must be held low until VCC reaches at least 4.5V. An ‘LS14 or
equivalent should be used to drive reset if there are multiple LXT980 devices (See Figure 25 on
page 58).
2.2.5
PROM
An external, auto-incrementing 48-bit PROM can be used for two purposes:
• to assign a unique ID to all LXT980s on a board
• to support the EPROM-based address arbitration mechanism on the Serial Management
Interface (refer to page 44)
30
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Multiple devices on the same board can share a single common PROM. The LXT980 with ChipID
= 0 actively reads the PROM at power-up; all other LXT980s listen in. If PROM arbitration is not
used, the PROM data input signal must be tied either High or Low. Refer to Table 10 on page 18
for PROM interface pin assignments and signal descriptions.
2.2.6
Chip ID
Each LXT980 on a board requires a unique 3-bit Chip ID value asserted on these pins in order for
the Serial Management Interface (SMI) to function correctly. One LXT980 on each board must be
assigned ChipID = 0.
2.2.6.1
When Substituting a LXT983 Device
The LXT983 can be substituted in LXT980 designs for a 10/100Mbps unmanaged solution without
changing the LXT980 Chip ID pin states. The LXT980 Chip ID 0, Chip ID 1, and Chip ID 2 pins
are renamed FPS, GND, and GND respectively for the LXT983. For cascading, the first LXT983
device is addressed 000 and all others 001 as indicated by the pin names. The LXT983 requires one
chip to have the LXT980-equivalent address 000 and all other LXT983s a non-000 address.
2.2.7
Management Master I/O Link
In multiple device applications, the Management Master daisy chain (MMSTRIN/MMSTROUT)
ensures that collisions are counted correctly. Connect the MMSTRIN input to the MMSTROUT
output of the previous device, even across board boundaries. Ground the MMSTRIN input of the
first or only device in the system. In hot-swap applications, resistive bypassing can be used with a
value between 1 and 3 kΩ.
2.2.8
IRB Bus Pull-ups
Even when the LXT980 is used in a stand-alone configuration, pull-up resistors are required on the
IRB signals listed below. See Figure 22 on page 57 and Figure 23 on page 57 for sample circuits.
100 Mbps IRB
10Mbps IRB
IR100CFS
IR10DAT
IR100CFSBP
IR10ENA
IR100DV
IR10COL
IR100CLK
IR10CFS
IR10COLBP
IR10CFSBP
2.3
LED Operation
The LXT980 provides three types of LED indicators: port, segment, and global (refer to Table 8 on
page 16). Three user-selectable LED modes determine pin conditions and how particular
conditions are indicated. The LED mode is selected via the LEDSEL<1:0> pins and reflected in an
Datasheet
31
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
internal register. The LEDs generally operate under hardware control although some limited
software overrides are available. In addition to On and Off states, some LED drivers provide a
blink state output.
2.3.1
Blink Rates
Two programmable blink rates are provided. The default period for the slow blink rate is 1.6s. The
default period is 0.4s for the fast blink rate. These rates may be changed via the LED Timer
Register. The slow blink rate is defined by the upper 8 bits and the fast blink rate is defined by the
lower 8 bits of the LED Timer Register. Refer to Table 73 through Table 75 for details.
2.3.2
Power-Up and Reset Conditions
During reset or power-up, all LED drivers turn on steady and remain on for approximately 2
seconds after reset is cleared. After reset, the Collision, Activity, and Redundant Power Supply
LEDs revert to hardware control. The Global Fault and Port LEDs revert to hardware control
unless a manager is present in the system.
2.3.3
Port LEDs
Port LEDs provide status for the four twisted-pair ports and the MII port. The LXT980 has 3 LED
driver pins for each port as described in Table 8. These pins drive standard LEDs. Three userselectable modes are provided for the port LEDs. Port LED states are also affected by port speed
and auto-negotiation status, see Table 13 through Table 15.
2.3.3.1
Link Loss
During link loss, the Speed LED indicates10M, and the Partition LED indicates “No partition,”
regardless of actual partition status.
2.3.3.2
Software Overrides of Port LEDs
The Port LED Control Register allows limited software overrides of the Port LEDs. Two bits per
port provide independent control of each port. However, all three LEDs for the respective port
receive the same override (all Port n LEDs will be simultaneously set to On, Off, or Blink). Refer
to Table 69 and Table 74 for coding and bit assignments.
2.3.4
Segment LEDs
These outputs can directly drive LEDs to indicate activity and collision status on a per segment
basis. No software overrides are provided for these LED drivers, and they are not affected by LED
mode selection. Pulse stretchers are used to extend the on-time for these LEDs.
2.3.4.1
Collision LEDs
The collision LEDs turn on for approximately 120 µs when the LXT980 detects a collision on the
respective 10 Mbps or 100 Mbps segment. During the time that the collision LED is on, any
additional collisions are ignored by the collision LED logic.
32
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
2.3.4.2
Activity LEDs
The activity LEDs turn on for approximately 4 ms when the LXT980 detects any activity on the
respective 10 Mbps or 100 Mbps segment. During the time that the activity LED is on, any
additional activity is ignored by the activity LED logic.
2.3.5
Global LEDs
These LED driver outputs indicate global status conditions.
2.3.5.1
Manager Present LED
When active, this LED indicates the presence of a manager in the system. It is not affected by LED
mode selection and does not allow software overrides.
2.3.5.2
Global Fault LED
The global fault LED indicates one or more of the following conditions: any port partitioned, any
port isolated or RPS fault. How the condition is indicated depends on the LED mode as shown in
Table 13 through Table 15.
Software Overrides of the Global Fault LED
Two bits in the global LED Control Register allow software overrides to control the global Fault
LED. Refer to Table 69 on page 88 and Table 73 on page 91 for coding and bit assignments.
2.3.5.3
Redundant Power Supply LED
• The redundant power supply LED is controlled by the RPS_FLT and RPS_PRES pins. The
LED state reflects the states of these two inputs, depending on the LED mode selected as listed
in Table 13 through Table 15.
Datasheet
33
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 13. LED Mode 1 Indications
LED
Hardware Control
Operating
Mode
Software Control
On
Blink
Off
10 Mbps
operation
Link up, not partitioned
N/A
Any other
state
100 Mbps
operation
Link up, not partitioned,
not isolated
N/A
Any other
state
10 Mbps
operation
Link up, partitioned
N/A
Any other
state
100 Mbps
operation
Link up, partitioned or
isolated
N/A
Any other
state
Auto-neg
enabled
100 Mbps link up
No link,
(fast blink)1
Any other
state
Auto-neg
disabled
100 Mbps link selected,
link may be up or down
N/A
Any other
state
RPS
Any
Present, fault
N/A
Any other
state
N/A
Global
FAULT
Any
Any port partitioned, any
port isolated or RPS fault
N/A
Any other
state
Off via global LED Control
Register, address 0B1
PORTnLED1
PORTnLED2
Off via Port LED Control
Register, address 0B2
PORTnLED3
1. Setting AUTO_BLINK (Pin 74) High disables blink (LXT980A only).
Table 14. LED Mode 2 Indications
LED
Hardware Control
Operating
Mode
Software Control
On
Blink
Off
10M: Port enabled,
link up, not
partitioned
10M: Port enabled,
link up, and
partitioned
Any
100M: Port enabled,
link up, not
partitioned, and not
isolated
100M: Port enabled,
link (partitioned or
isolate)
(slow blink)
Any other state
Any
N/A
N/A
Always off
10 or 100
Mbps ops
Receive activity
(20 ms pulse)
N/A
Any other state
Auto-neg
enabled
100 Mbps link up
No link
(fast blink)1
10 Mbps link up
Auto-neg
disabled
100 Mbps selected,
link may be up or
down
N/A
10 Mbps selected,
link may be up or
down
RPS
Any
Present, no fault
Present, fault
Not present
N/A
Global
FAULT
Any
N/A
Any port partitioned,
any port isolated or
RPS fault (slow
blink)
Any other state
On, off, or slow blink via
global LED Control
Register, address 0B1
PORTnLED1
PORTnLED2
(LXT980)
PORTnLED2
(LXT980A)
PORTnLED3
On, Off or fast Blink via
Port LED Control
Register, Address 0B2
1. Setting AUTO_BLINK (Pin 74) High disables blink (LXT980A only).
34
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 15. LED Mode 3 Indications
LED
Hardware Control
Operating
Mode
Software Control
On
Blink
Off
10 Mbps
operation
Link up, not partitioned
N/A
Any other state
100 Mbps
operation
Link up, not partitioned,
not isolated
N/A
Any other state
10 or 100
Mbps ops
Receive activity
(20 ms pulse)
N/A
Any other state
Auto-neg
enabled
100 Mbps link up
No link
(fast blink)1
10 Mbps link up
Auto-neg
disabled
100 Mbps link selected,
link may be up or down
N/A
10 Mbps link
selected, link may be
up or down
Any
Present, fault
N/A
Any other state
N/A
Any
Any port partitioned,
any port isolated or
RPS fault
N/A
Any other state
Off via global LED
Control Register,
address 0B1
PORTnLED1
PORTnLED2
PORTnLED3
RPS
Global
FAULT
Off via port LED
Control Register,
address 0B2
1. Setting AUTO_BLINK (Pin 74) High disables blink (LXT980A only).
2.4
IRB Operation
The Inter Repeater Backplane (IRB) allows multiple devices to operate as a single logical repeater,
exchanging data collision status information. Each segment on the LXT980 has its own complete,
independent IRB. The backplanes use a combination of digital and analog signals as shown in
Figure 7. IRB signals can be characterized by connection type as Local (connected between
devices on the same board), Stack (connected between boards) or Full (connected between devices
on the same board and between different boards). Refer to Table 16 and Table 17 for details on
buffering and pull-up requirements, and to Figure 22 on page 57 and Figure 23 on page 57 for
application circuitry.
2.4.1
MAC IRB Access
The MACACTIVE TTL-level pin allows an external MAC or other digital ASIC to interface
directly to the 10 Mbps IRB. When the MACACTIVE pin is asserted, the LXT980 will drive the
IR10CFS and IR10CFSBP signals on behalf of the external device, allowing it to participate in
collision detection functions.
2.4.2
IRB Isolation
The ISOLATE outputs (IR10ISO and IR100ISO) are provided to control the enable pins of external
bidirectional transceivers. In multi-board applications, they can be used to isolate one board from
the rest of the system. Only one device can control these signals. The output states of these pins are
controlled by the Isolate bits in the Master Configuration Register.
Note:
Datasheet
Inter-board analog signals will be isolated internally by the device.
35
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
2.4.3
MMSTRIN, MMSTROUT
This daisy chain is provided for correct gathering of statistics in multiple-device configurations. In
multiple-board applications, this daisy chain must be maintained across boards. In stand-alone
applications, or for the first device in a chain, the MMSTRIN input must be pulled Low in order for
the management counters to work correctly.
Figure 7. IRB Block Diagram
Digital IRB Signals
Hub Board 1
Analog IRB Signals
’245
MMSTR
IN
980 ChipID = 0
ISOLATE
MMSTR
OUT / IN
980 ChipID = 1
MMSTR
OUT / IN
980 ChipID = n
MMSTR
OUT
HOLDCOL
IRDEN
MMSTR
OUT
MMSTR IN
Digital IRB Signals
Hub Board 2
Analog IRB Signals
’245
980 ChipID = 0
ISOLATE
MMSTR
OUT / IN
980 ChipID = 1
MMSTR
OUT / IN
980 ChipID = n
MMSTR
OUT
HOLDCOL
IRDEN
MMSTR
OUT
MMSTR IN
Digital IRB Signals
Hub Board n
Analog IRB Signals
’245
980 ChipID = 0
ISOLATE
MMSTR
OUT / IN
980 ChipID = 1
MMSTR
OUT / IN
980 ChipID = n
MMSTR
OUT
HOLDCOL
IRDEN
MMSTR OUT / IN
This diagram shows a single IRB. The LXT980 actually has two independent IRBs, one per speed/segment.
Digital IRB signals include IRnDAT, IRnENA and IRnCLK.
Local Analog IRB signals include IRnCOL and IRnCFS.
Inter-Board Analog IRB signals include IRnCOLBP and IRnCFSBP.
HOLDCOL is used on the 10Mbps IRB Only.
Table 16. IRB Signal Types
Connection Type
Connections Between Devices
(same board)
Connections Between Boards
Full
Connect all.
Connect using buffers.
Local
Connect all.
Do not connect.
Stack
For devices with ChipID ≠ 0, pull-up at each
device and do not interconnect.
Connect devices with ChipID = 0 between boards.
Use one pull-up resistor per stack.
Special (xxISO)
For devices with ChipID ≠ 0, leave open.
For device with ChipID = 0, connect to buffer
enable.
Do not connect.
36
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 17. IRB Signal Details
Name
Pad Type
Buffer
Pull-up
Connection Type
100 Mbps IRB Signals
IR100DAT<4:0>
Digital
Yes
No
Full
IR100CLK
Digital
Yes
1 kΩ
Full
IR100DV
Digital, Open Drain
Yes
120Ω
Full
IR100CFS
Analog
No
240Ω, 1%
Local
IR100CFSBP
Analog
No
91Ω, 1%2
Stack
IR100COL
Digital
No
No
Local
IR100SNGL
Digital
No
No
Local
1
IR100DEN
Digital, Open Drain
N/A
IR100ISO
Digital
N/A1
330Ω
Local
No
Special
10 Mbps IRB Signals
Digital, Open Drain
Yes
330Ω
Full
IR10CLK
Digital
Yes
No
Full
IR10ENA
Digital, Open Drain
Yes
330Ω
Full
IR10CFS
Analog
No
680Ω, 1%
Local
IR10CFSBP
Analog
No
330Ω, 1%
Stack
IR10COL
Analog
No
330Ω, 1%
Local
IR10COLBP
Analog
No
330Ω, 1%
Stack
IR10DEN
Digital, Open Drain
N/A1
330Ω
Local
No
Special
IR10DAT
IR10ISO
Digital
N/A
1
1. Isolate and Driver Enable signals are provided to control an external bidirectional transceiver.
2. 91Ω resistors provide greater noise immunity. Systems using 91Ω resistors are backwards stackable with systems using
100Ω resistors.
2.5
MII Port Operation
The LXT980 MII allows a MAC or PHY to directly connect into the repeater environment. The
MII port (Port 5) can operate at either 10 or 100 Mbps. The LXT980 maintains the same statistics
for this ‘Port’ as it does for the other 10/100 ports (except for illegal symbols). Utilizing two
LXT980s allows the user to have a MAC interface to both the 10 and 100 Mbps segments, in
addition to providing segment statistics for both. The LXT980 does not provide MDIO/MDC
capability, as this is provided via the serial controller interface.
Mode and speed control is provided via PORT5_SPD and PORT5_SEL pins as listed in Table 18.
Datasheet
37
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
2.5.1
PHY Mode Operation
PHY Mode is available at both 10 and 100 Mbps. It allows the LXT980 to interface to a 10 or
100 Mbps MAC. When operating at 100 Mbps, the LXT980 passes the full 56 bits of preamble
through before sending the SFD. When operating at 10 Mbps, the LXT980 sends data across the
MII starting with the 8-bit SFD (no preamble bits).
2.5.2
MAC Mode Operation
MAC Mode (available at 100 Mbps only) allows the user to attach an additional PHY to the
LXT980. In this mode the PHY provides both MII_TXCLK and MII_RXCLK. The MII_TXCLK
must be frequency-locked to the 25 MHz oscillator used by the LXT980. The LXT980 does not
provide an elasticity buffer to compensate for frequency differences. When operating in MAC
mode, the LXT980 generates the full 56 bits of preamble before sending the SFD across the MII.
Table 18. MII (Port 5) Mode & Speed Control
PORT5_SPD
PORT5_SEL
Speed &
Statistics
Mode
High
Low
100 Mbps
MAC
Low
High
10 Mbps
PHY
High
High
100 Mbps
PHY
Figure 8. MII (Port 5) Operation
The LXT980 MII port is reversible.
When PHY mode is selected, the
LXT980 acts as the PHY side of the
MII. In this mode an external MAC
sends TX Data to the LXT980 to be
repeated to the network. The
LXT980 repeats network data to the
MAC via the RX Data lines.
When MAC mode is selected, the
LXT980 acts as the MAC side of the
MII. In this mode the LXT980
repeats network data to the PHY via
the TX Data lines.
The external PHY sends data to the
LXT980 to be repeated to the
network via the RX Data lines.
LXT980
TP Ports
MII Port
Port 1
Port 5
Port 2
PHY
Port 3
Port 4
LXT980
TP Ports
MII Port
Port 1
Port 5
Port 2
MAC Mode
MII_TXD<3:0>
MII_TXEN
MII_TXER
MII_TXCLK
MII_RXCLK
MII_RXD<3:0>
10/100
MAC
MII_RXDV
MII_RXER
MII_CRS
MII_COL
MII_TXD<3:0>
MII_TXEN
MII_TXER
100 Mbps
PHY
MII_TXCLK
MII_RXCLK
MII_RXD<3:0>
Port 3
MII_RXDV
MII_RXER
Port 4
MII_CRS
MII_COL
38
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
2.5.3
MII Port Timing Considerations
The IEEE 802.3u specification provides propagation delay constraints for standard PHY devices in
Section 24.6, and for repeater devices in Section 27. The LXT980 MII port is a hybrid that does not
fit either of these categories. The critical consideration that applies to the LXT980 MII port is the
overall end-to-end system propagation delay (132 bit times maximum). The LXT980 supports the
intent of the Class II repeater application. Figure 9 and “Serial Management I/F” summarizes the
propagation delay issues relevant to the LXT980 MII port.
The LXT980 architecture treats the MII port as a fifth repeater port. The timing delay (latency)
from the MII port to any other port meets the requirements for a Class II repeater (≤ 46 BT). It does
not meet the requirements for a standard MII-PHY interface (20 - 24 BT). When operating in MAC
mode with a PHY connected to the LXT980 MII port (Figure 9B), the fifth TP port does not have
the latency characteristics of a Class II repeater with respect to the other ports.
With a MAC connected to the LXT980 MII port (Figure 9D), the maximum latency to any other
MAC is 112 BT (not including cable delay). The MAC connected to the LXT980 has an advantage
relative to other MACs because it has one less transceiver delay.
Datasheet
39
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 9. MII Timing Issues
A
B
Propagation Delay Requirements per IEEE 802.3u:- PHY prop delay (MII-TP) must be ≤ 20 BT
- Class II Repeater prop delay (TP-TP) must be ≤ 46 BT
Class II RPTR
Prop Delay
≤ 46 BT
Class II RPTR
Prop Delay
≤ 46 BT
MII Port
MII Port
P5
PHY
TP
TP
TP
P4
PHY
Prop Delay
≤ 20 BT
PHY
Prop Delay
≤ 20 BT
MII-to-MII
Prop Delay
≤ 132 BT
MII
TP Port
MAC
LXT980 Port 5 (MII)
operating in MAC Mode,
connected to a PHY device.
TP
PHY
Prop Delay
≤ 20 BT
PHY
Prop Delay
≤ 20 BT
MII
MAC
2.6
P2
P1
TP Ports
Meets Class II
RPTR Prop Delay
( ≤ 46 BT )
LXT980 Port 5 (MII)
operating in PHY Mode,
connected to a MAC device.
D
MAC
MII
MII
Class II RPTR
Prop Delay
≤ 46 BT
TP
P3
Does Not Meet
Class II RPTR
Prop Delay
MII
MAC
C
LXT980
TP
PHY-to-MAC
Prop Delay
≤ 132 BT
Class II RPTR
Prop Delay
≤ 46 BT
TP
TP
Class II RPTR
Prop Delay
≤ 46 BT
TP
PHY
Prop Delay
≤ 20 BT
PHY
Prop Delay
≤ 20 BT
MII
MII
MAC
MAC
TP
Prop Delay
≤ 112 BT
Class II RPTR
Prop Delay
≤ 46 BT
TP
TP
PHY
Prop Delay
≤ 20 BT
MII
MAC
Serial Management I/F
The high-speed Serial Management Interface (SMI) provides access to repeater MIB variables,
RMON Statistics attributes and status and control information. A network manager can access the
interface through a simple serial communications controller. The interface is designed to be used in
a multi-drop configuration, allowing multiple LXT980 devices to be managed from one common
line.
The interface consists of a data input line (SRX), data output line (STX), and a clock (SERCLK). It
can operate at up to 2 Mbps. The interface operates on a simple command response model, with the
network manager as the master and the LXT980 devices as slaves. Figure 10 is a simplified view of
typical serial management interface architecture. Refer to Figure 24 on page 58 for circuit details.
40
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 10. Typical Serial Bus Architecture
Network
Management
8530 Serial
Controller
User
Definable
Partitioning
2.6.1
LXT980
LXT918
LXT918
RMON &
Repeater MIB
Support
Serial Clock
SERCLK is a bidirectional pin; direction control is provided by the RECONFIG input. If
RECONFIG is High, the LXT980 will drive SERCLK at 625 kHz. If RECONFIG is Low,
SERCLK is an input, between 0 and 2 MHz. There is no lower bound to how slow the interface can
operate. The clock can be stopped after each operation, as long as an idle (16 ones in a row) is
transmitted first.
2.6.2
Serial Data I/O
The serial data pins, SRX and STX, should be tied together. The SRX input is compared with the
STX output. If a mismatch occurs, STX goes to a high impedance. STX is driven on the falling
edge of SERCLK. SRX is sampled on the rising edge. Refer to Test Specifications (Figure 40 on
page 77) for timing information.
2.6.3
Read and Write Operations
Normally the network manager directs read and write operations to a specific LXT980 device
using a two-part address consisting of HubID and ChipID. The interface allows up to 127 32-bit
registers to be read at one time. Up to two registers can be written at a time.
Some registers may be automatically cleared when subsequent write operations are performed on
other registers. Refer to the “Auto-Clearing Registers” section, which follows.
2.6.3.1
Management Frame Format
The SMI uses a simple frame format, which is shown in Figure 11 on page 43. Table 19 describes
the individual fields. Table 20 on page 43 shows how the bits for the header field would be stored
in memory, assuming that they are transmitted LSB to MSB, low address to high address. Table 21
on page 43 lists the command set and Table 22 on page 44 provides a variety of typical packets.
All frames begin and end with a flag of consisting of “01111110”. All fields are transmitted LSB
first. Zero-bit stuffing is required if more than five 1s in a row appear in the header, data or CRC
fields. In addition, all operations directed to the device must be followed by an idle (ten 1s in a
row), and the first operation must be preceded with an idle.
Datasheet
41
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Note:
2.6.3.2
The LXT980 uses the CCITT method of CRC (X16 + X12 + X5 +1).
Auto-Clearing Registers
Two registers, the Interrupt Status Register, see Table 64 on page 86 and the Search Port Match
Register, see Table 55 on page 83, exhibit an “Auto Clearing” feature.
How Auto Clearing Works
Before executing any write command, the device first reads the most recently accessed register. If
the accessed register was an auto-clearing register and set to Auto-Clear Mode, it will be read and
cleared.
Example: A read or write command is performed on the Interrupt Status Register. Next, a write
command is performed on Port Status Register. The write command to the Port Status Register
causes an internal read of the Interrupt Status Register. If the Interrupt Status Register was set to
Auto-Clear Mode, it will be read and cleared—as a result of the write command to the Port Status
Register. Because the read and clear is internal (and automatic), the user may not be aware that all
data in register 1 is now lost.
Note:
The Auto-Clear behavior of the Interrupt Status Register and the Search Port Match Register is
determined by the auto-clear bit in the Repeater Configuration Register (see Table 70 on page 90).
Preserving Auto-Clearing Register Data
To preserve auto-clearing data in either the interrupt status register or the Search Port Match
Register, always follow any read or write command to these registers with a read command to a
register that does not auto clear. In other words, do not leave the read pointer on an auto-clearing
register.
Example: If you read the interrupt status register (address: 0AE), immediately follow with a
“dummy” read of the port link status register (address: 098). This dummy read moves the pointer,
ensuring that the information in the interrupt status register is not inadvertently lost through auto
clearing. After the “dummy” read, you are now free to go perform any read or write operation
without fear of losing data in the auto clearing registers.
Note:
There is nothing inherently special about using one particular register for the “dummy” read
instead of another. Using the port link status register (in the preceding example) is only a
suggestion; a read command to any other register that is not auto-clearing is also acceptable.
Table 19. Serial Management Interface Message Fields
Message
Description
Start or Stop Flag
“01111110”. Protocol requires zero insertion after any five consecutive “1”s in the data stream.
Hub ID
Identifies board or sub-system. Assigned by one of two arbitration mechanisms at power-up.
Chip ID
Identifies one of eight LXT980 devices on a board or sub-system. Assigned by 3 external pins on each
device.
Command
Identifies the particular operation being performed (see Table 21 on page 43)
Length
Specifies number of registers to be transferred (1 to 127). Maximum is 2 per write, 127 per read.
Address
Specifies address of register or register block to be transferred.
42
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 11. Serial Management Frame Format
Start
Flag
Idle
Header
Chip ID
3 bits
Hub ID
5 bits
Header Content:
Data
(0-508 bytes)
Cmd
5 bits
Length
7 bits
CRC
(2 bytes)
Stop
Flag
Idle
Address
12 bits
Table 20. Serial Management Header Storage
MSB
Increasing
Address
LSB
Addr 11
Addr 10
Addr 9
Addr 8
Addr 7
Addr 6
Addr 5
Addr 4
Addr 3
Addr 2
Addr 1
Addr 0
Length 6
Length 5
Length 4
Length 3
Length 2
Length 1
Length 0
CMD 4
Cmd 3
Cmd 2
Cmd 1
Cmd 0
ChipID 2
ChipID 1
ChipID 0
HubID 4
HubID 3
HubID 2
HubID 1
HubID 0
Table 21. Serial Management Interface Command Set
Command
Value
Name
Usage
Normally
Sent By
Description
18 (Hex)
Write
Normal Ops
Network Mgr
Used to write up to 2 registers (8 bytes) at a time.
04 (Hex)
Read
Normal Ops
Network Mgr
Used to read up to 127 registers at a time.
08 (Hex)
Request ID
Arbitration
LXT980
Requests Hub ID. Repeated periodically.
00 (Hex)
ConfigChg
Arbitration
LXT980
Notifies system of configuration change (hot swap).
Requests new arbitration phase.
10 (Hex)
Re-arbitrate
Arbitration
Network Mgr
Re-starts arbitration.
14 (Hex)
Assign HubID
Arbitration
Mech. 2
Network Mgr
Assigns Hub ID to device with ARBIN=0 and ARBOUT = 1
(top of chain).
0C (Hex)
Set Arbout to 1
Arbitration
Mech. 2
Network Mgr
Commands specific device to set ARBOUT to 1.
1C (Hex)
Set Arbout to 0
Arbitration
Mech. 2
Network Mgr
Commands specific device to set ARBOUT to 0.
02 (Hex)
DevID
Config
Network Mgr
Asks device to send contents of device revision register.
2.6.4
Interrupt Functions
The LXT980 provides a single open-collector pin for external interrupt signalling. Seven different
interrupt conditions may be reported. The Interrupt Status Register identifies the specific interrupt
condition (refer to Table 66 on page 87). The Interrupt Mask Register allows specific interrupts to
be masked. Interrupts may be cleared in two ways, depending on the status of bit 11 in the Repeater
Configuration Register (refer to Table 71 on page 90).
Datasheet
43
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 22. Typical Serial Management Packets
Contents of Fields in Serial Management Packet
Message
Hub ID
Write 1, 2
Chip ID
Command
Length
Address
Data
User defined
User defined
18 Hex
01 or 02 Hex
User defined
User defined
User defined
User defined
04 Hex
01 to 7F Hex
User defined
Null
00000
000
04 Hex
01 to 7F Hex
User defined
Data values
11111
111
18 Hex
02 Hex
188 Hex
Formatted per
Table 76 on
page 91
11111
111
14 Hex
01 Hex
000 Hex
Hub ID (LSB)
and 27 0s0s
Set Arbout to 0
User defined
User defined
1C Hex
00 Hex
000 Hex
Null
Set Arbout to 1
User defined
User defined
0C Hex
00 Hex
000 Hex
Null
Arb Request
00000
000
08 Hex
02 Hex
190 Hex
PROM ID
Resend Arbitration
11111
111
10 Hex
00 Hex
000 Hex
Null
Resend Arbitration
Response
00000
000
08 Hex
02 Hex
190 Hex
EEPROM ID
User defined
User defined
02 Hex
01 Hex
000 Hex
Null
00000
000
02 Hex
01 Hex
0AD Hex
Read Request
1, 3
Read Response 3
Assign Hub ID
(Arb Method 1)
Assign Hub ID
(Arb Method 2)
Device type/
Revision code
Device/Revision
Response
Device type/
revision
1. Other than checking that the top 3 bits of the address equals 000, the LXT980 does not check if the user writes or reads past
the highest location in the data sheet. There are no adverse effects for writing or reading locations above the specified range.
2. If the user performs a write operation of length 1 or 2 and does not send a data field, the LXT980 will write junk into the
specified registers. This constitutes an invalid command.
3. If the user reads past the highest location of the LXT980, all those locations will read back 0s. If a read operation is performed
with a length of 0, the LXT980 will not respond.
2.6.5
Address Arbitration
Each device has a two part address, consisting of a HubID and a ChipID. The ChipID is assigned
by the input pins CHIPID<2:0>. The manager assigns the HubID, and each LXT980 within a
particular box will have the same HubID. The Hub ID is assigned through one of two arbitration
mechanisms as shown in Figure 12.
2.6.5.1
EEPROM Arbitration Mechanism
This mechanism requires one serial EEPROM with a unique 48-bit ID on each board. This ID can
consist of serial number, date/week/year of manufacture, etc. The ARBSELECT pin must be pulled
Low. At power-up, the device with ChipID = 0 reads a 48-bit ID from the PROM. All other devices
on the board listen in and record this ID. The device with ChipID = 0 then transmits Arbitration
Request messages on the Serial Management Interface (SMI) every 2-3 ms. The request messages
from the two boards may collide. If this happens, a resolution scheme ensures that only one
message will be transmitted.
44
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
The network manager must respond to each request with a message that includes the 48-bit ID and
the HubID. All devices hear this message, but only those that match the 48-bit ID receive the
HubID as their own. Once a HubID has been assigned to a hub, that hub will cease requesting a
HubID. This process continues until all hubs have been assigned an ID. Should a board power off
and back on, the hub will re-request an ID, which the manager provides. The command types are
assigned so an address arbitration packet will be selected over normal requests.
2.6.5.2
Chain Arbitration Mechanism
When constructing the stack, the designer should create a daisy chain by tying the ARBOUT pin of
each LXT980 to the ARBIN pin of the following LXT980. The manager is at the top of the stack
and has control of the ARBIN for the first LXT980. The manager progressively assigns hub IDs
using the “Assign Address” and “Set ARBOUT to ZERO” commands. The manager will initially
set its ARBOUT (first LXT980’s ARBIN) to zero. Since the assign address command only works
on the LXT980 that has an ARBIN of 0 and an ARBOUT of 1, the first LXT980 can be assigned an
address. After the first LXT980 has been assigned an address, it can uniquely be told to switch its
ARBOUT to zero. This creates the (01) condition on the next LXT980 in the line. This LXT980 is
then assigned an address and the process continues until all chips have been assigned a unique
address. The manager can verify that a hub is still present by performing DEVICE ID commands.
If a change of configuration is detected, the manager can perform a broadcast write to return each
hub’s ARBOUT to 1, and then re-perform the address assignment process.
When using the chain arbitration method, set up the daisy chain so that the device with ChipID = 0
is the first device on the board that the chain passes through. Tie to ARBOUT of the SCC or to
previous hub in the daisy chain. The first hub ARBIN can also be grounded. When assigning IDs,
the first chain bit, located in the Device Revision Register (refer to Table 72 on page 91) can then
be used to determine when a new board has been encountered.
2.6.5.3
Address Re-Arbitration
Two mechanisms for address re-arbitration following a configuration change, such as a hot-swap of
a board:
• Manual Re-arbitration. If the LXT980 detects a Low-to-High transition on RECONFIG, or if
RECONFIG is High at power-up, it sends out a “Configuration Change” message (all 0s) on
the bus, the network manager can use to detect that re-arbitration is required. This message
will be sent regardless of arbitration method; however, with “Chain” arbitration mechanism, it
will be sent once. The message can be ignored.
• Network Manager. The network manager detects or re-starts arbitration by sending the “Rearbitrate” command.
Datasheet
45
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 12. Address Arbitration Mechanisms
Network
Manager
SRX/STX
Network
Manager
EPROM Mechanism
for Address Arbitration
SRX/STX
Chain Mechanism for
Address Arbitration
ARBOUT
Serial
EEPROM
PROMDTI/O
PROMDTI/O
LXT980
LXT980
SRX/STX
SRX/STX
LXT980
0
ARBIN
1
ARBOUT
LXT980
Hub Board 1
ARBIN
0
ARBOUT
SRX/STX
SRX/STX
SRX/STX
SRX/STX
Hub Board 1
Hub Board 2
SRX/STX
SRX/STX
0
LXT980
LXT980
PROMDTI/O
PROMDTI/O
Serial
EEPROM
Serial I/F to Next Module
2.7
ARBIN
1
ARBOUT
LXT980
Hub Board 2
ARBIN
ARBOUT 1
LXT980
Serial I/F to Next Module
ARBI/O Chain to Next Module
Serial EEPROM Interface
The serial EEPROM interface has been designed to allow the vendor to load in optional
information unique to each board. Items such as serial number or date of manufacture can be
placed in the serial EEPROM which is also used in the address arbitration process. Each board
must contain a unique set of information. Additionally, only 1 serial EEPROM is required per
board, they are not required per chip. The LXT980 reads in the first 48 bits (three 16-bit words) out
of the EEPROM and stores them in a register. This read occurs only on power-up as this
information is static. Only the LXT980 with a ChipID of 000 will drive the serial EEPROM control
lines; all other LXT980s will listen in on the data and clock lines. The first bit to be shifted into the
LXT980 from this interface would correspond to bit 47, while the last would be 0. The serial
EEPROM shifts out the most significant bit (15) of the word first (the EEPROM must be autoincrementing).
46
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 13. Serial EEPROM Interface
93CS46
PROM_DTOUT
PROM_DTIN
PROM_CLK
PROM_CS
PROM_DTIN
PROM_CLK
LXT980
(ID=0)
LXT980
(ID≠0)
Figure 14. Optional R/W Serial EEPROM Interface
CLK
DTOUT
CS
Outgoing Data is sent on the falling clock edge.
Incoming Data is sampled on the rising clock edge.
Datasheet
47
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
3.0
Application Information
3.1
Design Recommendations
The LXT980 has been designed to comply with IEEE requirements and to provide outstanding
receive BER and long-line-length performance. Lab testing has shown that the LXT980 can
perform well beyond the required distance of 100m. As with any finely crafted device, reaping the
full benefits of the LXT980 requires attention to detail and good design practice.
3.1.1
General Design Guidelines
Adherence to generally accepted design practices is essential to minimize noise levels on power
and ground planes. Up to 50 mV of noise is considered acceptable. 50 to 80 mV of noise is
considered marginal. High-frequency switching noise can be reduced, and its effects can be
eliminated, by following these simple guidelines throughout the design:
• Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC
or ground plane that is not located adjacent to the signal layer.
• Use ample bulk and decoupling capacitors throughout the design (a value of .01 µF is
recommended for decoupling caps).
•
•
•
•
•
•
Provide ample power and ground planes.
Provide termination on all high-speed switching signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Route high-speed signals next to a continuous, unbroken ground plane.
Filter and shield DC-DC converters, oscillators, etc.
Do not route any digital signals between the LXT980 and the RJ-45 connectors at the edge of
the board.
• Do not extend any circuit power or ground plane past the center of the magnetics or to the edge
of the board. Use this area for chassis ground, or leave it void.
3.1.2
Power Supply Filtering
Power supply ripple and digital switching noise on the VCC plane can cause EMI problems and
degrade line performance. It is generally difficult to predict in advance the performance of any
design, although certain factors greatly increase the risk of having these problems:
• Poorly-regulated or over-burdened power supplies.
• Wide data busses (>32-bits) running at a high clock rate.
• DC-to-DC converters.
Many of these issues can be improved just by following good general design guidelines. In
addition, Intel also recommends filtering between the power supply and the analog VCC pins of the
LXT980. Filtering has two benefits. First, it keeps digital switching noise out of the analog
circuitry inside the LXT980, which helps line performance. Second, if the VCC planes are laid out
correctly, it keeps digital switching noise away from external connectors, reducing EMI problems.
48
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
The recommended implementation is to divide the VCC plane into two sections. The digital section
supplies power to the digital VCC pin, and to the external components. The analog section supplies
power to VCCH, VCCT, and VCCR pins of the LXT980. The break between the two planes should
run under the device. In designs with more than one LXT980, a single continuous analog VCC
plane can be used to supply them all.
The digital and analog VCC planes should be joined at one or more points by ferrite beads. The
beads should produce at least a 100Ω impedance at 100 MHz. The beads should be placed so that
current flow is evenly distributed. The maximum current rating of the beads should be at least
150% of the current that is actually expected to flow through them. Each LXT980 draws a
maximum of 500 mA from the analog supply so beads rated at 750 mA should be used. A bulk cap
(2.2 -10 µF) should be placed on each side of each ferrite bead to stop switching noise from
traveling through the ferrite.
In addition, a high-frequency bypass cap (.01 µf) should be placed near each analog VCC pin.
3.1.2.1
Ground Noise
The best approach to minimize ground noise is strict use of good general design guidelines and by
filtering the VCC plane.
3.1.3
Power and Ground Plane Layout Considerations
Great care needs to be taken when laying out the power and ground planes. The following
guidelines are recommended:
• Follow the guidelines in the LXT980 Design and Layout Guide for locating the split between
the digital and analog VCC planes.
• Keep the digital VCC plane away from the TPOP/N and TPIP/N signals, away from the
magnetics, and away from the RJ-45 connectors.
• Place the layers so that the TPOP/N and TPIP/N signals can be routed near or next to the
ground plane. For EMI reasons, it is more important to shield TPOP and TPIP/N.
3.1.3.1
Chassis Ground
For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the
board and is isolated via moats and keep-out areas from all circuit-ground planes and active
signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used
to terminate unused signal pairs (‘Bob Smith’ termination). In single-point grounding applications,
provide a single connection between chassis and circuit grounds with a 2kV isolation capacitor. In
multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kV
isolation to the Bob Smith termination.
3.1.4
MII Terminations
Series termination resistors are recommended on all MII signals driven by the LXT980. The proper
value = nominal trace impedance minus 13Ω. If the nominal trace impedance is not known, use
55Ω.
Datasheet
49
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
3.1.5
The RBIAS Pin
The LXT980 requires a 22.1 kΩ, 1% resistor directly connected between the RBIAS pin and
ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from
the pin to the resistor, and sink the other side of the resistor to ground. Surround the RBIAS trace
with ground; do not run high-speed signals next to RBIAS.
3.1.6
The Twisted-Pair Interface
Because the LXT980 transmitter uses 2:1 magnetics, system designers must take extra precautions
to minimize parasitic shunt capacitance in order to meet return loss specifications. These steps
include:
•
•
•
•
Use compensating inductor in the output stage (Figure 21).
Place magnetics as close as possible to the LXT980.
Keep transmit pair traces short.
Do not route transmit pair adjacent to a ground plane. If possible, eliminate planes under the
transmit traces completely. Otherwise, keep planes 3-4 layers away.
• Some magnetic vendors are producing magnetics with higher than average return loss
performance. Use of these improved magnetics increases the return loss budget available to
the system designer.
• Improve EMI performance by filtering the output center tap. A single ferrite bead may be used
to supply center tap current to all four ports.
In addition, follow all the standard guidelines for a twisted-pair interface:
•
•
•
•
•
•
•
•
3.1.7
Route the signal pairs differentially, close together. Allow nothing to come between them.
Keep distances as short as possible; both traces should have the same length.
Avoid vias and layer changes as much as possible.
Keep the transmit and receive pairs apart to avoid cross-talk.
If possible, place entire receive termination network on one side and transmit on the other.
Keep termination circuits close together and on the same side of the board.
Always put termination circuits close to the source end of any circuit.
Bypass common-mode noise to ground on the in-board side of the magnetics using 0.01 µF
capacitors.
The Fiber Interface
The fiber interface consists of a pseudo-ECL (PECL) transmit and receive pair to an external fiber
optic transceiver. The transmit pair should be AC coupled to the transceiver, and biased to 3.7V
with a 50Ω equivalent impedance. The receive pair can be DC-coupled, and should be biased to
3.0V with a 50Ω equivalent impedance. Figure 20 on page 55 shows the correct bias networks to
achieve these requirements.
50
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
3.1.8
Magnetics Information
The LXT980 requires a 1:1 ratio for the receive transformers and a 2:1 ratio for the transmit
transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from
static voltages across the connectors and cables. Refer to Table 23 for transformer specifications
and Magnetic Manufacturers for Networking Product Applications (App. Note 73) for a reference
list of compatible magnetic components. Before committing to a specific component, designers
should test and validate the magnetics in the specific application to verify that system requirements
are met.
Table 23. Magnetics Specifications
Parameter
Rx turns ratio
Min
Nom
Max
Units
Test Condition
–
1:1
–
–
Tx turns ratio
–
2:1
–
–
Insertion loss
0.0
–
1.1
dB
Primary inductance
350
–
–
µH
Transformer isolation
–
2
–
kV
Differential to common mode rejection
–
–
-40
dB
.1 to 60 MHz
–
–
-35
dB
60 to 100 MHz
–
–
-16
dB
30 MHz
–
–
-10
dB
80 MHz
–
–
-20
dB
30 MHz
–
–
-15
dB
80 MHz
80 MHz
Return Loss - standard
Return Loss - improved
Datasheet
51
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
3.2
Typical Application Circuitry
Figure 15 through Figure 18 are simplified block diagrams showing typical applications. Figure 19
through Figure 25 show application circuitry details.
Figure 15. Managed 10/100 Repeater Stack
Serial Comm Controller
(8530)
Bridge
10M
MAC
RMON (Optional)
100M
MAC
Inter-Repeater
Inter-Repeater
Backplanes
Backplanes
LXT980
10M
IRB
MII
Serial
Port
10 or 100M
MAC
LXT980
100M
IRB
TP/Fiber
Ports
100M
IRB
LXT980
10M
IRB
TP/Fiber
Ports
MII
MII
Serial
Port
LXT980
10M
IRB
Serial
Port
100M
IRB
100M
IRB
TP/Fiber
Ports
10M
IRB
TP/Fiber
Ports
MII
Serial
Port
16 10/100 Ports
Figure 16. Hybrid Switch/Repeater Application - for Balanced 10/100 Performance
Ethernet Switch
Memory
10/100
MAC
10/100
MAC
10/100
MAC
Inter-Repeater
100 Mbps
Control
10/100
MAC
Inter-Repeater
100 Mbps
Backplanes
Backplanes
10 Mbps
10 Mbps
LXT980
MII
10M
IRB
LXT980
100M
IRB
TP/Fiber
Ports
100M
IRB
10M
IRB
LXT980
MII
MII
TP/Fiber
Ports
10M
IRB
LXT980
100M
IRB
TP/Fiber
Ports
100M
IRB
10M
IRB
MII
TP/Fiber
Ports
16 10/100 Ports
52
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 17. Hybrid Switch/Repeater Application - Weighted Toward
100 Mbps Performance
Ethernet Switch
Memory
Control
100 Mbps
MAC
100 Mbps
MAC
100 Mbps
MAC
100 Mbps
MAC
100 Mbps
100 Mbps
100 Mbps
100 Mbps
10 Mbps
MAC
10 Mbps
10 Mbps Inter-Repeater Backplanes
LXT980
100M
IRB
LXT980
MII
10M
IRB
100M
IRB
TP/Fiber
Ports
LXT980
10M
IRB
MII
100M
IRB
TP/Fiber
Ports
PAL
LXT980
MII
10M
IRB
100M
IRB
TP/Fiber
Ports
MII
10M
IRB
TP/Fiber
Ports
16 10/100 Ports
Figure 18. Unmanaged 100-Only Repeater Stack
Inter-Repeater
Inter-Repeater
Backplanes
Backplanes
LXT980
LEDs
10M
IRB
TP/Fiber
Ports
100M
IRB
MII
100M
IRB
MII
LXT980
LXT980
10M
IRB
10M
IRB
LEDs
TP/Fiber
Ports
LEDs
TP/Fiber
Ports
LXT980
100M
IRB
MII
100M
IRB
MII
10M
IRB
LEDs
TP/Fiber
Ports
16 100M Ports
Datasheet
53
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 19. Power and Ground Connections
To Output Magnetics Centertap
LXT980
VCCT
.1µF
.01µF
.1µF
.01µF
GNDT
VCCV
GNDV
RBIAS
22.1k Ω
1%
GNDA
VCCR
.1µF
.01µF
GNDR
10µF
Analog Supply Plane
+
Ferrite
Beads
Digital Supply Plane
10µF
VCC
+5V
0.1µF
GND
54
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 20. Typical Fiber Port Interface
VCCT +5 V
69 W
0.1 mF
69 W
0.01µF
FIBONn
TD
FIBOPn 0.01µF
TD
191 W
LXT980
191 W
Fiber
Txcvr
GNDA
SIGDETn
2
VCCR
+5 V
1
80 W
To Fiber Network
GNDA
0.1 mF
80 W
GNDA
FIBINn
RD
FIBIPn
RD
130 W
130 W
GNDA
Datasheet
55
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 21. Typical Twisted-Pair Port Interface and Power Supply Filtering
Output Stage with
Compensating Inductor
0.1µF
1
GNDR
TPIP
1:1
1
2
50 Ω
1%
3
75 Ω
TPIN
50 Ω
50 Ω
4
TPOP
LXT980
200 Ω
1%
5
6
50 Ω
320 nH
TPON
200 Ω
1%
50 Ω
2:1
To Twisted-Pair Network
RJ45
50 Ω
1%
7
75 Ω
2
50 Ω
50 Ω
8
0.001µF/2kV
VCCT
0.1µF
.01µF
GNDT
1. Receiver common mode bypass cap may improve BER performance in systems with noisy power supplies.
2. A single ferrite bead may be used to supply center tap current to all 4 ports.
56
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 22. Typical 100 Mbps IRB Implementation
+5V
+5V
1 kΩ
IR100CLKBP
IR100DATBP
IR100DVBP\
91Ω
1%*
1
’245
IR100CLK
A
B
IR100DAT
IR100DV\
IR100DEN\
DIR
ISOLATE
ENA
330 Ω
1 kΩ
+5V
240 Ω
1%
+5V
120 Ω
91 Ω
IR100DAT <4:0>
IR100DV\
IR100DEN\
IR100COL\
IR100CFS\
IR100SNGL
IR100CFSBP\
LXT980
Chip ID 0
91 Ω
2
IR100CFSBP\
+5V
Stack or
Segment
Connector
LXT980
Chip ID 1
LXT980
Chip ID 2
1. In stacked configurations, all devices with ChipID = 0 are tied together at IR100CFSBP. The entire stack
must be pulled up by only one resistor per signal. Pull-up resistor is installed in the base board only.
2. All devices with ChipID ≠ 0 require individual pull-up resistors at IR100CFSBP.
3. 91Ω resistors provide gresater noise immunity. Systems using 91Ω resistors are backwards stackable
with systems using 100Ω resistors.
Figure 23. Typical 10 Mbps IRB Implementation
+5V
A
IR10CLK
B
IR10DAT
IR10ENA\
330 Ω
330 Ω
330 Ω
2
330 Ω
330 Ω
IR10CLK
IR10DAT
IR10ENA\
IR10DEN\
IR10COL\
IR10CFS\
HOLDCOL
IR10DEN\
DIR
330 Ω
ISOLATE
ENA
1%
IR10COLBP\
IR10CFSBP\
330 Ω
1%
680 Ω
1%
IR10CFSBP\
IR10DATBP
IR10ENABP\
’245
IR10COLBP\
330 Ω
IR10CLKBP
+5V
IR10CFSBP\
+5V
IR10COLBP\
Stack or
Segment
Connector
1
LXT980
Chip ID 0
LXT980
Chip ID 1
LXT980
Chip ID 2
1. In stacked configurations, all devices with ChipID = 0 are tied together at IR100CFSBP and IR10CFSBP. The entire
stack must be pulled up by only one resistor per signal. Pull-up resistor is installed in the base board only.
2. All devices with ChipID ≠ 0 require individual pull-up resistors at IR100CFSBP and IR10CFSBP.
Datasheet
57
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 24. Typical Serial Management Interface Connections
VCC
VCC
1k Ω
1k Ω
STX
’05
’05
VCC
VCC
VCC
1k Ω
1k Ω
1k Ω∗
SRX
SERDAT
’05
’05
* This resistor installed in base module only.
Figure 25. Typical Reset Circuit
VCC
D
R2
C
’14
R1
58
t(CR1) > Power Supply Ramp Up Time
R2 discharges C when supply goes away
’14 needed for multiple LXT980 devices.
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
4.0
Test Specifications
Table 24 through Table 48 and Figure 26 through Figure 41 represent the performance
specifications of the LXT980/980A. These specifications are guaranteed by test except where
noted “by design.” Minimum and maximum values listed in Table 26 through Table 48 apply over
the recommended operating conditions specified in Table 25.
Table 24. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
VCC
-0.3
6
V
Ambient
TOPA
-15
+80
ºC
Case
TOPC
–
+130
ºC
TST
-65
+150
ºC
Supply voltage
Operating temperature
Storage temperature
Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 25. Operating Conditions
Parameter
Sym
Min
Typ1
Max
Units
VCC
4.75
5.0
5.25
V
VCCV
4.75
5.0
5.25
V
VCCR
4.75
5.0
5.25
V
VCCT
4.75
5.0
5.25
V
Ambient
TOPA
0
–
70
°C
Case
TOPC
0
–
115
°C
Auto-Negotiation
PC
–
–
3.5
W
100BASE-TX, 4 ports active
PC
–
–
3.5
W
10BASE-T, 4 ports active
PC
–
–
3.4
W
100BASE-FX, 4 ports active
PC
–
–
3.0
W
Recommended supply voltage
Recommended operating temperature
Power consumption
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 26. Input Clock Requirements
Parameter1
Symbol
Min
Typ2
Max
Units
Test Conditions
Frequency
–
–
25
–
MHz
–
Frequency Tolerance
–
–
–
±100
PPM
–
Duty Cycle
–
40
–
60
%
–
1. These requirements apply to the external clock supplied to the LXT980, not to LXT980 test specifications.
2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
59
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 27. I/O Electrical Characteristics
Parameter
Min
Typ1
Max
–
–
0.8
V
TTL inputs
–
–
30
% VCC
CMOS inputs 2
–
–
1.0
2.0
–
–
V
TTL inputs
70
–
–
% VCC
CMOS inputs 2
VCC - 1.0
–
–
V
Schmitt triggers 3
Sym
Input Low voltage
VIL
Input High voltage
VIH
Units
Test Conditions
Schmitt triggers 3
Hysteresis voltage
–
1.0
–
–
V
Schmitt triggers 3
Output Low voltage
VOL
–
–
0.4
V
IOL = 1.6 mA
Output Low voltage (LED)
VOLL
–
–
1.0
V
IOLL = 10 mA
Output High voltage
VOH
2.4
–
–
V
IOH = 40 µA
Input Low current
IIL
-100
–
–
µA
–
Input High current
IIH
–
–
100
µA
–
Output rise / fall time
TRF
–
3
10
ns
CL = 15 pF
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Does not apply to IRB pins. Refer to Table 28 and Table 29 for IRB I/O characteristics.
3. Applies to RESET and CLK25 pins only.
Table 28. 100 Mbps IRB Electrical Characteristics
Symbol
Min
Typ1
Max
Units
Output Low voltage
VOL
–
.3
.7
V
RL = 330 Ω
Output rise or fall time
TRF
Parameter
Input High voltage
Test Conditions
–
4
10
ns
CL = 15 pF
VCC - 2.0
–
–
V
CMOS inputs
VCC - 1.0
–
–
V
IR100CLK (Schmitt trigger)
–
–
2.0
V
CMOS inputs
VIH
Input Low voltage
VIL
–
–
1.0
Hysteresis voltage
–
1.0
–
–
V
single drive
–
–
8.0
–
mA
RL = 240 Ω
collision
–
–
16.0
–
mA
RL = 240 Ω
single drive
–
–
22.0
–
mA
RL = 91 Ω2
collision
–
–
45.0
–
mA
RL = 91 Ω2
single drive
–
–
2.8
–
V
–
collision
–
–
0.6
–
V
–
IR100CLK (Schmitt trigger)
IR100CFS current
IR100CFSBP current
IR100CFS/BP voltage
IR100CLK (Schmitt trigger)
1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
2. 91Ω resistors provide greater noise immunity. Systems using 91Ω resistors are backwards stackable with systems using
100Ω resistors.
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Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 29. 10 Mbps IRB Electrical Characteristics
Parameter
Symbol
Min
Typ1
Max
Units
Test Conditions
Output Low voltage
VOL
0
.1
.4
V
RL = 330 Ω
Output rise or fall time
TRF
–
4
10
ns
CL = 15 pF
VCC - 2.0
–
–
V
CMOS inputs
Input High voltage
VIH
VCC - 2.0
–
–
V
IR10CLK (Schmitt trigger)
–
–
2.0
V
CMOS inputs
–
–
1.0
V
IR10CLK (Schmitt trigger)
–
0.5
–
–
V
IR10CLK (Schmitt trigger)
–
–
3.2
–
mA
Input Low voltage
VIL
Hysteresis voltage
single drive
RL = 680 Ω
IR10CFS current
collision
–
–
6.6
–
mA
RL = 680 Ω
single drive
–
–
8.1
–
mA
RL = 330 Ω
collision
–
–
17.0
–
mA
RL = 330 Ω
single drive
–
1.9
2.8
3.2
V
–
collision
–
.25
0.6
0.8
V
–
IR10CFSBP current
IR10CFS/BP voltage
1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
Table 30. 100BASE-TX Transceiver Electrical Characteristics
Symbol
Min
Typ1
Max
Units
VP
0.95
1.0
1.05
V
Note 2
–
98
–
102
%
Note 2
Signal rise/fall time
Trf
3.0
–
5.0
ns
Note 2
Rise/fall time symmetry
Trfs
–
–
0.5
ns
Note 2
–
–
–
+/- 0.5
ns
Offset from 8 ns pulse width at 50%
of pulse peak,
Vo
–
–
5
%
–
Parameter
Peak differential output voltage
(single ended)
Signal amplitude symmetry
Duty cycle distortion
Overshoot
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Measured at line side of transformer, line replaced by 100Ω (±.1%) resistor.
Table 31. 100BASE-FX Transceiver Electrical Characteristics
Parameter
Symbol
Min
Typ1
Max
Units
Test Conditions
Transmitter
Peak differential output voltage
(single ended)
VOP
0.6
–
1.0
V
–
Signal rise/fall time
TRF
–
–
1.6
ns
10 <-> 90%, 2.0 pF load
–
–
–
1.3
ns
–
Jitter (measured differentially)
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
61
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 31. 100BASE-FX Transceiver Electrical Characteristics (Continued)
Parameter
Symbol
Min
Typ1
Max
Units
Test Conditions
Receiver
Peak differential input voltage
Common mode input range
VIP
0.55
–
1.5
V
–
VCMIR
2.25
–
VCC - 0.5
V
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 32. 10BASE-T Transceiver Electrical Characteristics
Parameter
Symbol
Min
Typ1
Max
Units
Test Conditions
Transmitter
Peak differential output voltage
VP
2.2
2.5
2.8
V
Measured at line side of
transformer, line replaced by 100Ω
(± .1%) resistor
Transmit timing jitter addition2
–
–
±6.4
±10
ns
0 line length for internal MAU
Transmit timing jitter added by the
MAU and PLS sections2, 3
–
–
±3.5
±5.5
ns
After line model specified by IEEE
802.3 for 10BASE-T internal MAU
Receiver
Receive input impedance
ZIN
–
3.4
–
kΩ
Between TPIP/TPIN
Differential Squelch Threshold
VDS
300
420
585
mV
5 MHz square wave input,
750 mVpp
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU.
62
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 26. 100 Mbps Port-to-Port Delay Timing
Normal Propagation
TP / FIB
Input
t1A
t1B
TP / FIB
Output
Collision Jamming
TP / FIB
Input #1
TP / FIB
Input #2
t1C
t1D
TP / FIB
Output Jam
Table 33. 100 Mbps Port-to-Port Delay Timing Parameters
Parameter
Symbol
Min
Typ1
Max
Units2
TPIP/N or FIBIP/N to TPOP/N or FIBOP/N, start
of transmission
t1A
–
–
46
BT
–
TPIP/N or FIBIP/N to TPOP/N or FIBOP/N, end
of transmission
t1B
–
–
46
BT
–
TPIP/N or FIBIP/N collision to TPOP/N or
FIBOP/N, start of jam
t1C
–
–
46
BT
–
TPIP/N or FIBIP/N idle to TPOP/N or FIBOP/N,
end of jam
t1D
–
–
46
BT
–
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
Datasheet
63
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 27. 100BASE-TX Transmit Timing - PHY MODE MII
TX_CLK
t2A
TXD,
TX_EN,
TX_ER
t2B
t2C
t2D
CRS
t2E
TPOP/N
Table 34. 100BASE-TX Transmit Timing Parameters - PHY Mode MII
Parameter
TXD, TX_EN, TX_ER Setup to TX_CLK High
TXD, TX_EN, TX_ER Hold from TX_CLK High
TX_EN sampled to CRS asserted
TX_EN sampled to CRS de-asserted
TX_EN sampled to TPOP/N active (Tx latency)
Sym
Min
Typ1
Max
Units2
t2A
t2B
t2C
t2D
t2E
10
–
–
ns
–
5
–
–
ns
–
0
–
4
BT
–
Test Condition
0
–
16
BT
–
–
–
46
BT
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
64
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 28. 100BASE-TX Receive Timing - PHY Mode MII
TPIP/N
t3A
t3B
CRS
t3C
t3D
RXD,
RX_DV,
RX_ER
t3E
RX_CLK
COL
t3F
t3G
Table 35. 100BASE-TX Receive Timing Parameters - PHY Mode MII
Sym
Min
Typ1
Max
Units2
t3A
t3B
–
–
46
BT
–
TPIP/N quiet to CRS de-asserted
–
–
46
BT
–
CRS asserted to RXD, RX_DV,
RX_ER
t3C
1
–
4
BT
–
CRS de-asserted to RXD,
RX_DV, RX_ER de-asserted
t3D
–
–
3
BT
–
RX_CLK falling edge to RXD,
RX_DV, RX_ER valid
t3E
–
–
10
ns
–
TPIP/N in to COL asserted
t3F
t3G
–
–
46
BT
–
–
–
46
BT
–
Parameter
TPIP/N in to CRS asserted
TPIP/N quiet to COL de-asserted
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
Datasheet
65
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 29. 100BASE-TX Transmit Timing - MAC Mode MII
RX_CLK
t4A
RXD,
RX_DV,
RX_ER
t4B
t4C
t4D
TPOP/N
Table 36. 100BASE-TX Transmit Timing Parameters - MAC Mode MII
Parameter
RXD, RX_DV, RX_ER Setup to RX_CLK High
RXD, RX_DV, RX_ER Hold from RX_CLK High
RXD sampled to TPO asserted
RXD sampled to TPO de-asserted
Sym
Min
Typ1
Max
Units2
t4A
t4B
t4C
t4D
10
–
–
ns
–
5
–
–
ns
–
–
–
46
BT
–
–
–
46
BT
–
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
66
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 30. 100BASE-TX Receive Timing - MAC Mode MII
TPIP/N
t5A
t5B
TXD,
TX_EN,
TX_ER
t5C
TX_CLK
Table 37. 100BASE-TX Receive Timing - MAC Mode MII
Sym
Min
Typ1
Max
Units2
–
–
46
BT
–
TPIP/N quiet to TXD de-asserted
t5A
t5B
13
–
46
BT
–
TX_CLK rising edge to TXD,
TX_EN, TX_ER valid
t5C
0
–
25
ns
–
Parameter
TPIP/N in to TXD, TX_EN, TX_ER
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
Datasheet
67
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 31. 100BASE-FX Transmit Timing - PHY Mode MII
TX_CLK
t6A
t6B
TXD,
TX_EN,
TX_ER
t6B
t6D
CRS
t6E
FIBOP/N
Table 38. 100BASE-FX Transmit Timing Parameters - PHY Mode MII
Parameter
Sym
Min
Typ1
Max
Units2
TXD, TX_EN, TX_ER Setup to TX_CLK
High
t6A
10
–
–
ns
–
TXD, TX_EN, TX_ER Hold from TX_CLK
High
t6B
5
–
–
ns
–
TX_EN sampled to CRS asserted
0
–
4
BT
–
TX_EN sampled to CRS de-asserted
t6C
t6D
0
–
16
BT
–
TX_EN sampled to FIBOP/N out
(Tx latency)
t6E
–
–
46
BT
–
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
68
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 32. 100BASE-FX Receive Timing - PHY Mode MII
FIBIP/N
t7A
t7B
CRS
t7C
t7D
RXD,
RX_DV,
RX_ER
t7E
RX_CLK
t7F
COL
t7G
Table 39. 100BASE-FX Receive Timing - PHY Mode MII
Sym
Min
Typ1
Max
Units2
t7A
t7B
–
–
46
BT
–
FIBIP/N quiet to CRS de-asserted
–
–
46
BT
–
CRS asserted to RXD, RX_DV,
RX_ER
t7C
1
–
4
BT
–
CRS de-asserted to RXD,
RX_DV, RX_ER de-asserted
t7D
–
–
3
BT
–
RX_CLK falling edge to RXD,
RX_DV, RX_ER valid
t7E
–
–
10
ns
–
FIBIP/N in to COL asserted
t7F
t7G
–
–
46
BT
–
–
–
46
BT
–
Parameter
FIBIP/N in to CRS asserted
FIBIP/N quiet to COL de-asserted
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
Datasheet
69
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 33. 100BASE-FX Transmit Timing - MAC Mode MII
RX_CLK
t8A
RXD,
RX_DV,
RX_ER
t8B
t8C
t8D
FIBOP/N
Table 40. 100BASE-FX Transmit Timing - MAC Mode MII
Parameter
Sym
Min
Typ1
Max
Units2
RXD, RX_DV, RX_ER Setup to RX_CLK
High
t8A
10
–
–
ns
–
RXD, RX_DV, RX_ER Hold from
RX_CLK High
t8B
5
–
–
ns
–
RXD sampled to FIBOP/N asserted
t8C
t8D
–
–
46
BT
–
–
–
46
BT
–
RXD sampled to FIBOP/N de-asserted
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
70
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 34. 100BASE-FX Receive Timing - MAC Mode MII
FIBIP/N
t9A
t9B
TXD,
TX_EN,
TX_ER
t9C
TX_CLK
Table 41. 100BASE-FX Receive Timing - MAC Mode MII
Parameter
Sym
Min
Typ1
Max
Units2
FIBIP/N in to TXD, TX_EN, TX_ER
–
–
46
BT
–
FIBIP/N quiet to TXD de-asserted
t9A
t9B
–
–
46
BT
–
TX_CLK rising edge to TXD,
TX_EN, TX_ER valid
t9C
0
–
25
ns
–
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
Datasheet
71
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 35. 10BASE-T Transmit Timing - PHY Mode MII
TX_CLK
t10A
TXD,
TX_EN,
TX_ER
t10B
t10C
CRS
Table 42. 10BASE-T Transmit Timing Parameters - PHY Mode MII
Parameter
TXD, TX_EN, TX_ER Setup to TX_CLK High
TXD, TX_EN, TX_ER Hold from TX_CLK High
TX_EN sampled to CRS asserted
Sym
Min
Typ1
Max
Units2
t10A
t10B
t10C
10
–
–
ns
Note: –
5
–
–
ns
Note: –
0
.9
2
BT
Note: –
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 10BASE-T =
10-7 s or 100 ns.
72
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 36. 10BASE-T Receive Timing - PHY Mode MII
TPIP/N
t11A
CRS
t11B
RXD,
RX_DV,
RX_ER
t11C
RX_CLK
COL
t11D
Table 43. 10BASE-T Receive Timing Parameters - PHY Mode MII
Sym
Min
Typ1
Max
Units2
TPIP/N in to CRS asserted
t11A
5
6.6
8
BT
–
CRS asserted to RXD, RX_DV,
RX_ER
t11B
70
76
84
BT
–
RX_CLK falling edge to RXD,
RX_DV, RX_ER valid
t11C
–
–
10
ns
–
TPIP/N in to COL asserted
t11D
6
7.4
9
BT
–
Parameter
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 10BASE-T =
10-7s or 100 ns.
Datasheet
73
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 37. 100 Mbps IRB Timing
TPIP/N
FIBIP/N
t12A
IR100DV
IR100CFS
1R100COL
IR100DAT<4:0>
t12C
t12B
IR100CLK
Table 44. 100 Mbps IRB Timing Parameters1
Parameter
TPIP/N or FIBP/N to IR100DV Low
IR100DAT to IR100CLK setup time.
IR100DAT to IR100CLK hold time.
Symbol
Min
Typ2
Max
Units3
t12A
t12B
t12C
18
24
30
BT
–
–
10
–
ns
–
–
0
–
ns
–
Test Conditions
1. This table contains propagation delays from the TP ports to the IRB for normal repeater operation. All values in this table are
output timings.
2. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
3. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T =
10-8 s or 10 ns.
74
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 38. 10 Mbps IRB Receive Timing
TPIP/N
t13A
IR10ENA
t13B
t13C
IR10DAT
See Table 45, Note 3
IR10CLK
Table 45. 10 Mbps IRB Receive Timing Parameters1
Symbol
Min
Typ2
Max
Units4
TPIP/N to IR10ENA Low
t13A
3
5.1
7
BT
–
IR10CLK rising edge to
IR10DAT rising edge.
t13B
25
-
55
ns
IR10CLK rising edge to
IR10DAT falling edge.
t13C
5
-
25
ns
330 Ω pull-up, 150 pF load on IR10DAT.
1 kΩ pull-up, 150 pF load on IRCLK.
All measurements at 2.5V.
Parameter
Test Conditions
1. This table contains propagation delays from the TP ports to the IRB for normal repeater operation. All values in this table are
output timings.
2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
3. There is a delay of approximately 13 to 16 bit times between the assertion of IR10ENA and the assertion of IR10CLK and
IR10DAT. This delay does not affect repeater operation because downstream devices begin generating preamble as soon as
IR10ENA is asserted.
4. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 10BASE-T =
10-7 s or 100 ns.
Datasheet
75
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 39. 10 Mbps IRB Transmit Timing
MACACTIVE
t14A
IR10ENA
IR10DAT
t14C
t14B
IR10CLK
t14D
TPOP/N
Table 46. 10 Mbps IRB Transmit Timing Parameters
Symbol
Min
Typ1
Max
Units2
Test Conditions
MACACTIVE to IR10ENA
assertion delay 3
t14A
–
100
–
ns
MACACTIVE High to IR10ENA Low. 4
IR10DAT (input) to IR10CLK
setup time
t14B
–
20
–
ns
IR10DAT valid to IR10CLK rising
edge.4
IR10CLK to IR10DAT (input)
hold time
t14C
–
0
–
ns
IR10CLK rising edge to IR10DAT
change.4
IR10ENA asserted to
TPOP/N active
t14D
5
5.1
6
BT
–
Parameter
1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 10BASE-T =
10-7 s or 100 ns.
3. External devices should allow at least one 10 MHz clock cycle (10 ns) between assertion of MACACTIVE and IR10ENA.
4. Input.
76
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 40. Serial Management Interface Timing
t15A
t15B
SERCLK
SRX
t15C
STX
Table 47. Serial Interface Timing Characteristics 1
Symbol
Min
Typ1
Max
Units
Test Conditions
SERCLK input frequency
–
–
–
2.0
MHz
SERCLK output frequency
–
625
–
kHz
Depending on RECONFIG, this is either an
input or output.
Parameter
Data to clock setup time
t15A
0
–
–
ns
SRX valid to SERCLK rising edge. 2
Clock to data hold time
t15B
200
–
–
ns
SERCLK rising edge to SRX change. 2
Data propagation delay
t15C
–
–
200
ns
SERCLK falling edge to STX valid. 3
1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
2. Input.
3. Output.
Datasheet
77
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Figure 41. PROM Interface Timing
PROM_CLK
t16A
PROM_CS
t16B
PROM_DTOUT
t16C t16D
PROM_DTIN
Table 48. PROM Interface Timing Characteristics
Parameter
PROM_CLK
Symbol
Min
–
Typ1
Max
Units
–
1.0
MHz
Test Conditions
PROM_CLK frequency.
CLK to PROM_CS delay
t16A
–
200
ns
CLK falling edge to PROM_CS.
CLK to PROM_DTOUT delay
t16B
–
20
ns
CLK falling edge to PROM_DTOUT.
PROM_DTIN to CLK setup time
t16C
20
–
ns
PROM_DTIN to CLK rising edge.
PROM_DTIN to CLK hold time
t16D
20
–
ns
PROM_DTIN to CLK rising edge.
78
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
5.0
Register Definitions
The LXT980/980A register set is composed of multiple 32-bit registers of the types listed in Table
49. All register addresses are hexadecimal.
Table 49. Register Set
Base
Address1
Register Type
00X
Port 1 Counters (TP/FX)
01X
Port 2 Counters (TP/FX)
02X
Port 3 Counters (TP/FX)
03X
Port 4 Counters (TP/FX)
04X
Port 5 Counters (MII)
05X
Additional Counters (100 only)
Bit Assignments & Description
Refer to Table 50 and Table 51.
05X, 06X
RMON Counters
Refer to Table 50 and Table 52.
07X
Port Addresses
Refer to Table 53 and Table 54.
08X
Authorized Addresses
Refer to Table 53.
08X, 09X
Global Addresses
Refer to Table 53 and Table 55.
09X
Port Control & Status
Refer to Table 56 through Table 63.
09X, 0AX, 0BX,
188, 189, 190,
191
General Setup/Status
Refer to Table 64 through Table 82.
1. X = Offset address of register desired. Note that base register addresses for port counters are offset by 1 (00x refers to Port 1,
01X to Port 2, 02X to Port 3, 03X to Port 4 and 04X to Port 5).
5.1
Counter Registers
Table 50 shows bit assignments. When reading a 64-bit counter, read the lower address (lower 32
bits of counter) first, followed by the upper address. The first read causes all 64 bits to be
simultaneously latched into an internal holding register. The second read is directed to this holding
register. The statistics bit must be set off to write to the counters.
Table 50. Counter Register Bit Assignments
31
30
29
28
27
26
25: 7
6
5
4
3
2
1
0
D31
D30
D29
D28
D27
D26
D25:D7
D6
D5
D4
D3
D2
D1
D0
5.1.1
Port Counter Registers
The Port Counter descriptions in Table 51 are intended to be illustrative. For the exact definition of
these counters, refer to the Repeater MIB, RFC 1516. All counters count packets, octets or events
that were received at each port. In the descriptions, the length of a packet never includes preamble
or framing bits (start of frame, end of frame, dribble bits, etc.), but an “event” does include these
items.
Datasheet
79
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 51. Port Counter Registers
Offset
Addr1
Name
Description
Registers Used When Running at 10 or 100 Mbps
Counts valid-length (64 to 1518 bytes), valid-CRC, collisionfree packets. Depending on the state of the CountMode bit
(6) in the Repeater Configuration Register, this counter will
count either all packets (CountMode=0) or only Unicast
Packets (CountMode=1).
rptrMonitorPortReadableFrames
0X0
rptrMonitorPortReadableOctets
0X1,
(Lower/Upper)
0X2
rptrMonitorPortFrameCheckSequence
0X3
Counts valid length, collision-free packets that had FCS
errors, but were correctly framed (had an integral number of
octets).
rptrMonitorPortAlignmentErrors
0X4
Counts valid length, collision-free packets that had FCS
errors and were incorrectly framed (had a non-integral
number of octets).
rptrMonitorPortFramesTooLong
0X5
Counts packets that had a length greater than 1518 octets.
rptrMonitorPortShortEvents
0X6
10M: Counts events <80 bit times.
Counts the number of octets in all valid-length (64 to 1518
bytes), valid-CRC, collision-free packets, not including
preamble and framing bits. This register is not affected by the
CountMode bit.
100M: Counts events < 88 bit times.
10M: Counts events > 80 and < 504 bit times.
rptrMonitorPortRunts
0X7
rptrMonitorPortCollisions
0X8
Counts the number of collisions that occurred, not including
late collisions.
rptrMonitorPortLateEvents
0X9
Counts the number of times collision was detected more than
512 bit times after the start of carrier.
rptrMonitorPortVeryLongEvents
0XA
Counts the number of times any activity continued for more
than 4 to 7.5 ms.
rptrMonitorPortDataRateMismatches
0XB
Counts the number of times the incoming data rate
mismatched the local clock source enough to cause a FIFO
underflow or overflow.
rptrMonitorPortAutoPartitions
0XC
Counts the number of times this port has been partitioned by
the Auto-partition algorithm.
rptrTrackSourceAddrChanges
0XD
Counts the number of times the source address has
changed.
Minimum roll-over time of 81 hours.
rptrMonitorPortBroadcastPkts
0XE
Counts the number of good broadcast packets received by
this port. Counter is not cleared by ZeroCount bit.
rptrMonitorPortMulticastPkts
0XF
Counts the number of good multicast packets received by
this port. Counter is not cleared by ZeroCount bit.
100M: Counts events > 92 and < 504 bit times.2
Registers used only when running at 100 Mbps
1. Replace “X” in address with specific port to be addressed (offsets 0 through 4 correspond to Ports 1 through 5).
2. For 100M: the “Short Events” register counts events < 88 bit times; the “Port Runts” register counts events > 92. A 4-bit-time
differential exists because 100M operates with nibble boundaries, so data packets < 4 bits are counted as 4.
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 51. Port Counter Registers (Continued)
Offset
Addr1
Name
rptrMonitorPortIsolates - Port 1
050
rptrMonitorPortIsolates - Port 2
051
rptrMonitorPortIsolates - Port 3
052
rptrMonitorPortIsolates - Port 4
053
rptrMonitorPortIsolates - Port 5
054
rptrMonitorSymbolErrorDuringPacket - Port 1
055
rptrMonitorSymbolErrorDuringPacket - Port 2
056
rptrMonitorSymbolErrorDuringPacket - Port 3
057
rptrMonitorSymbolErrorDuringPacket - Port 4
058
Description
Counts the number of times a port auto isolates. NOTE:
When these counters increment, none of the other port
counters will increment since the frame never had a valid
start.
Counts the number of time a packet contained symbol errors.
Only one symbol error is counted per packet.
1. Replace “X” in address with specific port to be addressed (offsets 0 through 4 correspond to Ports 1 through 5).
2. For 100M: the “Short Events” register counts events < 88 bit times; the “Port Runts” register counts events > 92. A 4-bit-time
differential exists because 100M operates with nibble boundaries, so data packets < 4 bits are counted as 4.
5.1.2
RMON Counter Registers
The interface counter descriptions in Table 52 are intended to be illustrative. For the exact
definition of these counters, refer to the RMON MIB, RFC 1757. All counters count events, octets
or packets that were received from the interface. Packet length never includes preamble or framing
bits (start of frame, end of frame, dribble bits, etc.).
Table 52. RMON Counter Registers
Name
Type
Addr
05C,
Description
05D
Number of data octets including those in bad packets and octets in
FCS fields, but does not include preamble or other framing bits.
R/W
05E
Number of packets received (from network), including errored packets.
etherStatsBroadcastPkts
R/W
05F
Number of good broadcast packets received. Counter is not cleared
by ZeroCount bit.
etherStatsMulticastPkts
R/W
060
Number of good multicast packets received.
etherStatsCRCAlignErrors
R/W
061
Number of valid-length packets (64 to 1518 bytes inclusive) that had a
bad Frame Check Sequence (FCS).
etherStatsUndersizePkts
R/W
062
Number of well-formed packets that were smaller than 64 octets.
etherStatsOctets
R/W
etherStatsPkts
LXT980: Number of well-formed packets that were longer than 1518
octets.
etherStatsOversizePkts
R/W
063
LXT980A: Number of well-formed packets that were longer than 1518
octets and smaller than 2044.
etherStatsFragments
R/W
064
Number of ill-formed packets less than 64 octets. Note: Any event
without a start-of-frame delimiter (0-octet packet) will be counted as a
fragment, no matter how long it is.
LXT980: Number of ill-formed packets longer than 1518 octets. An illformed packet is one with an FCS error.
etherStatsJabbers
Datasheet
R/W
065
LXT980A: Number of ill-formed packets longer than 1518 octets, and
number of packets (good and bad) greater than/equal to 2044. An illformed packet is one with an FCS error.
81
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 52. RMON Counter Registers (Continued)
Name
Type
Addr
R/W
066
The best estimate of the total number of collisions on this interface.
etherStatsPkts64Octets
R/W
067
No. of packets (good and bad) that were 64 octets long.
etherStatsPkts65to127Octets
R/W
068
No. of packets (good and bad) between 65 and 127 octets long.
etherStatsPkts128to255Octets
R/W
069
No. of packets (good and bad) between 128 and 255 octets long.
etherStatsPkts256to511Octets
R/W
06A
No. of packets (good and bad) between 256 and 511 octets long.
etherStatsPkts512to1023Octets
R/W
06B
No. of packets (good and bad) between 512 and 1023 octets
long.
No. of packets (good and bad) between 1024 and 1518 octets long.
etherStatsCollisions/ rptr
Monitor Transmit Collisions
etherStatsPkts1024to1518Octets
R/W
06C
Not Used
R/W
06D
rptrMonitorTotalOctets
(Lower/Upper)
5.2
R/W
06E,
06F
Description
Total number of octets contained in valid frames received on this
segment. Counter is not cleared by ZeroCount bit.
Ethernet Address Registers
All Ethernet address registers consist of two 32-bit registers that together contain a 48-bit Ethernet
address. Refer to Table 53 for register bit assignments.
Table 53. Ethernet Address Register Bit Assignments
5.2.1
Upper Address
Bits 15:0 contain bits 47:32 of the Ethernet Address.
Lower Address
Bits 31:0 contain bits 31:0 of the Ethernet Address.
Port Address Tracking Registers
The port address tracking register set is described in Table 54. These registers continuously
monitor the source addresses of packets emanating from the corresponding ports. Refer to Table 53
for bit assignments.
Table 54. Port Address Tracking Registers
Size,
bits
Addr
Description
rptrAddrTrackNewLastSrcAddress
Port 1
48
070, 071
rptrAddrTrackNewLastSrcAddress
Port 2
48
072, 073
Stores the value of the last Source Address received.
Can also act as NewLastSourceAddress via SW. These
addresses power up unknown, but can be zeroed by
software.
rptrAddrTrackNewLastSrcAddress
Port 3
48
074, 075
rptrAddrTrackNewLastSrcAddress
Port 4
48
076, 077
rptrAddrTrackNewLastSrcAddress
Port 5 (MII)
48
078, 079
Name
Example Address: 00-20-7B-03-02-01
First Read: msb037B2000lsb.
Second Read: msb XXXX0102lsb
All addresses must read in order. Only the first read
updates the holding register. X’s are currently defined
as zeros.
1. All port address tracking registers are Read/Write.
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
5.2.2
Search Address Registers
The Search Address Register set is described in Table 55.
Table 55. Search Address Registers
Name
Type
Addr
Size
(bits)
Description
48
On-board address search register. Should the user
wish to find out if a particular source address has
been seen on any of the ports, on any of the
segments, this register would be used. Each port
within an LXT980 chip will be checked for traffic
originating from the source address matching this
register. If a match is found, the port number where
the traffic originated will be saved thus allowing
software to determine where the address is located.
The register that contains the port from the Search
Address Match Function is the Search Address
Match Register.
(default = Xs)
Search Address Register
R/W
Refer to Table 53 for bit
assignments.
08A, 08B
This register holds the port number of the host which
uses the address specified in the Search Address
Register. When the Auto-Clear bit (bit 11) in the
Repeater Configuration Register is set to a ‘0’, this
register is cleared upon reading. If the Auto-Clear bit
is set to a ‘1’, this register’s bit(s) are cleared by
writing a ‘1’ to the appropriate bit(s). (default = 0s)
Search Port Match Register
Refer to Table 56 on page 83 for bit
assignments.
5.3
R
090
5
Control and Status Registers
The Control and Status Register set includes general port control and status registers that conform
to the bit assignments shown in Table 56, Table 58, and Table 60. Additional control and status
registers with alternate bit assignments are shown in Table 61 through Table 68.
5.3.1
Port Link Control Register
The Port Link Control Register is described in Table 57. Refer to Table 56 for Port Link Control
Register bit assignments.
Table 56. Port Link Control and Status Register Bit Assignments
31:4
3
2
1
0
Rsvd
Port 4
Port 3
Port 2
Port 1
Table 57. Port Link Control Register
Name
Port Link Control
Datasheet
Type
R/W
Addr
Description
091
This register controls the link function of the 4 twisted-pair ports of
the LXT980. When disabled, a port will no longer be disconnected
due to link fail. When enabled, the port will only remain connected
to the network so long as link pulses are being received: 0 =
disable, 1 = enable (default).
83
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
5.3.2
General Port Control Registers
The General Port Control Register set is described in Table 59. Refer to Table 58 for the General
Port Control Registers bit assignments.
Table 58. General Port Control and Status Register Bit Assignments
31:5
4
3
2
1
0
Rsvd
Port 5 (MII)
Port 4
Port 3
Port 2
Port 1
Table 59. General Port Control Registers
Name
Type
Addr
Description
LXT980
Provides per-port selection of partition algorithms.
0 = normal (default)
1 = alternate
Speed
Port Alternate Partition
Algorithm Control
R/W
Normal
Alternate
10M
Un-partition a port when data
can be either received or
transmitted from the port for
450-560 bit times without a
collision on that port.
Un-partition a port only when
data can be transmitted to the
port for 450-560 bit times
without a collision on that port.
100M
Un-partition a port only when
data can be transmitted to the
port for 450-560 bit times
without a collision on that port.
Un-partition a port when data
can be either received or
transmitted from the port for
450-560 bit times without a
collision on that port.
094
LXT980A
Provides per-port selection of partition algorithms.
0 = normal
1 = alternate (default)
Speed
Port Enable
R/W
095
Normal
Alternate
10M
Un-partition a port when data can be either received or
transmitted from the port for 450-560 bit times without a collision
on that port.
100M
Un-partition a port only when
data can be transmitted to the
port for 450-560 bit times
without a collision on that port.
Un-partition a port when data
can be either received or
transmitted from the port for
450-560 bit times without a
collision on that port.
This register controls whether a port is enabled/disabled. If the MGR_PRES
signal is Low on power up, then all ports will be disabled until such time that
management software re-enables them. Otherwise the ports will power on
enabled.
0 = disable, 1 = enable (default = 1).
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
5.3.3
Port Learn and Speed Control Registers
The port learn and speed control register set is described in Table 61 on page 85. Refer to Table 60
for the bit assignments of these registers.
Table 60. Port Learn and Speed Control Registers
31:10
9
8
Rsvd
Port 5 (MII)
7
6
5
Port 4
4
3
Port 3
2
Port 2
1
0
Port 1
Table 61. Port Learn and Speed Control Registers
Name
Type
Addr
Description
This register sets the level of learning each port uses. The Learn
Settings are as follows:
Port Authorized Learn Enable
R/W
Control
Bit 1
Bit 0
Function
0
0
Learn new source addresses.
0
1
Next Lock. Learn only the first source address
encountered. After a port learns its first address,
it changes the Authorized Learn bits (for that
port) to a “10” to lock down the address.
1
0
Lock. Hardware locked-down the address. Only
software can write to this address.
1
1
Reserved.
096
This register overrides the hardware settings.
Enabling auto-negotiation via software requires writing to both the Port
Speed Control Register and the Auto-Negotiate Configuration Register
(see Table 82 on page 94).
Forcing a port’s speed overrides and disables auto-negotiation.
The MII (expansion) port is not software-configurable.
Default is set by pins SPD0 and SPD1. Settings are as follows:
Port Speed Control
5.3.4
R/W
097
SPD1
SPD0
Function
0
0
If auto-negotiate is enabled, advertise all
abilities. Otherwise port is disabled.
0
1
Force 10 Mbps TP
1
0
Force 100 Mbps Fiber (Does not apply to MII)
1
1
Force 100 Mbps TP
Port Status Registers
The port status register set is described in Table 63. Bit assignments are shown in Table 62.
Table 62. Port Status Register Bit Assignments
31:4
41
3
2
1
0
Rsvd
Port 5 (MII)
Port 4
Port 3
Port 2
Port 1
1. Bit 4 used only in the port partition and port speed status registers.
Datasheet
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 63. Port Status Registers
Type1
Addr
Port Link Status
R
098
A read of this register will reflect the current link status of the 4 twisted-pair ports
within a LXT980 chip. A ‘1’ indicates that the port is currently in the LINK_GOOD
state. (default = 0s)
Port Polarity Status
R
099
A read of this register will reflect the current polarity status of the 4 twisted-pair
ports within a LXT980 chip. A ‘1’ indicates that the polarity has been crossed for a
given port. (default = 0s)
Port Partition Status
R
09A
A read of this register will reflect the current partition status of all 5 ports within a
LXT980 chip. A ‘1’ indicates that the port has been partitioned out of the repeater.
A ‘0’ is read if the port is connected. (default = 0s)
Port Speed Status
R
09C
Name
Description
Indicates the current status of each port.
0 = port is connected at 10 Mbps
1 = port is connected at 100 Mbps
Port Isolation Status
(Fast Ethernet Only)
R
09D
Indicates the current isolation status of each port operating in Fast Ethernet.
Fast Ethernet Port Isolation (Clause 27.3.2 of 802.3u)
1. R = Read Only
5.3.5
Interrupt Status/Mask Registers
The interrupt status and mask registers are described in Table 65 and Table 66. Refer to Table 64
for bit assignments.
Table 64. Interrupt Status/Mask Register Bit Assignments
31:8
Reserved
7
Far-End
Fault
6
5
4
3
2
1
0
Source
Speed
Reserved
Jabber
Isolate
Partition
FCC
Address
Change
Change
Detected
Table 65. Interrupt Status/Mask Register
Name
Type
Addr
Description
Interrupt Status Register
R(/W)1
0AE
This register captures status bits within the LXT980 and holds them.
Refer to Table 66 for bit descriptions.
Interrupt Mask Register
R/W
0AF
This register allows masking of individual interrupts.
0 = do not mask (default)
1 = mask
1. R(/W) When the register clear bit (bit11) in the repeater configuration register is set to a ‘0’, this register is cleared upon
reading.
If the register clear bit is set to a ‘1’, these register bit(s) are cleared by writing a ‘1’ to the appropriate bit(s).
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 66. Interrupt Status Register Bit Definitions
Bit
Name
Type1
31:8
Reserved
R/W
Description
Default
Reserved - Write as 0s; ignore on read.
N/A
A ‘1’ indicates that one of four conditions has occurred:
1. A port in fiber mode received the remote fault code from its link partner.
2. A port in auto-negotiation received 3 FLPs in a row with the remote fault bit set.
Far End
Fault
7
R/W
3. A port is in fiber mode with remote fault reporting enabled, and either the receive
PLL is unlocked or the signal detect input has been lost.
0
4. A port in auto-negotiation is transmitting FLPs with the remote fault bit set.
In conditions 1 and 2 the link partner has detected the remote fault condition and is
sending it to the LXT980.
In conditions 3 and 4 the LXT980 has detected the remote fault condition and is
sending it to the link partner.
6
Reserved
R/W
Reserved - Write as 0s; ignore on read.
0
A ‘1’ indicates that a port is in jabber state.
5
Jabber
R
During 100 Mbps operation, jabber occurs when any receiver remains active for
more than 57,500 bit times. The LXT980 exits this state when all receivers return to
the idle condition.
0
During 10 Mbps operation, jabber occurs when any port remains actively
transmitting for longer than 40,000 to 75,000 bit times. The LXT980 will assert a
minimum-IFG idle period when a port is jabbering.
4
Isolate
R/W
A ‘1’ indicates that a port has been isolated (100 Mbps only). The LXT980 isolates
any port that transmit more than two successive false carrier events. A false carrier
event is defined as a packet that does not start with a /J/K symbol pair.
0
A ‘1’ indicates that a port has been partitioned.
In 100 Mbps operation, the LXT980 partitions any port that participates in excess of
60 consecutive collisions. In 10 Mbps operation, the LXT980 partitions any port that
participates in excess of 32 consecutive collisions. Once partitioned, the LXT980
will continue monitoring and transmitting to the port, but will not repeat data
received from the port until it properly un-partitions.
0
3
Partition
R/W
2
FCC
R/W
A ‘1’ indicates that a port has received too many false carrier events
0
1
SA
Change
R/W
A ‘1’ indicates that a port address changed from that stored in the
lastSourceAddress register.
0
0
Speed
Change
R/W
A ‘1’ indicates that a port speed change was detected.
0
1. R = Read only; R/W = Read/Write.
5.3.6
MII Status Register
The MII Status register is described in Table 68. Refer to Table 67 for bit assignments. This is a 32bit register.
Table 67. MII Status Register Bit Assignment
31:2
1
0
Select connecting device type
Select 10 Mbps or 100 Mbps
Reserved
0 = 10 Mbps
1 = 100 Mbps
Datasheet
0 = MAC Mode (connected to a PHY)
(Available at 100 Mbps only)
1 = PHY Mode (connected to a MAC)
(Available at either 10 or 100 Mbps)
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 68. MII Status Register
Name
MII Register
5.4
Type
Addr
R
0B4
Description
Used to give the status of the MII port. Default is set by pins.
Configuration Registers
The Configuration Register set is described in Table 69. Bit assignments for the configuration
registers are shown in Table 70 through Table 77.
Table 69. Configuration Registers
Name
Repeater Configuration Register
Repeater Serial Configuration
Register
Type1
Addr
R/W
0AB
Refer to Table 70 for bit assignments.
R
0AC
This 8 bit register holds user-defined data. These bits may be
used to indicate the type of board configuration, port count or
other vendor-related data. Default is set by pins.
Description
This register follows the IEEE 1149.1 specification. Refer to
Table 72 for bit assignments.
Device/Revision ID register
R
0AD
Reserved
R
0B0
The upper 4 bits identify the device revision level. The next 16
bits store the Part ID Number, which in this case is hexadecimal
‘3D4’. The next 11 bits contain a JEDEC Manufacturer ID, which
for Intel is hexadecimal ‘FE’. The lowest bit (0) is set only for the
first device in a chain.
Ignore on read.
Refer to Table 73 for bit assignments. This register reflects the
LED Mode set by pins 207 and 208, and provides software
control for the global Fault LED.
LED Mode, Bit Encoding (read only from pins):
Global LED Control Register
R/W
0B1
Bit 5
Bit 4
Mode Selected
0
0
Mode 1
0
1
Mode 2
1
0
Mode 3
1
1
Reserved
Global Fault LED, Bit Encoding:
Bits 3 : 2
0 0
0 1
2
1 0
1 1
3
Modes 1 & 3
Mode 2
LED off
LED off
Hardware control
Hardware control
Reserved
LED slow blink
LED off
LED on steady
1. R = Read only; W = Write only; R/W = Read /Write.
2. Default value if manager is not present.
3. Default value if manager is present.
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 69. Configuration Registers (Continued)
Name
Type1
Addr
Description
This register provides a measure of software control over the
port LEDs. Refer to Table 74 on page 91 for bit assignments.
During reset, the state of this register is all 1s. If a manager is
present, this register remains in the all 1s state after reset.
Otherwise, the bits default to hardware control. Encoding is as
follows:
Port LED Control Register
R/W
Bits 1 : 0
0B2
Modes 1 & 3
Mode 2
LED off
LED off
0 0
0 1
LED Timer Control Register
R/W
0B3
Reserved
LED fast blink
1 0
2
Hardware Control
Hardware Control
1 1
3
LED off
LED on steady
Refer to Table 75 on page 91 for bit assignments. Bits 8-15 of
this register set the fast blink frequency of the LEDs. Bits 0-7 set
the slow blink frequency. The same formula is used in each case,
with a maximum of 128 Hz and a minimum of 0.5 Hz.
Example:
fast blink = x32 (0.4 sec)
slow blink = xCC (1.6 sec)
Repeater Reset Register
W
0B5
Writing any data value to this register with the Least Significant
Bit (LSB) = 1 causes the repeater functional logic to reset. (All
bits other than LSB do not matter.) The counters and
configuration information will be held static and will not be reset.
(default = 0s)
Software Reset Register
W
0B6
Writing any data value to this register with the Least Significant
Bit (LSB) = 1 is identical to a hardware reset. (All bits other than
LSB do not matter.) Everything is reset except the Source
Address RAM. (default = 0s)
W
188, 189
Refer to Table 76 on page 91 for bit assignments. Writing a valid
48-bit ID (one that matches the EPROM ID) to this register
causes the device to change its Hub ID to the contents of the
EPROM ID register listed below. This register cannot be read.
R
190, 191
These two registers contain the 48-bit ID read in from EPROM at
power-up. Refer to Table 77 on page 91 for bit assignments.
Assign Address Register
(1 and 2)
EPROM Address Register
(1 and 2)
1. R = Read only; W = Write only; R/W = Read /Write.
2. Default value if manager is not present.
3. Default value if manager is present.
5.4.1
Repeater Configuration Register
This register contains many of the global repeater settings. The Repeater Configuration Register is
described in Table 71. Refer to Table 70 on page 90 for bit assignments of the Repeater
Configuration Register.
Datasheet
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 70. Repeater Configuration Register Bit Assignments
31:13
12
11
10
9
8
7
6
5
4
3
2
1:0
Reserved
Enable
Port
Late
Event
Auto
Clear
Stats
Enable
Send
/T/R
Iso
100
Iso
10
Uni-cast
Frame
Count
Arbit
Input
Value
Zero
Cntrs
Enable
FIFO
Error
Enable
Manchst
r Code
Violation
Reserved
Table 71. Repeater Configuration Register Bit Definitions
Bit
Name
Type1
31:13
Reserved
R/W
Reserved - Write as ‘0s; ignore on read.
12
Enable PortN
Late Event
R/W
A ‘0’ does not allow out-of-window collisions to increment portN’s Late Event
Counter. A ‘1’ does allow it.
0
11
Auto-Clear
R/W
A ‘0’ causes Interrupt Status Register and Search Port Match Register to
automatically clear when read.
A ‘1’ requires that the appropriate register bits be written to be cleared. This is
done by writing a ‘1’ to the bit(s) that are to be cleared.
0
10
Statistics
Enable
R/W
Turns statistics gathering on and off.
A ‘1’ enables statistics gathering. ‘0’ disables statistics gathering.
1
9
Send /T/R
R/W
Forces a good /T/R after each 100 Mbps transmission.
A ‘1’ forces /T/R. ‘0’ disables forced /T/R.
0
8
Isolate 100
R/W
Isolates the IR100CFS stack signal and provides an output pin for disabling an
external backplane transceiver.
A ‘1’ isolates. ‘0’ does not isolate.
0
7
Isolate 10
R/W
Isolates the IR10COL and IR10CFS signals and provides an output pin for
disabling an external backplane transceiver.
A ‘1’ isolates. ‘0’ does not isolate.
0
6
CountMode
R/W
Changes the definition of portReadableFrames to only count Unicast Frames.
A ‘1’ counts Unicast only. ‘0’ counts all.
0
5
Arbitration Input
Value
R
4
Zero Counters
R/W
A ‘1’ causes the LXT980 to sequentially walk through each counter location
and zero its contents2. When all counter locations have been cleared3, this bit
will be reset to a ‘0’.
0
3
Enable FIFO
error
R/W
When set to ‘1’, the LXT980 enters transmit collision upon detection of a data
rate mismatch.
1
2
Enable
Manchester
Code Violation
R/W
When set to ‘1’, the LXT980 enters transmit collision upon detection of a
Manchester code violation (10 Mbps only)
0
1:0
Reserved
R/W
Reserved - Write as ‘0s; ignore on read.
Description
As read from input pin.
Default
N/A
N/A
N/A
1. R = Read only; R/W = Read/Write.
2. While zeroing is in progress, the CPU will be locked out from accessing the statistics RAM until the Zero Counters bit has
been reset back to ‘0’. This will be approximately 15 µs.
3. The rptrMonitorPortBroadcastPkts and rptrMonitorPortMulticastPkts counters (refer to Table 51 on page 80) are not cleared
by the Zero Counters bit.
90
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
-
Table 72. Device/Revision Register Bit Assignment
31:28
27:12
11:8
7:1
0
Version
Part No.
Jedec Continuation Characters
JEDEC ID1
1st in Chain2
0000 0011 1101 0100
0000
111 1110
See Note 2
0100
(LXT980)
0110
(LXT980A)
1. The JEDEC ID is an 8-bit identifier. However, the MSB is for parity only and is ignored.
Intel’s JEDEC ID is FE (1111 1110) which becomes 111 1110.
2. First Chain Bit = 0 if ChipID ≠ 000.
First Chain Bit = 1 if ChipID = 000.
Table 73. Global LED Control Register Bit Assignments
31:6
5
4
Reserved
3
Mode Control
2
1:0
Global Fault LED
Reserved
Table 74. Port LED Control Register Bit Assignments
31:10
9
8
Rsvd
Port 5 (MII)
7
6
5
Port 4
4
3
Port 3
2
1
Port 2
0
Port 1
Table 75. LED Timer Control Register Bit Assignments
31:16
15:8
7:0
Reserved
Slow Blink Frequency
Fast Blink Frequency
1. Period = 7.8125 ms x (Register
Value + 1)
1
2.Frequency = -------------------------------------------------------------------------------------------------------------------------------------------------------------------7.8125ms × ( RegisterValue
RegisterValue ++ 11))
Table 76. Address Assignment Register Bit Assignments
31:0
Assign
Addr 1
Assign
Addr 2
Bits (47:16) of the EPROM Serial number
31:21
20:16
15:0
Zeros
Hub ID(4:0)
Bits (15:0) of the EPROM serial number
Table 77. EPROM Address Register Bit Assignments
31:0
EPROM
Addr 1
EPROM
Addr 2
Datasheet
Bits(47:16) of the EPROM serial number
31:16
15:0
Zero’s
Bits (15:0) of the EPROM serial number
91
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
5.5
Auto-Negotiation Registers
Table 78. Auto-Negotiation Registers
size
bits
Addr
Type1
Auto-Negotiate Link Partner Ability #1 (Port 1)
16
09E
R
Auto-Negotiate Link Partner Ability #2 (Port 2)
16
09F
R
Auto-Negotiate Link Partner Ability #3 (Port 3)
16
0A0
R
Auto-Negotiate Link Partner Ability #4 (Port 4)
16
0A1
R
Auto-Negotiate Status #1 (Port 1)
16
0A2
R
Auto-Negotiate Status #2 (Port 2)
16
0A3
R
Auto-Negotiate Status #3 (Port 3)
16
0A4
R
Auto-Negotiate Status #4 (Port 4)
16
0A5
R
Auto-Negotiate Advertisement #1 (Port 1)
16
0A6
R/W
Auto-Negotiate Advertisement #2 (Port 2)
16
0A7
R/W
Auto-Negotiate Advertisement #3 (Port 3)
16
0A8
R/W
Auto-Negotiate Advertisement #4 (Port 4)
16
0A9
R/W
Auto-Negotiate Configuration
8
0AA
R/W
Name
Description
Refer to Table 79 on page 92
Refer to Table 80 on page 93
Refer to Table 81 on page 93
Refer to Table 82 on page 94
1. R = Read only; R/W = Read/Write.
Table 79. Auto-Negotiation Link Partner Ability Registers
Bit
Name
15
Next Page
14
Acknowledge
13
Remote Fault
12:10
9
8
7
Reserved
100BASE-T4
Description
1 = Link Partner has ability to send multiple pages
0 = Link Partner has no ability to send multiple pages
1 = Link Partner has received Link Code Word from LXT980
0 = Link Partner has not received Link Code Word from LXT980
1 = Remote fault.
0 = No remote fault.
Write as 0, ignore on read
1 = Link Partner is 100BASE-T4 capable.
0 = Link Partner is not 100BASE-T4 capable.
100BASE-TX
1 = Link Partner is 100BASE-TX full-duplex capable.
full-duplex
0 = Link Partner is not 100BASE-TX full-duplex capable.
100BASE-TX
1 = Link Partner is 100BASE-TX capable.
0 = Link Partner is not 100BASE-TX capable.
Type 1
Default
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
1. R = Read only.
92
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 79. Auto-Negotiation Link Partner Ability Registers (Continued)
Bit
6
5
Name
Description
10BASE-T
1 = Link Partner is 10BASE-T full-duplex capable.
full-duplex
0 = Link Partner is not 10BASE-T full-duplex capable.
10BASE-T
1 = Link Partner is 10BASE-T capable.
0 = Link Partner is not 10BASE-T capable.
Type 1
Default
R
N/A
R
N/A
R
N/A
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
4:0
Selector Field
<00000> = Reserved for future Auto-Negotiation development.
<11111> = Reserved for future Auto-Negotiation development.
Unspecified or reserved combinations shall not be transmitted.
1. R = Read only.
Table 80. Auto-Negotiation Status Registers
Bit
15:5
Name
Description
Reserved
Write as zero, ignore on read.
4
Parallel
Detection Fault
1 = More than one of the PMAs detects a valid link.
3
Link Partner Next
Page Able
1 = Link partner is next page able.
2
Next Page Able
1
Page Received
0
Link Partner
Auto-Negotiation
Able
Type1
Default
R
0 = No conflict.
0 = Link partner is not next page able.
0 = Local device is not next page able.
1 = Three identical and consecutive link code words have been
received from link partner.
0 = Three identical and consecutive link code words have not been
received from link partner.
1 = Link partner is auto-negotiate able.
0 = Link partner is not auto negotiate able.
R/LH
R
R
R/LH
R/LH
1. R = Read only; LH = Latching high.
Table 81. Auto-Negotiation Advertisement Register
Bit
Name
15
Next Page
14
Reserved
13
12:10
9
Remote Fault
Description
1 = Phy has ability to send multi-pages.
0 = Phy has no ability to send multi-pages.
Write as zero, ignore on read.
1 = Remote fault.
0 = No remote fault.
Type 1
Default
R
0
R
0
R/W
0
Reserved
Write as zero
R
0
100BASE-T4
1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
R
0
The LXT980 does not support 100BASE-T4 operation.
1. R = Read only; R/W = Read/Write.
2. These settings are determined by the port speed control register and the auto negotiate configuration register.
Datasheet
93
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Table 81. Auto-Negotiation Advertisement Register (Continued)
Type 1
Default
1 = DTE is 100BASE-TX full-duplex capable.
0 = DTE is not 100BASE-TX full-duplex capable.
R
0
100BASE-TX
1 = DTE is 100BASE-TX capable.
0 = DTE is not 100BASE-TX capable.
R2
1
6
10BASE-T FD
1 = DTE is 10BASE-T full-duplex capable.
0 = DTE is not 10BASE-T full-duplex capable.
R
0
5
10BASE-T
1 = DTE is 10BASE-T capable.
0 = DTE is not 10BASE-T capable.
R2
1
R
00001
Bit
Name
8
100BASE-TX FD
7
Description
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
4:0
Selector Field,
<00000> = Reserved for future auto-negotiation development.
<11111> = Reserved for future auto-negotiation development.
Unspecified or reserved combinations should not be transmitted.
1. R = Read only; R/W = Read/Write.
2. These settings are determined by the port speed control register and the auto negotiate configuration register.
Table 82. Auto-Negotiation Configuration Register
Bit
7
6
5
4
Type1
Default
W
0
Writing a ‘1’ causes the port to renegotiate if its Auto-Negotiate Enable
bit is set to ‘1’. Writing a ‘1’ to this bit overrides the port external
configuration settings.
W
0
These bits are self-clearing.
W
0
W
0
R/W
1
R/W
1
R/W
1
R/W
1
Name
Description
Restart Negotiate
(Port 4)
Restart Negotiate
(Port 3)
Restart Negotiate
(Port 2)
Restart Negotiate
(Port 1)
Auto-Negotiate
Enable (Port 4)
1 = Port auto negotiate is enabled.
2
Auto-Negotiate
Enable (Port 3)
1
Auto-Negotiate
Enable (Port 2)
Enabling auto-negotiation via software requires writing to both the Port
Speed Control Register and the Auto-Negotiate Configuration Register
(see Table 61 on page 85).
0
Auto-Negotiate
Enable (Port 1)
3
0 = Port auto negotiate is not enabled.
If Auto negotiate is not enabled, the port will take on the speed forced
values set in the port speed control register. If auto negotiate is enabled,
all abilities will be advertised. Forcing a port speed via the port speed
control register (refer to Table 61 on page 85) will always override and
disable auto-negotiation.
1. W = Write; R/W = Read/Write.
94
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
6.0
Mechanical Specifications
Figure 42. Package Specifications
208-Pin Plastic Quad Flat Package
• Part Numbers:
• LXT980QC
• LXT980AHC
• Commercial Temperature Range (0°C to 70°C)
Millimeters
Dim
D
Min
Max
A
-
4.10
A1
0.25
-
A2
3.20
3.60
D1
e
E1
b
0.17
0.27
D
30.30
30.90
D1
27.70
28.30
E
30.30
30.90
E1
27.70
E
e/
2
e
θ2
L
L1
A2
θ
A1
θ3
L
Datasheet
0.50
0.75
1.30 REF
L1
A
28.30
.50 BASIC
q
0°
7°
θ2
5°
16°
θ3
5°
16°
b
95