. Preliminary IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25µ CMOS technology • Synchronous Register-Latch Mode of Operation with Self-Timed Late Write • Single Differential PECL Clock • Latched Outputs • Common I/O • 30Ω Drivers • Asynchronous Output Enable and Power Down Inputs • +3.3V Power Supply, Ground, 2.5V VDDQ • Boundary Scan using limited set of JTAG 1149.1 functions • 2.5V LVTTL Input and Output levels • Byte Write Capability & Global Write Enable • Registered Addresses, Write Enables, Synchronous Select, and Data Ins • 7 x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order Description IBM0436A4ANLAB, IBM0436A8ANLAB, IBM0418A4ANLAB, and IBM0418A8ANLAB are 4Mb and 8Mb Synchronous Register-Latch Mode, high-performance CMOS Static Random Access Memories (SRAMs). These SRAMs are versatile, have a wide input/output (I/O) interface, and can achieve cycle times as short as 4.5ns. Differential K clocks are used to initiate the read/write operation; all internal operations are self-timed. At the rising crlL3325.03 08/06/2001 edge of the K clock, all address, write-enables, sync select, and data input signals are registered internally. Data outputs are updated from output registers off the falling edge of the K clock. An internal write buffer allows write data to follow one cycle after addresses and controls. The device is operated with a single +3.3V power supply and is compatible with 2.5V LVTTL I/O interfaces. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary x36 BGA Pinout (Top View) 1 2 3 4 5 6 7 A VDDQ SA SA NC SA SA VDDQ B NC NC SA NC SA NC,SA(8Mb) NC C NC SA SA VDD SA SA NC D DQ19 DQ18 VSS NC VSS DQ9 DQ10 E DQ22 DQ20 VSS SS VSS DQ11 DQb13 F VDDQ DQ21 VSS G VSS DQ12 VDDQ G DQ24 DQ23 SBWc NC SBWb DQ14 DQb15 H DQ25 DQ26 VSS NC VSS DQ17 DQb16 J VDDQ VDD NC VDD NC VDD VDDQ K DQ34 DQ35 VSS K VSS DQ8 DQ7 L DQ33 DQ32 SBWd K SBWa DQ5 DQ6 M VDDQ DQ30 VSS SW VSS DQ3 VDDQ N DQ31 DQ29 VSS SA VSS DQ2 DQ4 P DQ28 DQ27 VSS SA VSS DQ0 DQ1 M2* SA NC SA NC ZZ NC VDDQ R NC SA M1* VDD T NC NC SA SA U VDDQ TMS TDI TCK TDO * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VDD and VSS respectively. x18 BGA Pinout (Top View) 1 2 3 4 5 6 7 A VDDQ SA SA NC SA SA VDDQ B NC NC SA NC SA NC,SA(8Mb) NC C NC SA SA VDD SA SA NC D DQ14 NC VSS NC VSS DQ0 NC NC DQ1 DQ2 VDDQ E NC DQ15 VSS SS VSS F VDDQ NC VSS G VSS G NC DQ16 SBWb NC NC NC DQ3 H DQ17 NC VSS NC VSS DQ4 NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQ13 VSS K VSS NC DQ8 L DQ12 NC NC K SBWa DQ7 NC M VDDQ DQ10 VSS SW VSS NC VDDQ N DQ11 NC VSS SA VSS DQ6 NC P NC DQ9 VSS SA VSS NC DQ5 R NC SA M1 VDD M2 SA NC T NC SA SA NC SA SA ZZ U VDDQ TMS TDI TCK TDO NC VDDQ * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VDD and VSS respectively. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 24 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Pin Description SA0-SA18 Address Input SA0-SA18 for 512K x 18 SA0-SA17 for 256K x 36 SA0-SA17 for 256K x 18 SA0-SA16 for 128K x 36 TDO DQ0-DQ35 Data I/O DQ0-DQ17 for 512K x 18 DQ0-DQ35 for 256K x 36 G Asynchronous Output Enable K, K Differential Input Register Clocks SS Synchronous Select SW Write Enable, Global M1, M2 IEEE 1149.1 Test Output (LVTTL level) Clock Mode Inputs. Selects Single or Dual Clock Operation. SBWa Write Enable, Byte a (DQ0-DQ8) VDD Power Supply (+3.3V) SBWb Write Enable, Byte b (DQ9-DQ17) VSS Ground SBWc Write Enable, Byte c (DQ18-DQ26) VDDQ SBWd Write Enable, Byte d (DQ27-DQ35) ZZ Synchronous Sleep Mode IEEE® 1149.1 Test Inputs (LVTTL levels) NC No Connect TMS, TDI, TCK Output Power Supply Ordering Information Part Number Organization Speed Leads IBM0436A8ANLAB - 4H 256K x 36 4.5ns Access / 4.5ns Cycle 7 x 17 BGA IBM0436A8ANLAB - 5 256K x 36 5.0ns Access / 5.0ns Cycle 7 x 17 BGA IBM0436A8ANLAB - 5H 256K x 36 5.5ns Access / 5.5ns Cycle 7 x 17 BGA IBM0436A4ANLAB - 4H 128K x 36 4.5ns Access / 4.5ns Cycle 7 x 17 BGA IBM0436A4ANLAB - 5 128K x 36 5.0ns Access / 5.0ns Cycle 7 x 17 BGA IBM0436A4ANLAB - 5H 128K x 36 5.5ns Access / 5.5ns Cycle 7 x 17 BGA IBM0418A4ANLAB - 4H 256K x 18 4.5ns Access / 4.5ns Cycle 7 x 17 BGA IBM0418A4ANLAB - 5 256K x 18 5.0ns Access / 5.0ns Cycle 7 x 17 BGA IBM0418A4ANLAB - 5H 256K x 18 5.5ns Access / 5.5ns Cycle 7 x 17 BGA IBM0418A8ANLAB -4H 512K x 18 4.5ns Access / 4.5ns Cycle 7 x 17 BGA IBM0418A8ANLAB -5 512K x 18 5.0ns Access / 5.0ns Cycle 7 x 17 BGA IBM0418A8ANLAB -5H 512K x 18 5.5ns Access / 5.5ns Cycle 7 x 17 BGA crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Row Decode WR_BUF0 WR_BUF1 ZZ MATCH1 MATCH LATCH DOC_Array0 Col Decode Read/Wr Amp WRITE SS DOC_MUX0 2:1 MUX SBW0 REG READ K WRITE1 ADD REG SA0-SA18 SBW REG READ ADD REG SBW WRITE0 ADD REG Block Diagram SW DOC_MUX2 2:1 MUX LATCH0 SW0 REG SW1 REG DOC_MUX1 2:1 MUX DOC_ DOUT0 G ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 24 DQ0-DQ35 crlL3325.03 08/06/2001 Preliminary IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM SRAM Features Late Write The Late Write function allows for write data to be registered one cycle after addresses and controls. This feature eliminates one bus-turnaround cycle, necessary when going from a read to a write operation. Late write is accomplished by buffering write addresses and data so that the write operation occurs during the next write cycle. When a read cycle occurs after a write cycle, the address and write data information are stored temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array is updated with address and data from the holding registers. Read cycle addresses are monitored to determine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last written address has new byte data from the write buffer and remaining bytes from the SRAM array. Mode Control Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM supports single clock, register latch operation (M1 = VDD, M2 = VSS). This datasheet describes single clock register latch functionality only. Mode control inputs must be set at power up and must not change during SRAM operation. This SRAM is tested only in the register-latch mode. Sleep Mode The sleep mode is enabled by switching the synchronous signal ZZ High. When the SRAM is in the sleep mode, the outputs go to a High-Z state and the SRAM draws standby current. SRAM data is preserved and a recovery time (tZZR) is required before the SRAM resumes normal operation. Power-Up Requirements To ensure the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up time after VDD reaches its operating range. Power-Up and Power-Down Sequencing The power supplies must be powered up in the following order: VDD, VDDQ, and Inputs. The power-down sequence must be in the reverse order. VDDQ may not exceed VDD by more than 0.6V. No special tracking between power supplies is required. crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Clock Truth Table K ZZ SS SW SBWa SBWb SBWc SBWd DQ (n) DQ (n+1) MODE L→H L L H X X X X X DOUT 0-35 Read Cycle All Bytes L→H L L L L H H H X DIN 0-8 Write Cycle 1st Byte L→H L L L H L H H X DIN 9-17 Write Cycle 2nd Byte L→H L L L H H L H X DIN 18-26 Write Cycle 3rd Byte L→H L L L H H H L X DIN 27-35 Write Cycle 4th Byte L→H L L L L L L L X DIN 0-35 Write Cycle All Bytes L→H L L L H H H H X High-Z Abort Write Cycle L→H L H X X X X X X High-Z Deselect Cycle X H X X X X X X High-Z High-Z Sleep Mode Output Enable Truth Table Operation G DQ Read L DOUT 0-35 Read H High-Z Sleep (ZZ = H) X High-Z Write (SW = L) X High-Z Deselect (SS = H) X High-Z Absolute Maximum Ratings Item Symbol Rating Units Notes VDD -0.5 to 4.3 V 1 VDDQ -0.5 to 2.825 V 1 VIN -0.5 to 4.3 V 1, 2 VDQIN -0.5 to 2.825 V 1 Operating Temperature TA 0 to 85 °C 1 Junction Temperature TJ 110 °C 1 Storage Temperature TSTG -55 to +125 °C 1 Short Circuit Output Current IOUT 25 mA 1 Power Supply Voltage Output Power Supply Voltage Input Voltage DQ Input Voltage 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Excludes DQ inputs. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 24 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Recommended DC Operating Conditions (TA = 0 to +85°C) Parameter Symbol Min. Typ. Max. Units Notes VDD 3.3 - 5% 3.3 3.3 + 10% V 1 VDDQ 2.375 2.5 2.625 V 1 Input High Voltage VIH 1.65 — VDD+0.3 V 1, 2, 4 Input Low Voltage VIL -0.3 — 0.8 V 1, 3, 4 PECL K-Clock Input High Voltage VIH - PECL 2.135 — 2.420 V 1, 2 PECL K-Clock Input Low Voltage VIL - PECL 1.490 — 1.825 V 1 IOUT — 5 8 mA Supply Voltage Output Driver Supply Voltage Output Current 1. 2. 3. 4. All voltages are referenced to VSS. All VDD, VDDQ and VSS pins must be connected. VIH(Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 1.5 V (pulse width ≤ 4.0ns). VIL(Min)DC = - 0.3 V, VIL(Min)AC= -1.5 V (pulse width ≤ 4.0ns). It does not include DQs. DC Electrical Characteristics (TA = 0 to +85°C, VDD = 3.3V -5%, +10%) (Part 1 of 2) Parameter Average Power Supply Operating Current- x36 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) Average Power Supply Operating Current - x18 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) Symbol Min. Max. Units Notes IDD4H IDD5 — 380 340 300 mA 1, 3 — 350 310 270 mA 1, 3 IDD5H IDD4H IDD5 IDD5H Power Supply Standby Current (SS = VIH, ZZ = VIH. All other inputs = VIH or VIH, IIH = 0) ISBSS — 150 mA 1 Power Supply Sleep Current (ZZ = VIH, All other inputs = VIH or VIL, IOUT = 0) ISBZZ — 100 mA 1, 5 Input Leakage Current, any input (except JTAG) (VIN = VSS or VDDQ) ILI -2 +2 µA Output Leakage Current (VOUT = VSS or VDDQ, DQ in High-Z) ILO -5 +5 µA Output “High” Level Voltage (IOH = -8mA) VOH 1.6 VDDQ V 2, 4 Output “Low” Level Voltage (IOL = +8mA) VOL VSS VSS + .4 V 2, 4 1. 2. 3. IOUT = Device Output Current. Minimum Impedance Output Driver. The numeric suffix indicates part operating at speed as indicated in AC Characteristics on page 10: that is, IDD4H indicates 4.5ns cycle time. 4. JEDEC Standard JESD8-6 Class 1 Compatible. 5. When ZZ = High, spec is guaranteed at 75°C junction temperature. 6. For JTAG inputs only. crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary DC Electrical Characteristics (TA = 0 to +85°C, VDD = 3.3V -5%, +10%) (Part 2 of 2) Parameter JTAG Leakage Current (VIN = VSS or VDD) Symbol Min. Max. Units Notes ILIJTAG -50 +10 µA 6 1. IOUT = Device Output Current. 2. Minimum Impedance Output Driver. 3. The numeric suffix indicates part operating at speed as indicated in AC Characteristics on page 10: that is, IDD4H indicates 4.5ns cycle time. 4. JEDEC Standard JESD8-6 Class 1 Compatible. 5. When ZZ = High, spec is guaranteed at 75°C junction temperature. 6. For JTAG inputs only. PBGA Thermal Characteristics Item Symbol Rating Units RΘJC 1 °C/W Thermal Resistance Junction to Case Capacitance (TA = 0 to +85°C, VDD = 3.3V -5%, +10%, f = 1MHz) Parameter Symbol Test Condition Max Units CIN VIN = 0V 4 pF COUT VOUT = 0V 4 pF Input Capacitance Data I/O Capacitance (DQ0-DQ35) AC Test Conditions (TA=0 to +70°C, VDD =3.3V -5%, +10%, VDDQ =2.5V -5%, +5%) Parameter Symbol Conditions Units Notes Output Driver Supply Voltage VDDQ 2.5 Input High Level for 2.5V I/O VIH(2.5V) 2.25 V 2 Input Low Level for 2.5V I/O VIL(2.5V) 0.25 V 2 PECL K-Clock Input High Voltage VIH-PECL 2.4 V PECLK-Clock Input Low Voltage VIL-PECL 1.5 V Input Rise Time TR 1.0 ns Input Fall Time TF 1.0 ns PECL Clock Input Rise Time TR-PECL 0.5 ns PECL Clock Input Fall Time TF-PECL 0.5 ns 1.25 V K and K Cross Point V Input and Output Timing Reference Level (except K,K) PECL Clock Reference Level Output Load Conditions 1 1. See the AC Test Loading figure below. 2. Does not include DQs. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 24 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary AC Test Loading 50 Ω 50 Ω 1.25V Test Sensor 5pF 25 Ω DQ 1.25V 50 Ω 50 Ω 1.25V 5pF crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary AC Characteristics (TA = 0 to +85°C, VDD = 3.3V -5%, +10%, VDDQ = 2.5V). -4H Parameter -5 -5H Symbol Units Min. Max. Min. Max. Min. Max. Notes Cycle Time tKHKH 4.5 — 5.0 — 5.5 — ns Clock High Pulse Width tKHKL 1.5 — 1.5 — 1.5 — ns Clock Low Pulse Width tKLKH 1.5 — 1.5 — 1.5 — ns Clock High to Output Valid tKHQV — 4.5 — 5.0 — 5.5 ns 1 Clock Low to Output Valid tKLQV — 2.0 — 2.25 — 2.5 ns 1 Address Setup Time tAVKH 0.5 — 0.5 — 0.5 — ns Address Hold Time tKHAX 1.0 — 1.0 — 1.0 — ns Sync Select Setup Time tSVKH 0.5 — 0.5 — 0.5 — ns Sync Select Hold Time tKHSX 1.0 — 1.0 — 1.0 — ns Write Enables Setup Time tWVKH 0.5 — 0.5 — 0.5 — ns Write Enables Hold Time tKHWX 1.0 — 1.0 — 1.0 — ns Data In Setup Time tDVKH 0.5 — 0.5 — 0.5 — ns Data In Hold Time tKHDX 1.0 — 1.0 — 1.0 — ns Clock Low to Data Out Hold Time tKLQX 0.5 — 0.5 — 0.5 — ns 1 Clock Low to Output Active tKLQX4 0.5 — 0.5 — 0.5 — ns 1, 2 Clock High to Output High-Z tKHQZ — 2.5 — 2.5 — 2.5 ns 1, 2 Output Enable to High-Z tGHQZ — 2.5 — 2.5 — 2.5 ns 1, 2 Output Enable to Low-Z tGLQX 0.5 — 0.5 — 0.5 — ns 1 Output Enable to Output Valid tGLQV — 1.8 — 1.8 — 1.8 ns 1 Output Enable Setup Time tGHKH 0.5 — 0.5 — 0.5 — ns 1 Output Enable Hold TIme tKHGX 1.5 — 1.5 — 1.5 — ns 1 Sleep Mode Recovery TIme tZZR 200 — 200 — 200 — ns Sleep Mode Enable TIme tZZE — 9.0 — 10.0 — 11.0 ns 1. See the AC Test Loading figure on page 9. 2. Verified by design and tested without guardbands. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 24 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Read and Deselect Cycles Timing Diagram tKLKH tKHKH tKHKL K tAVKH SA A1 A2 A3 tKHAX A3 A4 tKHSX SS tSVKH tWVKH SW tGLQV tKHWX G tGHQZ tKHQX Q1 DQ tGLQX crlL3325.03 08/06/2001 tKHQZ tKHQV Q4 Q3 Q2 tKHQX4 tKHQV ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Read and Write Cycles Timing Diagram tKLKH tKHKH tKHKL K tAVKH SA A2 A1 A3 A2 A4 tKHAX tSVKH SS tKHSX tKHWX tKHWX SW tWVKH tWVKH tKHWX tKHWX SBW tWVKH tWVKH tKLQV G tGHQZ tKHQZ tKLQX4 Q1 DQ D2 tKHQV Q3 D4 Q2 tKHDX tKHQV tDVKH tDVKH tKHDX Notes: 1. D2 is the input data written in memory location A2. 2. Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 24 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Synchronous Sleep Mode Timing Diagram tKHKH tZVKH tZVKH K tKHZX tKHZX ZZ tZZE tZZR DQ Q1 tAVKH tKHQV ADDR A1 tKHAX Note: For tZZR < 200ns, access time will be equal to 2 x tKHQV. crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary IEEE 1149.1 TAP and Boundary Scan The SRAM provides a limited set of JTAG functions as defined in the IEEE Standard 1149.1 that are intended to test the interconnection between SRAM I/Os and the printed circuit board traces or other components. There is no multiplexer in the path from the I/O pins to the SRAM core. In conformance with IEEE Standard 1149.1, the SRAM contains a test access port (TAP) controller, instruction register, boundary scan register, bypass register, and an ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, a test reset (TRST) signal is not required. Signal List • TCK: Test Clock • TMS: Test Mode Select • TDI: Test Data In • TDO: Test Data Out JTAG DC Operating Characteristics (TA = 0 to +85°C) Operates with JEDEC Standard JESD8A (3.3V) logic signal levels Parameter Symbol Min. Typ. Max. Units Notes JTAG Input High Voltage VIH1 2.2 — VDD+0.3 V 1 JTAG Input Low Voltage VIL1 -0.3 — 0.8 V 1 JTAG Output High Level VOH1 2.4 — — V 1, 2 JTAG Output Low Level VOL1 — — 0.4 V 1, 3 1. All JTAG Inputs/Outputs are LVTTL compatible only. 2. IOH1 ≥ -|8mA|. 3. IOL1 ≥ +|8mA|. JTAG AC Test Conditions (TA = 0 to +85°C, VDD = 3.3V -5%, +10%) Parameter Symbol Conditions Units Input Pulse High Level VIH1 3.0 V Input Pulse Low Level VIL1 0.0 V Input Rise Time TR1 2.0 ns Input Fall Time TF1 2.0 ns 1.5 V Input and Output Timing Reference Level ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 24 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary JTAG AC Characteristics (TA = 0 to +85°C, VDD = 3.3V -5%, +10%) Parameter Symbol Min. Max. Units TCK Cycle Time tTHTH 20 — ns TCK High Pulse Width tTHTL 7 — ns TCK Low Pulse Width tTLTH 7 — ns TMS Setup tMVTH 4 — ns TMS Hold tTHMX 4 — ns TDI Setup tDVTH 4 — ns TDI Hold tTHDX 4 — ns TCK Low to Valid Data tTLOV — 7 ns JTAG Timing Diagram tTHTL tTLTH tTHTH TCK tTHMX TMS tMVTH tTHDX TDI tDVTH TDO tTLOV crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Scan Register Definition Register Name Bit Size x18 Bit Size x36 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan * 51 70 * The Boundary Scan chain consists of the following bits: • 36 or 18 bits for Data Inputs, depending on x18 or x36 configuration • 18 bits for SA0 - SA17 in x36, 19 bits for SA0 - SA18 in x18 • 4 bits for SBWa - SBWd in x36, 2 bits for SBWa and SBWb in x18 • 9 bits for K, K, SS, G, SW, ZZ, M1 and M2 • 4bits for Place Holders for 8 Mb, 5bits for Place Holders for 4Mb * K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used for Boundary Scan sampling. ID Register Definition Field Bit Number and Description Part Revision Number (31:28) Device Density and Configuration (27:18) Vendor Definition (17:12) Manufacturer JEDEC Code (11:1) Start Bit(0) 128K x 36 0101 011 010 1100 xxxxxx 000 101 001 00 1 256K x 18 0101 011 100 1011 xxxxxx 000 101 001 00 1 512K x 18 0101 101 111 0011 xxxxxx 000 101 001 00 1 256K x 36 0101 101 101 0100 xxxxxx 000 101 001 00 1 Instruction Set Code Instruction Notes 000 SAMPLE-Z 1 001 IDCODE 010 SAMPLE-Z 1 011 PRIVATE 5 100 SAMPLE 4 101 PRIVATE 5 110 PRIVATE 5 111 BYPASS 2, 3 1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the Shift DR state. 4. SAMPLE instruction does not place DQs in High-Z. 5. This instruction is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality. List of IEEE 1149.1 Standard Violations • 7.2.1.b, e • 7.7.1.a-f • 10.1.1.b, e ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 24 crlL3325.03 08/06/2001 Preliminary IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM • 10.7.1.a-d • 6.1.1.d crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Boundary Scan Order (128K x 36), (256K x 36) (PH = Place Holder) Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 25 DQ12 6F 49 DQ26 2H 2 SA 4P 26 DQ13 7E 50 DQ25 1H 3 SA 4T 27 DQ11 6E 51 SBWc 3G 4 SA 6R 28 DQ10 7D 52 PH2 4D 5 SA 5T 29 DQ9 6D 53 SS 4E 6 ZZ 7T 30 SA 6A 54 PH1 4G 7 DQ0 6P 31 SA 6C 55 PH2 4H 8 DQ1 7P 32 SA 5C 56 SW 4M 9 DQ2 6N 33 SA 5A 57 SBWd 3L 10 DQ4 7N 34 PH1(4Mb), SA(8Mb) 6B 58 DQ34 1K 11 DQ3 6M 35 SA 5B 59 DQ35 2K 12 DQ5 6L 36 SA 3B 60 DQ33 1L 13 DQ6 7L 37 PH1 2B 61 DQ32 2L 14 DQ8 6K 38 SA 3A 62 DQ30 2M 15 DQ7 7K 39 SA 3C 63 DQ29 1N 16 SBWa 5L 40 SA 2C 64 DQ31 2N 17 K 4L 41 SA 2A 65 DQ28 1P 18 K 4K 42 DQ18 2D 66 DQ27 2P 19 G 4F 43 DQ19 1D 67 SA 3T 20 SBWb 5G 44 DQ20 2E 68 SA 2R 21 DQ16 7H 45 DQ22 1E 69 SA 4N 22 DQ17 6H 46 DQ21 2F 70 M1 3R 23 DQ15 7G 47 DQ23 2G 24 DQ14 6G 48 DQ24 1G 1. Input of PH register connected to VSS. 2. Input of PH register connected to VDD. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 24 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Boundary Scan Order (256K x 18), (512K x 18) (PH = Place Holder) Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 27 PH1 2B 2 SA 6T 28 SA 3A 3 SA 4P 29 SA 3C 4 SA 6R 30 SA 2C 5 SA 5T 31 SA 2A 6 ZZ 7T 32 DQ14 1D 7 DQ5 7P 33 DQ15 2E 8 DQ6 6N 34 DQ16 2G 9 DQ7 6L 35 DQ17 1H 10 DQ8 7K 36 SBWb 3G 11 SBWa 5L 37 PH2 4D 12 K 4L 38 SS 4E 13 K 4K 39 PH1 4G 14 G 4F 40 PH2 4H 15 DQ4 6H 41 SW 4M 16 DQ3 7G 42 DQ13 2K 17 DQ2 6F 43 DQ12 1L 18 DQ1 7E 44 DQ10 2M 19 DQ0 6D 45 DQ11 1N 20 SA 6A 46 DQ9 2P 21 SA 6C 47 SA 3T 22 SA 5C 48 SA 2R 23 SA 5A 49 SA 4N 24 PH1(4Mb), SA(8Mb) 6B 50 SA 2T 25 SA 5B 51 M1 3R 26 SA 3B 1. Input of PH register connected to VSS. 2. Input of PH register connected to VDD. crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary TAP Controller State Machine 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 0 1 1 Select IR 1 Capture IR Capture DR 0 0 0 Shift IR 0 Shift DR 1 1 1 1 Exit1 IR Exit1 DR 0 0 0 0 Pause DR Pause IR 1 1 Exit2 DR Exit2 IR 0 0 1 1 Update DR 0 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 24 1 Update IR 1 0 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary 7 x17 BGA Dimensions Top View 22.00 16.764 12.294 12.7 Ref 14.00 Indicates A1 Location Plate Die 0.625 ± .254 Underfill Side View Structural Adhesive 0.1778 Ref Underfill Plate Ello’ Guv’na! 2.549 ± 0.13 0.701 ± 0.099 0.71 ± 0.05 Typ Bottom View 0.84 Ref 20.32 1.27 7.62 0.889 ± 0.04 diam. Solder Ball 1 2 3 4 5 6 7 3.19 Ref A B C D E F G H J K L M N P R T U Note: All dimensions are in millimeters crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary References The following documents give recommendations, restrictions, and limitations for 2nd level attach process: Double Sided 4Mb SRAM Coupled Cap PBGA Card Assembly Guide Qualification information, including the scope of application conditions qualified, is available from your IBM sales representative. Note: This document contains information on products in the sampling and/or initial production phases of development. This information is subject to change without notice. Verify with your IBM field applications engineer that you have the latest version of this document before finalizing a design. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 24 crlL3325.03 08/06/2001 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Revision Log Revision 3/99 Contents of Modification Initial Release. Updated 7 x17 BGA Dimensions on page 21. 7/99 Bit 52 updated. See Boundary Scan Order (128K x 36), (256K x 36) on page 18. Bit 37 updated. See Boundary Scan Order (256K x 18), (512K x 18) on page 19. 12/19/00 02/28/01 Rev. 02. Made various minor editorial changes and format refinements. Rev. 03. Updated DC Electrical Characteristics on page 7. Changed maximum value for Standby current (ISBSS) from 120mA to 150mA. Changed maximum value for Sleep current (ISBZZ) from 65mA to 100mA. 08/06/2001 crlL3325.03 08/06/2001 Rev. 03 release. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 23 of 24 IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM Preliminary Copyright and Disclaimer Copyright International Business Machines Corporation 1999 All Rights Reserved Printed in the United States of America August 2001 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers. Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com crlL3325.03 08/06/2001 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 24 of 24 crlL3325.03 08/06/2001