High Performance, 145 MHz FastFET™ Op Amps AD8065/AD8066 FEATURES APPLICATIONS FET input amplifier 1 pA input bias current Low cost High speed: 145 MHz, −3 dB bandwidth (G = +1) 180 V/µs slew rate (G = +2) Low noise 7 nV/√Hz (f = 10 kHz) 0.6 fA/√Hz (f = 10 kHz) Wide supply voltage range: 5 V to 24 V Single-supply and rail-to-rail output Low offset voltage 1.5 mV max High common-mode rejection ratio: −100 dB Excellent distortion specifications SFDR −88 dB @ 1 MHz Low power: 6.4 mA/amplifier typical supply current No phase reversal Small packaging: SOIC-8, SOT-23-5, and MSOP Instrumentation Photodiode preamps Filters A/D drivers Level shifting Buffering CONNECTION DIAGRAMS VOUT 1 AD8065 5 +VS NC 1 –VS 2 +IN 3 AD8065 –IN 2 4 TOP VIEW (Not to Scale) +IN 3 –IN –VS 4 8 NC 7 +VS 6 VOUT TOP VIEW 5 NC (Not to Scale) 8 +VS –IN1 2 7 VOUT2 +IN1 3 6 –IN2 –VS 4 5 +IN2 TOP VIEW (Not to Scale) 02916-E-001 AD8066 VOUT1 1 Figure 1. GENERAL DESCRIPTION The AD8065/AD80661 FastFET amplifiers are voltage feedback amplifiers with FET inputs offering high performance and ease of use. The AD8065 is a single amplifier, and the AD8066 is a dual amplifier. These amplifiers are developed in the Analog Devices, Inc. proprietary XFCB process and allow exceptionally low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as very high input impedance. operate using only a 6.4 mA/amplifier typical supply current and are capable of delivering up to 30 mA of load current. The AD8065/AD8066 are high performance, high speed, FET input amplifiers available in small packages: SOIC-8, MSOP-8, and SOT-23-5. They are rated to work over the industrial temperature range of −40°C to +85°C. 24 G = +10 VO = 200mV p-p 18 15 G = +5 12 9 G = +2 6 3 G = +1 0 –3 –6 0.1 1 10 100 FREQUENCY (MHz) 1000 02916-E-002 Despite the low cost, the amplifiers provide excellent overall performance. The differential gain and phase errors of 0.02% and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz, make these amplifiers ideal for video applications. Additionally, they offer a high slew rate of 180 V/µs, excellent distortion (SFDR of −88 dB @ 1 MHz), extremely high common-mode rejection of −100 dB, and a low input offset voltage of 1.5 mV maximum under warmed up conditions. The AD8065/AD8066 21 GAIN (dB) With a wide supply voltage range from 5 V to 24 V, the ability to operate on single supplies, and a bandwidth of 145 MHz, the AD8065/AD8066 are designed to work in a variety of applications. For added versatility, the amplifiers also contain rail-to-rail outputs. Figure 2. Small Signal Frequency Response 1 Protected by U. S. Patent No. 6,262,633. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD8065/AD8066 TABLE OF CONTENTS Specifications..................................................................................... 3 REVISION HISTORY Absolute Maximum Ratings............................................................ 6 2/04—Data Sheet Changed from Rev. D to Rev. E. Updated Format.................................................................Universal Updated Figure 56 ......................................................................... 21 Updated Outline Dimensions...................................................... 25 Updated Ordering Guide.............................................................. 26 ESD Caution.................................................................................. 6 Maximum Power Dissipation ..................................................... 7 Output Short Circuit .................................................................... 7 Typical Performance Characteristics ............................................. 8 Test Circuits..................................................................................... 15 Theory of Operation ...................................................................... 18 Closed-Loop Frequency Response........................................... 18 Noninverting Closed-Loop Frequency Response .................. 18 Inverting Closed-Loop Frequency Response ......................... 18 Wideband Operation ................................................................. 19 Input Protection.......................................................................... 19 Thermal Considerations............................................................ 20 Input and Output Overload Behavior...................................... 20 Layout, Grounding, and Bypassing Considerations................... 21 Power Supply Bypassing ............................................................ 21 Grounding ................................................................................... 21 Leakage Currents........................................................................ 22 Input Capacitance....................................................................... 22 Output Capacitance ................................................................... 22 Input-to-Output Coupling ........................................................ 23 Wideband Photodiode Preamp ................................................ 23 High Speed JFET Input Instrumentation Amplifier.............. 24 11/03—Data Sheet changed from Rev. C to Rev. D. Changes to Features ........................................................................ 1 Changes to Connection Diagrams ................................................ 1 Updated Ordering Guide................................................................ 5 Updated Outline Dimensions...................................................... 22 4/03—Data Sheet changed from Rev. B to Rev. C. Added SOIC-8 (R) for the AD8065............................................... 4 2/03—Data Sheet changed from Rev. A to Rev. B. Changes to Absolute Maximum Ratings ...................................... 4 Changes to Test Circuit 10 ........................................................... 14 Changes to Test Circuit 11 ........................................................... 15 Changes to Noninverting Closed-Loop Frequency Response 16 Changes to Inverting Closed-Loop Frequency Response ....... 16 Updated Figure 6 .......................................................................... 18 Changes to Figure 7....................................................................... 19 Changes to Figures 10 ................................................................... 21 Changes to Figure 11..................................................................... 22 Changes to High Speed JFET Instrumentation Amplifier....... 22 Changes to Video Buffer............................................................... 22 8/02—Data Sheet changed from Rev. 0 to Rev. A. Added AD8066 ..................................................................Universal Added SOIC-8 (R) and MSOP-8 (RM) ........................................ 1 Edits to General Description ......................................................... 1 Edits to Specifications ..................................................................... 2 New Figure 2 .................................................................................... 5 Changes to Ordering Guide ........................................................... 5 Edits to TPCs 18, 25, and 28........................................................... 8 New TPC 36 ................................................................................... 11 Added Test Circuits 10 and 11..................................................... 14 MSOP (RM-8) added.................................................................... 23 Video Buffer ................................................................................ 24 Outline Dimensions ....................................................................... 25 Ordering Guide........................................................................... 26 Rev. E | Page 2 of 28 AD8065/AD8066 SPECIFICATIONS @ TA = 25°C, VS = ±5 V, RL = 1 kΩ, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Conditions Min Typ G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, −5.5 V to +5.5 V G = −1, −5.5 V to +5.5 V G = +2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 8 V Step 100 100 145 120 50 42 7 175 170 180 55 205 MHz MHz MHz MHz MHz ns ns V/µs ns ns fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 1 MHz, G = +2, VO = 8 V p-p fC = 10 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω −88 −67 −73 24 7 0.6 0.02 0.02 dBc dBc dBc dBm nV/√Hz fA/√Hz % Degree VCM = 0 V, SOIC Package 0.4 1 2 25 1 1 113 130 SOIC Package TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio TMIN to TMAX VO = ±3 V, RL = 1 kΩ 100 −5 to +1.7 See the Theory of Operation section VCM = −1 V to +1 V VCM = −1 V to +1 V (SOT-23) RL = 1 kΩ RL = 150 Ω VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz −85 −82 −4.88 to +4.90 30% Overshoot G = +1 −85 Rev. E | Page 3 of 28 1.5 17 6 10 Unit mV µV/°C pA pA pA pA dB 1000 || 2.1 1000 || 4.5 GΩ || pF GΩ || pF −5.0 to +2.4 −5.0 to +5.0 −100 −91 V V dB dB −4.94 to +4.95 −4.8 to +4.7 35 90 20 V V mA mA pF 5 ±PSRR Max 6.4 −100 24 7.2 V mA dB AD8065/AD8066 @ TA = 25°C, VS = ±12 V, RL = 1 kΩ, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Output Overdrive Recovery Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Conditions Min Typ G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, −12.5 V to +12.5 V G = −1, −12.5 V to +12.5 V G = +2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 10 V Step 100 100 145 115 50 40 7 175 170 180 55 250 Unit MHz MHz MHz MHz MHz MHz ns ns V/µs ns ns fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 1 MHz, G = +2, VO = 10 V p-p fC = 10 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω −100 −67 −85 24 7 1 0.04 0.03 dBc dBc dBc dBm nV/√Hz fA/√Hz % Degree VCM = 0 V, SOIC Package 0.4 1 3 25 2 2 114 130 SOIC Package TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio TMIN to TMAX VO = ±10 V, RL = 1 kΩ 103 −12 to +8.5 See the Theory of Operation section VCM = −1 V to +1 V VCM = −1 V to +1 V (SOT-23) RL = 1 kΩ RL = 350 Ω VO = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz −85 −82 −11.8 to +11.8 30% Overshoot G = +1 −84 Rev. E | Page 4 of 28 1.5 17 7 10 mV µV/°C pA pA pA pA dB 1000 || 2.1 1000 || 4.5 GΩ || pF GΩ || pF −12.0 to +9.5 −12.0 to +12.0 −100 −91 V V dB dB −11.9 to +11.9 −11.25 to +11.5 30 120 25 V V mA mA pF 5 ±PSRR Max 6.6 −93 24 7.4 V mA dB AD8065/AD8066 @ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Conditions Min Typ G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, −0.5 V to +5.5 V G = −1, −0.5 V to +5.5 V G = +2, VO = 2 V Step G = +2, VO = 2 V Step 125 110 155 130 50 43 6 175 170 160 60 MHz MHz MHz MHz MHz ns ns V/µs ns fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 10 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω −65 −50 22 7 0.6 0.13 0.16 dBc dBc dBm nV/√Hz fA/√Hz % Degree VCM = 1.0 V, SOIC Package 0.4 1 1 25 1 1 113 103 105 SOIC Package TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio TMIN to TMAX VO = 1 V to 4 V (AD8065) VO = 1 V to 4 V (AD8066) 100 90 0 to 1.7 See the Theory of Operation section VCM = 1 V to 4 V VCM = 1 V to 2 V (SOT-23) RL = 1 kΩ RL = 150 Ω VO = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz −74 −78 0.1 to 4.85 30% Overshoot G = +1 5 5.8 −78 ±PSRR Rev. E | Page 5 of 28 Max 1.5 17 5 5 Unit mV µV/ºC pA pA pA pA dB dB 1000 || 2.1 1000 || 4.5 GΩ || pF GΩ || pF 0 to 2.4 0 to 5.0 −100 −91 V V dB dB 0.03 to 4.95 0.07 to 4.83 35 75 5 V V mA mA pF 6.4 −100 24 7.0 V mA dB AD8065/AD8066 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering, 10 sec) Rating 26.4 V See Figure 3 VEE − 0.5 V to VCC + 0.5 V 1.8 V −65°C to +125°C −40°C to +85°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. E | Page 6 of 28 AD8065/AD8066 MAXIMUM POWER DISSIPATION TJ = TA + (PD × θ JA ) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS /2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power ) 1.5 MSOP-8 SOIC-8 1.0 SOT-23-5 0.5 0 –60 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board Airflow will increase heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the θJA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the Layout, Grounding, and Bypassing Considerations section. Figure 3 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC (125°C/W), SOT-23 (180°C/W), and MSOP (150°C/W) packages on a JEDEC standard 4-layer board. θJA values are approximations. OUTPUT SHORT CIRCUIT ⎛V V ⎞ V OUT 2 PD = (VS × I S ) + ⎜ S × OUT ⎟ − RL ⎠ RL ⎝ 2 Shorting the output to ground or drawing excessive current for the AD8065/AD8066 will likely cause catastrophic failure. RMS output voltages should be considered. If RL is referenced to VS−, as in single-supply operation, then the total drive power is VS × IOUT. If the rms signal levels are indeterminate, then consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS × I S ) + –40 02916-E-003 The still-air thermal properties of the package and PCB (θJA), ambient temperature (TA), and total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as 2.0 MAXIMUM POWER DISSIPATION (W) The maximum safe power dissipation in the AD8065/AD8066 packages is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die will locally reach the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8065/AD8066. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in the silicon devices, potentially causing failure. (VS /4)2 RL In single-supply operation with RL referenced to VS−, worst case is VOUT = VS/2. Rev. E | Page 7 of 28 AD8065/AD8066 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: ±5 V, CL = 5 pF, RL = 1 kΩ, VOUT = 2 V p-p, Temperature = 25°C. 24 6.9 RL = 150Ω 21 6.8 G = +10 G = +2 VO = 200mV p-p 18 G = +5 15 VOUT = 0.7V p-p 6.6 12 GAIN (dB) GAIN (dB) VOUT = 0.2V p-p 6.7 9 G = +2 6 3 VOUT = 1.4V p-p 6.5 6.4 6.3 6.2 6.1 –3 6.0 1 10 100 1000 FREQUENCY (MHz) 5.9 0.1 02916-E-004 9 VO = 200mV p-p VO = 200mV p-p G = +1 G = +2 4 8 VS = +5V VS = +5V 7 GAIN (dB) VS = ±5V 0 VS = ±12V VS = ±12V 5 –4 4 1 10 100 1000 FREQUENCY (MHz) Figure 5. Small Signal Frequency Response for Various Supplies (See Figure 42) VS = ±5V 6 –2 02916-E-005 GAIN (dB) 2 3 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 8. Small Signal Frequency Response for Various Supplies (See Figure 43) 2 8 VO = 2V p-p G = +1 7 G = +2 VS = +5V VS = ±5V 6 0 VS = ±12V GAIN (dB) VS = ±5V GAIN (dB) 100 Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43) 6 –6 0.1 10 FREQUENCY (MHz) Figure 4. Small Signal Frequency Response for Various Gains 1 1 02916-E-008 –6 0.1 02916-E-007 G = +1 0 –1 VS = ±12V –2 5 4 3 –3 2 –4 10 FREQUENCY (MHz) 100 1000 Figure 6. Large Signal Frequency Response for Various Supplies (See Figure 42) 0 0.1 1 10 FREQUENCY (MHz) 100 1000 02916-E-009 1 02916-E-006 –5 0.1 1 Figure 9. Large Signal Frequency Response for Various Supplies (See Figure 43) Rev. E | Page 8 of 28 AD8065/AD8066 9 8 VO = 200mV p-p G = +1 6 CL = 25pF CL = 25pF RSNUB = 20Ω 6 CL = 55pF CL = 5pF 4 CL = 20pF CL = 25pF GAIN (dB) GAIN (dB) 3 0 CL = 5pF 2 0 –2 –3 –4 –6 1 10 100 1000 FREQUENCY (MHz) –8 0.1 02916-E-010 –9 0.1 Figure 10. Small Signal Frequency Response for Various CLOAD (See Figure 42) VO = 200mV p-p G = +2 1 10 100 1000 FREQUENCY (MHz) 02916-E-013 –6 Figure 13. Small Signal Frequency Response for Various CLOAD (See Figure 43) 8 8 VOUT = 0.2V p-p VOUT = 2V p-p 6 2 5 GAIN (dB) 4 VOUT = 4V p-p 0 4 3 –4 2 –6 1 –8 0.1 0 0.1 10 100 1000 FREQUENCY (MHz) 02916-E-011 –2 1 Figure 11. Frequency Response for Various Output Amplitudes (See Figure 43) RL = 1kΩ VO = 200mV p-p G = +2 1 10 100 1000 FREQUENCY (MHz) 02916-E-014 G = +2 GAIN (dB) RL = 100Ω 7 6 Figure 14. Small Signal Frequency Response for Various RLOAD (See Figure 43) 80 14 120 VO = 200mV p-p G = +2 GAIN (dB) 8 RF = RG = 500Ω, RS = 250Ω 6 4 RF = RG = 1kΩ, RS = 500Ω, CF = 3.3pF 2 RF = RG = 500Ω, RS = 250Ω, CF = 2.2pF 0 60 60 40 0 GAIN 20 –60 0 –120 PHASE (DEGREES) PHASE RF = RG = 1kΩ, RS = 500Ω 10 OPEN-LOOP GAIN (dB) 12 1 10 FREQUENCY (MHz) 100 1000 Figure 12. Small Signal Frequency Response for Various RF/CF (See Figure 43) Rev. E | Page 9 of 28 –20 0.01 0.1 1 10 FREQUENCY (MHz) Figure 15. Open-Loop Response 100 –180 1000 02916-E-015 –4 0.1 02916-E-012 –2 AD8065/AD8066 –40 –30 –40 G = +2 –50 –50 DISTORTION (dBc) HD2 RL = 150Ω –70 HD2 RL = 1kΩ –80 HD3 RL = 1kΩ –90 HD2 G = +2 HD2 G = +1 –80 –90 HD3 RL = 150Ω –100 HD3 G = +1 1 10 –110 0.1 02916-E-016 –120 0.1 100 FREQUENCY (MHz) 1 10 100 FREQUENCY (MHz) 02916-E-019 –100 –110 Figure 19. Harmonic Distortion vs. Frequency for Various Gains (See Figure 42 and Figure 43) Figure 16. Harmonic Distortion vs. Frequency for Various Loads (See Figure 43) –30 –20 –40 –30 G = +2 VS = ±12V F = 1MHz –60 HD2 RL = 150Ω –70 HD3 RL = 150Ω –80 VS = ±12V G = +2 HD2 VO = 20V p-p –40 –90 HD2 RL = 300Ω –100 HD3 VO = 20V p-p –50 DISTORTION (dBc) –50 DISTORTION (dBc) HD3 G = +2 –70 –60 HD2 VO = 10V p-p –70 –80 HD3 VO = 10V p-p –90 HD2 VO = 2V p-p –100 HD3 RL = 300Ω –110 1 2 3 4 5 6 7 8 9 –120 0.1 02916-E-017 –120 0 HD3 VO = 2V p-p –110 10 11 12 13 14 15 OUTPUT AMPLITUDE (V p-p) 1.0 10.0 FREQUENCY (MHz) Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = ±12 V (See Figure 43) 02916-E-020 DISTORTION (dBc) –60 –60 Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes (See Figure 42 and Figure 43) 50 100 RL = 100Ω VS = ±12V 40 NOISE (nV/ Hz) VS = ±5V 35 30 VS = +5V 10 25 15 1 10 FREQUENCY (MHz) Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 21. Voltage Noise Rev. E | Page 10 of 28 10M 100M 1G 02916-E-021 20 02916-E-018 INTERCEPT POINT (dBm) 45 AD8065/AD8066 CL = 5pF G = +1 20ns/DIV 20ns/DIV Figure 22. Small Signal Transient Response 5 V Supply (See Figure 52) 02916-E-025 50mV/DIV 02916-E-022 50mV/DIV G = +1 CL = 20pF Figure 25. Small Signal Transient Response ±5 V (See Figure 42) G = +1 VS = ±12V VOUT = 10V p-p VOUT = 10V p-p VOUT = 4V p-p G5µs = +2 VS = ±12V VOUT = 2V p-p VOUT = 2V p-p 80ns/DIV 80ns/DIV Figure 23. Large Signal Transient Response (See Figure 42) IN OUT OUT 1.5V/DIV 100ns/DIV G = +1 VS = ±5V 100ns/DIV 02916-E-024 1.5V/DIV –IN Figure 26. Large Signal Transient Response (See Figure 43) Figure 24. Output Overdrive Recovery (See Figure 44) 02916-E-027 G = –1 VS = ±5V 02916-E-026 2V/DIV 02916-E-023 2V/DIV Figure 27. Input Overdrive Recovery (See Figure 42) Rev. E | Page 11 of 28 AD8065/AD8066 VIN = 140mV/DIV VIN = 500mV/DIV VOUT – 2VIN +0.1% –0.1% +0.1% t=0 –0.1% t=0 VOUT – 2VIN 2mV/DIV 02916-E-028 10ns/DIV 02916-E-031 64 µs/DIV 2mV/DIV Figure 31. 0.1% Short-Term Settling Time (See Figure 49) Ib (µA) 0 –Ib –10 +Ib –Ib 10 –Ib 5 FET INPUT STAGE –15 0 +Ib –20 Ib (pA) INPUT BIAS CURRENT (pA) –5 42 36 30 24 18 12 6 0 BJT INPUT STAGE Figure 28. Long-Term Settling Time (See Figure 49) –25 –5 +Ib –10 –15 –20 35 45 55 65 75 85 TEMPERATURE (°C) –30 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 COMMON-MODE VOLTAGE (V) 02916-E-032 25 02916-E-029 –25 –30 Figure 32. Input Bias Current vs. Common-Mode Voltage Range (see the Input and Output Overload Behavior section) Figure 29. Input Bias Current vs. Temperature 40 0.3 N = 299 SD = 0.388 MEAN = –0.069 35 0.2 0.1 25 VS = +5V 0 20 VS = ±5V 15 –0.1 VS = ±12V 10 –0.2 –0.3 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 COMMON-MODE VOLTAGE (V) 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 INPUT OFFSET VOLTAGE (mV) Figure 33. Input Offset Voltage Figure 30. Input Offset Voltage vs. Common-Mode Voltage Rev. E | Page 12 of 28 1.5 2.0 02916-E-033 5 02916-E-030 OFFSET VOLTAGE (mV) 30 AD8065/AD8066 100 –30 –40 OUTPUT IMPEDANCE (Ω) 10 CMRR (dB) –50 –60 –70 VS = ±12V –80 1 G = +1 G = +2 0.1 0.01 1 10 100 FREQUENCY (MHz) 0 100 02916-E-034 –100 0.1 100k 1M 10M 100M Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47) Figure 34. CMRR vs. Frequency (See Figure 46) 0.25 VCC – VOH 0.20 0.15 0.10 VOL – VEE 0.05 0 0 10 20 30 40 ILOAD (mA) 70 VCC – VOH 60 50 VOL – VEE 40 30 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 35. Output Saturation Voltage vs. Output Load Current 02916-E-038 OUTPUT SATURATION VOLTAGE (mV) 80 02916-E-035 Figure 38. Output Saturation Voltage vs. Temperature 0 0 –10 –10 –20 VIN = 2V p-p G = +1 –20 CROSSTALK (dB) –PSRR –30 +PSRR –40 –50 –60 –70 –30 –40 –50 –60 –80 –70 –90 –80 B TO A –100 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) 02916-E-036 A TO B Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50) –90 0.1 1 10 100 FREQUENCY (MHz) Figure 39. Crosstalk vs. Frequency (See Figure 51) Rev. E | Page 13 of 28 02916-E-039 OUTPUT SATURATION VOLTAGE (V) 10k FREQUENCY (Hz) 0.30 PSRR (dB) 1k 02916-E-037 VS = ±5V –90 AD8065/AD8066 125 6.60 VS = ±12V 6.55 120 VS = ±5V OPEN-LOOP GAIN (dB) 6.45 VS = +5V 6.40 6.35 VS = ±12V 110 105 100 VS = +5V 95 VS = ±5V 90 6.30 –20 0 20 40 TEMPERATURE (°C) 60 80 02916-E-040 6.25 –40 85 Figure 40. Quiescent Supply Current vs. Temperature for Various Supply Voltages Rev. E | Page 14 of 28 80 0 10 20 30 40 ILOAD (mA) Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages 02916-E-041 SUPPLY CURRENT (mA) 115 6.50 AD8065/AD8066 TEST CIRCUITS SOIC-8 Pinout +VCC +VCC 4.7µF 4.7µF 0.1µF 0.1µF 2.2pF 24.9Ω 499Ω VIN 499Ω 49.9Ω RSNUB FET PROBE FET PROBE AD8065 AD8065 VIN 1kΩ 249Ω CLOAD 1kΩ 0.1µF 0.1µF 4.7µF 02916-E-042 4.7µF –VEE –VEE Figure 42. G = +1 Figure 44. G = −1 +VCC +VCC 4.7µF 4.7µF 0.1µF 0.1µF 2.2pF 499Ω 02916-E-044 49.9Ω 24.9Ω 499Ω FET PROBE RSNUB AD8065 AD8065 NETWORK ANALYZER S22 0.1µF 49.9Ω 1kΩ CLOAD 0.1µF 4.7µF –VEE 4.7µF –VEE Figure 45. Output Impedance G = +1 Figure 43. G = +2 Rev. E | Page 15 of 28 02916-E-045 249Ω 02916-E-043 VIN AD8065/AD8066 +VCC VIN 1V p-p 4.7µF +VCC 49.9Ω 0.1µF 24.9Ω 499Ω 499Ω VIN FET PROBE FET PROBE AD8065 AD8065 49.9Ω 499Ω 1kΩ 0.1µF 4.7µF 4.7µF –VEE –VEE Figure 46. CMRR Figure 48. Positive PSRR +VCC +VCC 4.7µF 4.7µF 0.1µF 0.1µF 2.2pF 499Ω 499Ω 499Ω AD8065 NETWORK ANALYZER S22 976Ω 249Ω TO SCOPE AD8065 VIN 0.1µF 0.1µF 49.9Ω 49.9Ω 4.7µF –VEE 02916-E-047 249Ω 4.7µF –VEE Figure 47. Output Impedance G = +2 Figure 49. Settling Time Rev. E | Page 16 of 28 02916-E-049 499Ω 1kΩ 02916-E-048 0.1µF 02916-E-046 499Ω AD8065/AD8066 +VCC 4.7µF 2.2pF 499Ω 0.1µF 499Ω 24.9Ω 5V 4.7µF 1.5V 0.1µF FET PROBE FET PROBE AD8065 249Ω AD8065 VIN 1kΩ 49.9Ω 1kΩ 02916-E-050 VIN 1V p-p –VEE Figure 50. Negative PSRR Figure 52. Single Supply 24.9Ω FET PROBE 24.9Ω AD8066 +5V 1kΩ 4.7µF 0.1µF RECEIVE SIDE AD8066 VIN 0.1µF 1kΩ 49.9Ω –5V 02916-E-051 4.7µF DRIVE SIDE 1.5V 1.5V Figure 51. Crosstalk—AD8066 Rev. E | Page 17 of 28 02916-E-052 49.9Ω AD8065/AD8066 THEORY OF OPERATION The AD8065/AD8066 are voltage feedback operational amplifiers that combine a laser-trimmed JFET input stage with the Analog Devices eXtra Fast Complementary Bipolar (XFCB) process, resulting in an outstanding combination of precision and speed. The supply voltage range is from 5 V to 24 V. The amplifiers feature a patented rail-to-rail output stage capable of driving within 0.5 V of either power supply while sourcing or sinking up to 30 mA. Also featured is a single-supply input stage that handles common-mode signals from below the negative supply to within 3 V of the positive rail. Operation beyond the JFET input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. The amplifiers operate as if they have a rail-to-rail input and exhibit no phase reversal behavior for common-mode voltages within the power supply. With voltage noise of 7 nV/√Hz and −88 dBc distortion for 1 MHz 2 V p-p signals, the AD8065/AD8066 are a great choice for high resolution data acquisition systems. Their low noise, sub-pA input current, precision offset, and high speed make them superb preamps for fast photodiode applications. The speed and output drive capability of the AD8065/AD8066 also make them useful in video applications. NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE Solving for the transfer function 2π × f crossover (RG + RF ) VO = VI (RF + RG ) s + 2π × f crossover × RG where fcrossover is the frequency where the amplifier’s open-loop gain equals 0 db At dc Closed-loop −3 dB frequency f −3dB = f crossover × The AD8065/AD8066 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in Figure 53. Basic closed-loop frequency response for inverting and noninverting configurations can be derived from the schematics shown. −2π × f crossover × RF VO = VI s (RF + RG ) + 2π × f crossover × RG VO R =− F VI RG Closed-loop −3 dB frequency f −3dB = f crossover × RF VI VI VO A RG VE A VO A = (2π × fcrossover)/s 80 60 40 fcrossover = 65MHz 20 0 0.01 0.1 1 FREQUENCY (MHz) 10 100 Figure 53. Open-Loop Gain vs. Frequency and Basic Connections Rev. E | Page 18 of 28 02916-E-053 OPEN-LOOP GAIN (A) (dB) RG RF + RG RF RG VE RG RF + RG INVERTING CLOSED-LOOP FREQUENCY RESPONSE At dc CLOSED-LOOP FREQUENCY RESPONSE VO RF + RG = VI RG AD8065/AD8066 The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (RF + RG )/RG. This simple model is accurate for noise gains above 2. The actual bandwidth of circuits with noise gains at or below 2 will be higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp. RF A VO Ib+ Figure 54. Voltage Feedback Amplifier DC Errors Figure 54 shows a voltage feedback amplifier’s dc errors. For both inverting and noninverting configurations Also see Figure 16 to Figure 20. The lowest distortion will be obtained with the AD8065 used in low gain inverting applications, since this eliminates common-mode effects. Higher closed-loop gains result in worse distortion performance. INPUT PROTECTION ⎛ R + RF ⎞ ⎛ R + RF ⎞ VO (error ) = I b+ × RS ⎜ G ⎟ ⎟ − I b− × RF + VOS ⎜ G R G ⎝ RG ⎠ ⎠ ⎝ The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG (though with the AD8065 input currents at less than 20 pA over temperature, this is likely not a concern). To include commonmode and power supply rejection effects, total VOS can be modeled as VOS = VOS nom + The closed-loop gain of the application Whether it is inverting or noninverting Amplifier loading Signal frequency and amplitude Board layout Δ VS Δ VCM + PSR CMR VOS nom is the offset voltage specified at nominal conditions, ∆VS is the change in power supply from nominal conditions, PSR is the power supply rejection, ∆VCM is the change in common-mode voltage from nominal conditions, and CMR is the common-mode rejection. WIDEBAND OPERATION Figure 42 through Figure 44 show the circuits used for wideband characterization for gains of +1, +2, and −1. Source impedance at the summing junction (RF || RG) will form a pole in the amplifier’s loop response with the amplifier’s input capacitance of 6.6 pF. This can cause peaking and ringing if the time constant formed is too low. Feedback resistances of 300 Ω to 1 kΩ are recommended, since they will not unduly load down the amplifier and the time constant formed will not be too low. Peaking in the frequency response can be compensated for with a small capacitor (CF) in parallel with the feedback resistor, as illustrated in Figure 12. This shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting G = +2 amplifier. The inputs of the AD8065/AD8066 are protected with back-toback diodes between the input terminals as well as ESD diodes to either power supply. This results in an input stage with picoamps of input current that can withstand up to 1500 V ESD events (human body model) with no degradation. Excessive power dissipation through the protection devices will destroy or degrade the performance of the amplifier. Differential voltages greater than 0.7 V will result in an input current of approximately (|V+ − V−| 0.7 V)/RI, where RI is the resistance in series with the inputs. For input voltages beyond the positive supply, the input current will be approximately (VI − VCC − 0.7)/RI. Beyond the negative supply, the input current will be about (VI − VEE + 0.7)/RI. If the inputs of the amplifier are to be subjected to sustained differential voltages greater than 0.7 V or to input voltages beyond the amplifier power supply, input current should be limited to 30 mA by an appropriately sized input resistor (RI) as shown in Figure 55. RI > (| V+– V– | – 0.7V) RI > 30mA FOR LARGE | V+ – V– | Rev. E | Page 19 of 28 VI RI RI > AD8065 (VI – VEE – 0.7V) 30mA (VI – VEE + 0.7V) 30mA FOR VI BEYOND SUPPLY VOLTAGES VO 02916-E-055 Ib – RS 02916-E-054 VI Actual distortion performance depends on a number of variables: • • • • • +VOS – RG For the best settling times and the best distortion, the impedances at the AD8065/AD8066 input terminals should be matched. This minimizes nonlinear common-mode capacitive effects that can degrade ac performance. Figure 55. Current Limiting Resistor AD8065/AD8066 THERMAL CONSIDERATIONS With 24 V power supplies and 6.5 mA quiescent current, the AD8065 dissipates 156 mW with no load. The AD8066 dissipates 312 mW. This can lead to noticeable thermal effects, especially in the small SOT-23-5 (thermal resistance of 160°C/W). VOS temperature drift is trimmed to guarantee a maximum drift of 17 µV/°C, so it can change up to 0.425 mV due to warm-up effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V. Ib increases by a factor of 1.7 for every 10°C rise in temperature. Ib will be close to 5 times higher at 24 V supplies as opposed to a single 5 V supply. Heavy loads will increase power dissipation and raise the chip junction temperature as described in the Maximum Power Dissipation section. Care should be taken to not exceed the rated power dissipation of the package. INPUT AND OUTPUT OVERLOAD BEHAVIOR The AD8065/AD8066 have internal circuitry to guard against phase reversal due to overdriving the input stage. A simplified schematic of the input stage, including the input-protection diodes and antiphase reversal circuitry, is shown in Figure 56. The circuit is arranged such that when the input commonmode voltage exceeds a certain threshold, the input JFET pair’s bias current will turn OFF, and the bias current of an auxiliary NPN pair will turn ON, taking over control of the amplifier. When the input common-mode voltage returns to a viable operating value, the FET stage turns back ON, the NPN stage turns OFF, and normal operation resumes. The NPN pair can sustain operation with the input voltage up to the positive supply, so this is a pseudo rail-to-rail input stage. For operation beyond the FET stage’s common-mode limit, the amplifier’s VOS will change to the NPN pair’s offset (mean of 160 µV, standard deviation of 820 µV), and Ib will increase to the NPN pair’s base current up to 45 µA (see Figure 32). Switchback, or recovery time, is about 100 ns, see Figure 27. The output transistors of the rail-to-rail output stage have circuitry to limit the extent of their saturation when the output is overdriven. This helps output recovery time. Output recovery from a 0.5 V output overdrive on a ±5 V supply is shown in Figure 24. Rev. E | Page 20 of 28 AD8065/AD8066 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS POWER SUPPLY BYPASSING GROUNDING Power supply pins are actually inputs and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering most of the noise. A ground plane layer is important in densely packed PC boards to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and therefore the high frequency impedance of the path. High speed currents in an inductive ground return will create an unwanted voltage noise. Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. 0.1 µF (X7R or NPO) chip capacitors are critical and should be as close as possible to the amplifier package. The 4.7 µF tantalum capacitor is less critical for high frequency bypassing, and, in most cases, only one is needed per board, at the supply inputs. VCC R1 R5 TO REST OF AMP Q2 VTHRESHOLD Q5 VBIAS D1 R6 R3 Q3 S Q6 D2 D3 R4 VP D4 Q4 S R7 R2 R8 IT1 Q7 IT2 –VEE Figure 56. Simplified Input Stage Rev. E | Page 21 of 28 02916-E-056 Q1 VN AD8065/AD8066 The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding will work against the low impedance created by the bypass capacitor. Place the ground leads of the bypass capacitors at the same physical location. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are effective at lower frequencies, the current return path distance is less critical. LEAKAGE CURRENTS Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the AD8065/AD8066. Any voltage differential between the inputs and nearby runs will set up leakage currents through the PC board insulator, for example, 1 V/100 GΩ = 10 pA. Similarly, any contaminants on the board can create significant leakage (skin oils are a common problem). To significantly reduce leakage, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below, using a multilayer board. INPUT CAPACITANCE Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few pF of capacitance will reduce the input impedance at high frequencies, in turn increasing the amplifier’s gain, causing peaking of the frequency response or even oscillations, if severe enough. It is recommended that the external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance from the input pins on all layers of the board. OUTPUT CAPACITANCE To a lesser extent, parasitic capacitances on the output can cause peaking and ringing of the frequency response. There are two methods to effectively minimize their effect. • As shown in Figure 57, put a small value resistor (RS) in series with the output to isolate the load capacitor from the amp’s output stage. A good value to choose is 20 Ω (see Figure 10). • Increase the phase margin with higher noise gains or add a pole with a parallel resistor and capacitor from −IN to the output. Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring will help to reduce the absorption. Also, low absorption materials, such as Teflon® or ceramic, could be necessary in some instances. AD8065 RS = 20Ω 02916-E-057 Figure 57. Output Isolation Resistor CF RF RSH = 1011Ω IPHOTO CM CS CD CM VO RF Figure 58. Wideband Photodiode Preamp Rev. E | Page 22 of 28 02916-E-058 VB CF + CS VO CL VI AD8065/AD8066 INPUT-TO-OUTPUT COUPLING The preamp’s output noise over frequency is shown in Figure 59. In order to minimize capacitive coupling between the inputs and output, the output signal traces should not be parallel with the inputs. f1 = WIDEBAND PHOTODIODE PREAMP VOLTAGE NOISE (nV/ Hz) Figure 58 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is where I PHOTO × RF 1 + sC F RF where IPHOTO is the output current of the photodiode, and the parallel combination of RF and CF set the signal bandwidth. f CR 2π × RF × C S where fCR is the amplifier crossover frequency, RF is the feedback resistor, and CS is the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics). The value of CF that produces f(45) can be shown to be CF = fCR (CS + CM + 2CD + CF) /CF RF NOISE f2 VEN (CF + CS + CM + 2CD)/CF CS 2π × RF × f CR VEN NOISE DUE TO AMPLIFIER FREQUENCY (Hz) Figure 59. Photodiode Voltage Noise Contributions The pole in the loop transmission translates to a 0 in the amplifier’s noise gain, leading to an amplification of the input voltage noise over frequency. The loop transmission 0 introduced by CF limits the amplification. The noise gain bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. Keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects, which will add to the output noise. Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. Table 5 summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with RF = 50 kΩ, CS = 15 pF, and CF = 2 pF (bandwidth of about 1.6 MHz) are also listed. The frequency response in this case will show about 2 dB of peaking and 15% overshoot. Doubling CF and cutting the bandwidth in half will result in a flat frequency response, with about 5% transient overshoot. Table 5. RMS Noise Contributions of Photodiode Preamp Contributor RF (×2) Amp to f1 Amp (f2 – f1) Amp to (past f2) f3 f1 The stable bandwidth attainable with this preamp is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the amplifier’s summing junction, including CS and the amplifier input capacitance. RF and the total capacitance produce a pole in the amplifier’s loop transmission that can result in peaking and instability. Adding CF creates a 0 in the loop transmission, which compensates for the pole’s effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45° phase margin (f(45)) is defined by the expression f ( 45 ) = f3 = 1 2πRFCF RMS Noise with RF = 50 kΩ, CS = 15 pF, CS = 15 pF 64.5 µV Expression 2 × 4 kT × RF × f 2 × 1.57 2.4 µV VEN × f1 VEN × C S + C M + C F + 2C D × CF f 2 − f1 VEN × C S + C M + C D + 2C F × CF f 3 × 1.57 02916-E-059 VOUT = f2 = 1 2π RF (CF + CS + CM + 2CD) 31 µV 260 µV 270 µV (Total) Rev. E | Page 23 of 28 AD8065/AD8066 VCC 0.1µF 4.7µF RS1 1/2 VN 2.2pF AD8066 0.1µF 4.7µF R2 500Ω VCC VEE 4.7µF 0.1µF R1 500Ω RF = 500Ω VO AD8065 RG 4.7µ F 0.1µ F R3 RF = 500Ω VEE 500Ω VCC 0.1µ F 4.7µF R4 500Ω 1/2 VP 2.2pF AD8066 0.1µ F 4.7µF 02916-E-060 RS2 VEE Figure 60. High Speed Instrumentation Amplifier RF || 0.5(RG). This is the value to be used for matching purposes. HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER VIDEO BUFFER VOUT ⎛ 1 + 1000 ⎞ = (VN − VP ) ⎜ ⎟ ⎝ RG ⎠ For G = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 Ω for 50 Ω source impedance). The bandwidth for G = +1 will be 50 MHz. For higher gains, the bandwidth will be set by the preamp, equaling The output current capability and speed of the AD8065 make it useful as a video buffer, shown in Figure 61. The G = +2 configuration compensates for the voltage division of the signal due to the signal termination. This buffer maintains 0.1 dB flatness for signals up to 7 MHz, from low amplitudes up to 2 V p-p (Figure 7). Differential gain and phase have been measured to be 0.02% and 0.028° at ±5 V supplies. Inamp−3dB = ( f CR × RG )/ (2 × RF ) +VS 0.1µ F 249Ω + VI – 75Ω AD8065 75Ω 0.1µ F Common-mode rejection of the inamp will be primarily determined by the match of the resistor ratios R1:R2 to R3:R4. It can be estimated (δ1 − δ2 ) VO = VCM (1 + δ1) δ2 Rev. E | Page 24 of 28 4.7µ F + VO – –VS 2.2pF 499Ω The summing junction impedance for the preamps is equal to 4.7µ F 499Ω Figure 61. Video Buffer 02916-E-061 Figure 60 shows an example of a high speed instrumentation amplifier with high input impedance using the AD8065/AD8066. The dc transfer function is AD8065/AD8066 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 4 3.00 BSC 8 6.20 (0.2440) 5.80 (0.2284) 5 4.90 BSC 3.00 BSC 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.50 (0.0196) × 45° 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) Figure 62. 8-Lead Standard Small Outline Package Narrow Body [SOIC] (R-8) Dimensions shown in millimeters (inches) 4 2.80 BSC 1 2 3 PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC 1.45 MAX 0.15 MAX 0.50 0.30 SEATING PLANE 0.22 0.08 10° 5° 0° 1.10 MAX 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 64. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 2.90 BSC 5 0.65 BSC 0.15 0.00 COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 1.60 BSC PIN 1 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178AA Figure 63. 5-Lead Small Outline Transistor Package [SOT-23] (RT-5) Dimensions shown in millimeters Rev. E | Page 25 of 28 0.80 0.60 0.40 AD8065/AD8066 ORDERING GUIDE Model AD8065AR AD8065AR-REEL AD8065AR-REEL7 AD8065ART-REEL AD8065ART-R2 AD8065ART-REEL7 AD8066AR AD8066AR-REEL AD8066AR-REEL7 AD8066ARZ1 AD8066ARZ-REEL1 AD8066ARZ-REEL71 AD8066ARM AD8066ARM-REEL AD8066ARM-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Z = Pb-free part. Rev. E | Page 26 of 28 Package Outline R-8 R-8 R-8 RT-5 RT-5 RT-5 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 Branding HRA HRA HRA HIB HIB HIB AD8065/AD8066 NOTES Rev. E | Page 27 of 28 AD8065/AD8066 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02916-0-2/04(E) Rev. E | Page 28 of 28