ST22XJ64 SMARTCARD 32-BIT RISC MCU WITH 64 KBYTES EEPROM AND JAVACARD™ HARDWARE EXECUTION DATA BRIEFING ST22XJ64 FEATURES ■ ■ ■ ■ 32-BIT RISC CPU WITH 24-BIT LINEAR MEMORY ADDRESSING 96 KBYTES USER ROM 4 KBYTES USER RAM 64 KBYTES USER EEPROM ■ ■ 32-BIT RISC CPU ■ ■ ■ ■ ■ DUAL INSTRUCTION SET, JAVACARD™ AND NATIVE 4-STAGE PIPELINE 16 GENERAL PURPOSE 32-BIT REGISTERS, AND 10 SPECIAL REGISTERS 4 MASKABLE INTERRUPT LEVELS SUPERVISOR AND USER MODES SECURITY ■ ■ ■ ■ ■ ■ CPU SECURITY INSTRUCTIONS – Clear all general purpose registers instruction – Hardware DES and 3DES instructions – Fast Multiply and Accumulate instructions for Public Key and Elliptic Curve Cryptography CPU DPA/SPA COUNTERMEASURES RANDOM NUMBER GENERATOR EEPROM FLASH PROGRAMMING MODE CLOCK AND POWER MANAGEMENT VOLTAGE AND CLOCK FREQUENCY SENSORS MEMORY ■ OTHER FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY – Error Correction Code for single bit fail within a 32-bit word – 10 years data retention, 500,000 Erase/Write cycles endurance – 1 to 128 bytes Erase or Program in 2 ms typical HIGH PERFORMANCE MEMORY – Dual memory buses for data and instruction – Byte, Short (2) and Word (4) load and store – Address auto-increment ADVANCED MEMORY PROTECTION – Memory Protection Unit for application firewalling and peripheral access control – Domain switching securely controlled by protected Context Stack – Native/Java, Code/Data memory attributes with 128-byte granularity THREE WORKING STACKS – Java stack with both 16 and 32-bit accesses – User and Supervisor mode stacks ■ ■ HARDWARE ASYNCHRONOUS SERIAL INTERFACE (UART) – Contact assignment compatible ISO 7816-2 – 2 serial IO ports compatible ISO 7816-3 2 USER CONFIGURABLE 12-BIT AND 16-BIT TIMERS WITH INTERRUPT, INTERNAL OR EXTERNAL CLOCK CENTRAL INTERRUPT CONTROLLER WITH UP TO 16 INPUT LINES UP TO 30 MHz INTERNAL CLOCK EXTERNAL CLOCK FROM 1 MHz TO 5 MHz 3 V ± 10% or 5 V ± 10% SUPPLY VOLTAGE TEMPERATURE RANGE -25° C to +85° C POWER SAVING STANDBY MODE ESD PROTECTION GREATER THAN 5000 V UNIQUE IDENTIFICATION PER DIE April 2001 This is Brief Data from STMicroelectronics. Details are subject to change without notice. For complete data, please contact your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: (+33) 4 42 25 87 29 1/7 ST22XJ64 DESCRIPTION 4 4 4 4 The ST22XJ64 is a member of the SmartJ™ platform using a 32-bit Reduced Instruction Set Computer (RISC) core to execute both Native RISC instructions and JavaCard™ 2.1 Technology instruction (bytecodes) directly. See Figure 1 “SmartJ™ Platform Architecture”, on page 3. – Direct JavaCard™ bytecode execution provides high performance advantage over processors that emulate the JavaCard™ bytecode instruction set. – The ST22XJ64 features a 24-bit wide linear addressing capability and includes 96 KBytes of User ROM, 4 KBytes of User RAM and 64 KBytes of User EEPROM. Micromodule Memory and Peripheral accesses are controlled by a Memory Protection Unit that allows to implement firewalls between applications. Wafer Volatile memory and non-volatile memory are accessed via two different buses, allowing simultaneous accesses to code and data. CRYPTOGRAPHY PERFORMANCE The following table provides the cryptographic performances of the ST22XJ64. Table 1 Cryptographic Performances Algorithm RSA 1024 bits RSA 2048 bits DES 1) 2) 2/7 Function Time 1) Signature with CRT 130 ms Signature without CRT2) 380 ms Verification (e=0x10001) 5 ms Signature with CRT Verification (e=0x10001) 780 ms 15 ms Triple (with keys loaded) Single (with keys loaded) Internal clock at 33 MHz CRT: Chinese Reminder Theorem 15 µs Memory load and stores can be performed at byte, short (2-bytes), or word (4-bytes) granularity, with optional pointer auto increment. – The ST22 core includes dedicated DES instructions for Secret Key cryptography, and a fast Multiply and Accumulate instruction for Public Key cryptography (RSA) and Elliptic Curve cryptography. The ST22 core also includes specific instructions for security, such as clear all general purpose registers in a single cycle. – The ST22XJ64 has clock and power management, 2 User configurable Timers, a Central Interrupt Controller and a Random Number Generator. ST22XJ64 ASI .... .... .... RAM RNG SECURITY PO W ER M N G T. TIMER Figure 1 SmartJ™ Platform Architecture ISO 78 16 P ER IPH ER A LS R AM BUS MPU 32-bit R IS C CORE R O M BUS ROM EE PR O M C LO C K M N G T. SCP 16 0b /P RZ – The ST22XJ64 has two execution modes. Java mode is used when JavaCard™ 2.1 bytecodes are being executed. Native mode is used for long JavaCard™ bytecodes, Native methods and system routines. The processor enters Java mode when a dispatch (DISP) instruction is encountered. When executing in Native mode, there are two privilege levels, User and Supervisor. Some instructions can only be executed in Supervisor mode. Instructions are of variable length, from 1 to 4 bytes in Native mode. EMBEDDED SOFTWARE The Hardware Software Interface (HSI) is a set of C interfaces to the ST22XJ64 EEPROM memory and peripherals. The drivers are: – – – – – – – – EEPROM Asynchronous Serial Interface Central Interrupt Controller Timer Random Number Generator Clock Manager Memory Protection Unit Sensors Special instructions exist for single-cycle stack operations, a frequent occurrence in Java code. Short branches and conditional branches within a 1 KByte block or the entire 16 MByte instruction space are supported. Important Notes: ST22XJ64 has four stages of pipeline in Native mode: fetch, decode, execute and write-back. In Java mode, there are five stages of pipeline: bytecode-fetch, bytecode-decode, decode, execute and write-back. – The HSI driver software layer is the only way to have access to the ST22XJ64 peripherals and EEPROM memory for programming or erasing. – Only the OS1) domain can access the HSI software layer. The CPU core has 16 32-bit general purpose registers, as well as 10 special registers of variable length. – The chip also features a very high performance Asynchronous Serial Interface (ASI) to support high speed serial communication protocols compatible with ISO 7816 standards. – It is manufactured using the highly reliable ST CMOS EEPROM technology. 1 In the following the term OS will refer to the software layer that is directly interfaced to the HSI. 3/7 ST22XJ64 SOFTWARE DEVELOPMENT ENVIRONMENT OEM DEVELOPMENT LICENSE TYPES Modularity, flexibility and methodology are the key words for the SmartJ™ Development Tools Platform. Using the same interface, the developers are able to create, compile and debug a project. The ST22XJ64 is a product based on the SmartJ™ Platform. Developers have two types of licenses for access to the technology: The SmartJ™ Integrated Development environment (IDE) includes: – A code Generation chain: C/C++ compiler, assembler and linker. The assembler supports both native and JavaCard™ instruction sets. – An instruction set simulator, a cycle accurate simulator, a C/C++ source level debugger and hardware emulation tools2). 2 4/7 Emulator under development. – STLDA The SmartJ™ Technology License and Distribution Agreement for Standard OEM Developers (Embedded Operating System and Application Software developers) and Card Embedders. They must use the SmartJ™ Hardware Software Interface (HSI) meta-layer communication interface to access the ST22XJ64 hardware resources. The validation of the Embedded Software will be done using the Simulators of the Code Validation Tools chain. – SPTLA 3) The SmartJ™ Platform Technology License Agreement for OEM Platform Developers. The SPTLA is for developers who need to develop a customised architecture using the platform blocks assembled with a proprietary custom hardware plug-in logic block and associated firmware. The complete Code Validation Tools chain including the VHDL Emulator, must be used for both the hardware, software development integration and validation. The complete Code Validation Tool chain is accessible to OEM Platform Developers licensees only. 3 Not yet available. ST22XJ64 Figure 2 ST22XJ64 Hardware Software Interface UPPER LAYER SOFTWARE SmartJ HSI RESET, ABORT, INT, HSI_DCALL ASI EEPROM TIMER RNG MPU CIC HANDLERS driver driver driver driver driver driver CLOCK SENSOR driver driver RESET, ABORT, INT, HSI_DCALL VECTORS CLOCK SENSOR ASI EEPROM TIMER RNG MPU CIC SmartJ HARDWARE Figure 3 SmartJ™ Platform Concept SmartJ Platform ST22 Core Plus ROM RAM EEPROM Size Definition SmartJ IDE SmartJ-Tools Pack-CD SmartJ H/W Development VHDL Library (1) STD PERIPHERALS & SECURITY ASI, Timers, Security Mechanisms,... SmartJ ISO 15408 Certified Embedded Library HSI (2) Memory & Std Peripherals Drivers CRYPTO (2) Certified Crypto Library (DES, 3DES, RSA, SHA,...) CUSTOMS PLUGS-IN (1) SCP 160a/PRZ 1. 2. SmartJ™ Platform Technology License Agreement required SmartJ™ Technology License and Distribution Agreement required 5/7 ST22XJ64 Figure 4 SmartJ™ IDE Figure 5 ST22XJ64 pins CLK I/O0 ST22XJ64 RST I/O1 VCC GND 6/7 ST22XJ64 Figure 6 SmartJ™ Code Generation Tools A s m S o u rc e C /C + + S o u rc e C / C + + C o m p ile r N a t iv e /J a v a A s s e m b le r C /C + + S ta n d a rd L ib r a rie s HSI L ib r a r y O b je c t F ile s L in k e r C ry p to . L ib r a ry D e v ic e S e t - u p A p p lic a tio n S C P 1 6 0 c/P R Z Figure 7 SmartJ™ Code Validation Tools Integrated Development Environment > Console.exe Debugger GUI Third party tools ST PLAYER DEBUGGER CORE ICE Drivers Cycle accurate Simulator Random Instruction Set Simulator Timer ASI (1) JTAG controller VHDL Emulator FPGA Board SMARTJ SmartCard Smart Card Reader SmartCard Pod SCP 160d/PRZ 1. SmartJ™ Platform Technology License Agreement required 7/7