VDD VIN+ T/H VIN– 12-BIT SUCCESSIVE APPROXIMATION ADC VREF SCLK AD7452 SDATA CONTROL LOGIC CS GND t1 CS t2 1 SCLK 2 3 t3 SDATA tCONVERT t5 4 5 0 0 4 LEADING ZEROS 0 14 DB11 DB10 15 t6 t7 t4 0 B 13 DB2 16 t8 DB1 DB0 tQUIET THREE-STATE 1.6mA TO OUTPUT PIN IOL 1.6V CL 25pF 200 A IOH VDD 1 SCLK 2 8 AD7452 VREF VIN+ TOP VIEW 6 VIN– (Not to Scale) CS 4 5 GND SDATA 3 7 0 75 8192 POINT FFT fSAMPLE = 555kSPS fIN = 100kSPS SINAD = 71.7dB THD = –82dB SFDR = –83dB VDD = 4.75V VDD = 5.25V –20 70 –40 VDD = 2.7V –60 65 –80 –100 60 03154-A-005 SINAD (dB) VDD = 3.6V 55 10 100 –120 –140 0 277 100 200 FREQUENCY (kHz) FREQUENCY (kHz) 0 1.0 –10 0.8 –20 0.6 –30 0.4 –40 0.2 –50 0 –60 –0.2 –70 277 –0.4 VDD = 3V –0.6 –80 –90 –0.8 VDD = 5V –100 10 100 1000 FREQUENCY (kHz) –1.0 10000 0 1024 2048 3072 4096 3072 4096 CODE 1.0 0 100mV p-p SINE WAVE ON VDD NO DECOUPLING ON VDD –20 0.8 0.6 0.4 –40 0.2 –60 0 VDD= 3V –0.2 VDD= 5V –80 –0.4 –0.6 –100 –0.8 –120 –1.0 0 100 200 300 400 500 600 700 800 SUPPLY RIPPLE FREQUENCY (kHz) 900 1000 0 1024 2048 CODE 3.0 2.0 2.5 1.5 2.0 1.0 1.5 POSITIVE INL 0.5 1.0 POSITIVE DNL 0 0.5 –0.5 0 NEGATIVE INL –1.5 –0.5 NEGATIVE DNL –2.0 –1.0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 0 3.5 0.5 1.0 1.5 2.0 2.2 2.5 VREF (V) 2.5 8 2.0 7 6 1.5 VDD = 5V 5 1.0 4 POSITIVE DNL 0.5 3 0 VDD = 3V 2 –0.5 NEGATIVE DNL 1 –1.0 0 0 0.5 1.0 1.5 2.2 2.0 2.5 0 0.5 1.0 VREF (V) 5 1.5 2.0 VREF (V) 2.5 3.0 3.5 1.5 2.0 VREF (V) 2.5 3.0 3.5 12.0 4 11.5 3 11.0 2 10.5 1 VDD = 3V VDD = 5V 10.0 POSITIVE INL 0 9.5 –1 NEGATIVE INL 9.0 –2 8.5 –3 8.0 –4 7.5 –5 7.0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 0 0.5 1.0 10,000 9,000 VIN+ = VIN– 10,000 CONVERSIONS fS = 555kSPS 10,000 CODES 8,000 7,000 6,000 5,000 4,000 3,000 2,000 1,000 0 2044 2045 2046 2047 CODE 2048 2049 CAPACITIVE DAC CS B VIN+ A SW1 A SW2 SW3 VIN– B CONTROL LOGIC CS VREF COMPARATOR CAPACITIVE DAC 1LSB = 2 VREF/4096 011...111 011...110 CAPACITIVE DAC VIN+ 000...001 000...000 111...111 CS B A SW1 A B SW2 SW3 VIN– VREF CONTROL LOGIC CS 100...010 100...001 100...000 –VREF 1LSB COMPARATOR CAPACITIVE DAC + VREF – 1LSB 0 LSB ANALOG INPUT (VIN+ –VIN–) 0.1 F 10 F 3V/5V SUPPLY SERIAL INTERFACE VDD VREF p-p CM* VIN+ SCLK AD7452 VREF p-p CM* VIN– SDATA C/ P 4.5 CS 4.0 GND VREF 3.25V 3.5 3.0 2V/2.5V VREF 2.5 COMMON-MODE RANGE 0.1 F 2.0 *CM IS THE COMMON-MODE VOLTAGE. 1.5 1.75V 1.0 0.5 0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 2.5 2V 2.0 VREF p-p VIN+ AD7452 COMMONMODE VOLTAGE VREF p-p 1.5 COMMON-MODE RANGE VIN– 1.0 1V 0.5 0 0 0.25 0.50 0.75 1.00 1.25 VREF (V) 1.50 1.75 2.00 REFERENCE = 2V VIN– COMMON-MODE (CM) CMMIN = 1V CM MAX = 4V 2V p-p VIN+ REFERENCE = 2.5V VIN– COMMON-MODE (CM) CM MIN = 1.25V CMMAX = 3.75V 2.5V p-p VIN+ 0 TA = 25°C VDD = 5V –20 –40 RIN = 1k RIN = 510 –60 –80 RIN = 300 RIN = 10 –100 10 100 INPUT FREQUENCY (kHz) 277 VDD D R1 VIN+ C1 C2 D –50 TA = 25°C –55 VDD –60 –65 D R1 VIN– C2 –70 C1 D –75 VDD = 2.7V VDD = 3.6V –80 –85 –90 10 VDD = 4.75V 100 INPUT FREQUENCY (kHz) VDD = 5.25V 277 3.75V 2.5V 1.25V RF1 RS* RG1 +2.5V GND –2.5V VOCM 51 VIN+ C* AD8138 RG2 AD7452 RS* VIN– VREF C* RF2 *MOUNT AS CLOSE TO THE AD7452 AS POSSIBLE AND ENSURE HIGH PRECISION Rs AND Cs ARE USED. RS–50 ; C–1nF RG1 = RF1 = RF2 = 499 ; RG2 = 523 3.75V 2.5V 1.25V EXTERNAL VREF (2.5V) 220 2 VREF p-p V+ 390 VREF VDD 27 GND V– VIN+ 220 AD7452 220 VIN– V+ VREF 27 A V– 0.1 F 10k EXTERNAL VREF 220 2 GND VREF p-p V+ 390 3.75V 2.5V 1.25V VDD 27 R V– 220 220 VIN+ AD7452 220 VIN– V+ A C R VREF 27 V– 20k R VIN+ 0.1 F AD7452 VIN– VREF 3.75V 2.5V 1.25V 10k EXTERNAL VREF EXTERNAL VREF (2.5 V) VDD AD7452* AD780 NC VDD 0.1 F 10nF 0.1 F 1 OPSEL 8 NC 7 NC 2.5V 2 VIN 3 TEMP VOUT 6 4 GND TRIM 5 NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY NC VREF 0.1 F 5V 2.5V 0V R +2.5V 0V –2.5V R VIN VIN+ R AD7452 R VIN– 0.1 F VREF EXTERNAL VREF (2.5V) CS 10ns t2 SCLK tCONVERT t5 1 2 3 4 5 13 14 t6 15 16 t8 tQUIET tACQUISITION 12.5(1/FSCLK) 1/THROUGHPUT CS SCLK SDATA CS 1 10 16 SCLK SDATA 4 LEADING ZEROS + CONVERSION RESULT 1 2 10 THREE-STATE tPOWER-UP PART BEGINS TO POWER UP CS A THIS PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED 1 10 16 1 10 SCLK SDATA INVALID DATA VALID DATA 16 100 VDD = 5V 10 1 VDD = 3V 0.1 0.01 0 50 100 150 200 250 THROUGHPUT (kSPS) 300 350 ADSP-21xx* AD7452* TMS320C5x/ C54x* AD7452* SCLK SCLK SDATA CS SCLK DR CLKR SDATA RFS CS TFS *ADDITIONAL PINS REMOVED FOR CLARITY CLKx DR FSx FSR *ADDITIONAL PINS REMOVED FOR CLARITY DSP56xxx* AD7452* SCLK SCLK SDATA SRD CS SR2 *ADDITIONAL PINS REMOVED FOR CLARITY 2.90 BSC 8 7 6 5 1 2 3 4 2.80 BSC 1.60 BSC PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC 1.45 MAX 0.15 MAX 0.38 0.22 SEATING PLANE 0.22 0.08 8° 4° 0° COMPLIANT TO JEDEC STANDARDS MO-178BA 0.60 0.45 0.30