54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATEÉ Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. Features Y Alternate Military/Aerospace device (54LS125) is available. Contact a National Semiconductor Sales Office/ Distributor for specifications. Connection Diagram Dual-In-Line Package TL/F/6387 – 1 Order Number 54LS125ADMQB, 54LS125AFMQB, 54LS125ALMQB, DM54LS125AJ, DM54LS125AW, DM74LS125AM or DM74LS125AN See NS Package Number E20A, J14A, M14A, N14A or W14B Function Table YeA Inputs Output A C Y L H X L L H L H Hi-Z H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level Hi-Z e TRI-STATE (Outputs are disabled) TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/6387 RRD-B30M105/Printed in U. S. A. 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol DM54LS125A Parameter DM74LS125A Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage 0.7 0.8 V IOH High Level Output Current b1 b 2.6 mA IOL Low Level Output Current 24 mA TA Free Air Operating Temperature 70 §C 2 2 V 12 b 55 125 V 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIL e Max DM54 0.25 0.4 DM74 0.35 0.5 IOL e 12 mA, VCC e Min DM74 0.25 0.4 2.4 3.4 V V II Input Current @ Max Input Voltage VCC e Max, VI e 7V 0.1 mA IIH High Level Input Current VCC e Max, VI e 2.7V 20 mA IIL Low Level Input Current VCC e Max, VI e 0.4V b 0.4 mA IOZH Off-State Output Current with High Level Output Voltage Applied VCC e Max, VO e 2.4V VIH e Min, VIL e Max 20 mA Off-State Output Current with Low Level Output Voltage Applied VCC e Max, VO e 0.4V VIH e Min, VIL e Max b 20 mA Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max (Note 3) IOZL IOS ICC DM54 b 20 b 100 DM74 b 20 b 100 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with the data control (C) inputs at 4.5V and the data inputs grounded. 2 11 20 mA mA Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 667X Symbol Parameter CL e 50 pF Min Max CL e 150 pF Min Units Max tPLH Propagation Delay Time Low to High Level Output 15 21 ns tPHL Propagation Delay Time High to Low Level Output 18 22 ns tPZH Output Enable Time to High Level Output 25 35 ns tPZL Output Enable Time to Low Level Output 25 40 ns tPHZ Output Disable Time from High Level Output (Note 1) 20 ns tPLZ Output Disable Time from Low Level Output (Note 1) 20 ns Note 1: CL e 5pF. 3 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS125ALMQB NS Package Number E20A 14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS125ADMQB or DM54LS125AJ NS Package Number J14A 4 Physical Dimensions inches (millimeters) (Continued) 14-Lead Small Outline Molded Package (M) Order Number DM74LS125AM NS Package Number M14A 14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS125AN NS Package Number N14A 5 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Flat Package (W) Order Number 54LS125AFMQB or DM54LS125AW NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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