CS5233-3 500 mA and 1.5 A, 3.3 V Dual Input Linear Regulator with Auxiliary Control http://onsemi.com D2PAK 5–PIN DP SUFFIX CASE 936F 1 5 1 PIN CONNECTIONS AND MARKING DIAGRAMS Semiconductor Components Industries, LLC, 2001 May, 2001 – Rev. 5 Pin 1. VSB 2. VIN 3. GND 4. VOUT 5. AuxDrv CS5233–3 AWLYWW 1 VSB 1 VIN VOUT AuxDrv Features • Linear Regulator – 3.3 V ± 2% Output Voltage – Current Limit – Thermal Shutdown with Hysteresis – 400 µA Reverse Current – ESD Protected • System Power Management – Auxiliary Supply Control – “Glitch Free” Transition Between 3 Sources – Similar to CS5231–3 • High Output Current Capability – 1.5 A D2PAK – 500 mA 8 Lead SOIC DF8 • Internally Fused Leads in SO–8 Package SO–8 D SUFFIX CASE 751 8 A WL, L YY, Y WW, W 8 5233– ALYW3 The CS5233–3 provides a glitch–free 3.3 V output from one of three possible supplies, (VIN, VSB and 3.3 VAUX). An on–chip linear regulator powers the output when either VIN or VSB is available. Otherwise AuxDrv turns on an external PFET, which connects the 3.3 VAUX supply to the output. The CS5233–3 is intended to provide power to an ASIC on a PCI Network Interface Card (NIC), and meets Intel’s “Instantly Available” power requirements which follow from the Advanced Configuration and Power Interface (ACPI) standards. Other applications include desktop computers, power supplies with multiple input sources, and PCMCIA interface cards. The CS5233–3 linear regulator provides a fixed 3.3 V output at up to 1.5 A with an overall accuracy of ±2%. The internal NPN–PNP composite pass transistor provides a low dropout voltage and requires less supply current than a straight PNP design. Full protection with both current limit and thermal shutdown is provided. Designed for low reverse current, the IC prevents excessive current from flowing from VOUT to either VIN or ground when the regulator input voltage is lower than the output. The auxiliary drive control feature allows the use of an external PFET to supply power to the output when the regulator supplies are off. The CS5233–3 regulator is available in two package types: the 5 Lead D2PAK package (TO–263) and 8 Lead SOIC with 4 Lead Fused (DF8) package. When powered from the VIN source, the D2PAK is rated for 1.5 A and the 8 Lead SOIC is rated for 500 mA. Both packages are rated for 500 mA when only powered from the VSB source. GND GND GND GND = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device 1 Package Shipping CS5233–3GDP5 D2PAK 50 Units/Rail CS5233–3GDPR5 D2PAK 750 Tape & Reel CS5233–3GDF8 SO–8 95 Units/Rail CS5233–3GDFR8 SO–8 2500 Tape & Reel Publication Order Number: CS5233–3/D CS5233–3 D +3.3 VAUX S G VSB VSB AuxDrv VDD CS5233–3 VIN 10 µF min ESR < 1.0 Ω + ASIC VOUT VIN GND 10 µF min ESR < 1.0 Ω + 10 µF min ESR < 1.0 Ω + GND Figure 1. Application Diagram, 5.0 V to 3.3 V Dual Input Regulator with Auxiliary PFET Power Switch ABSOLUTE MAXIMUM RATINGS* Rating Operating Junction Temperature Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1.) Storage Temperature Range ESD Susceptibility (Human Body Model) Value Unit 150 °C 230 peak °C –65 to +150 °C 2.0 kV 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. ABSOLUTE MAXIMUM RATINGS Pin Name Pin Symbol VMAX VMIN ISOURCE ISINK IC Power Input (Main) VIN 6.0 V –0.3 V 100 mA Internally Limited IC Power Input (Standby) VSB 6.0 V –0.3 V 100 mA Internally Limited Output Voltage VOUT 6.0 V –0.3 V Internally Limited 100 mA Auxiliary Drive Output AuxDrv 6.0 V –0.3 V 10 mA 50 mA IC Ground GND N/A N/A N/A N/A ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 150°C; 4.75 V < VIN; VSB < 6.0 V; COUT ≥ 10 µF with ESR < 1.0 Ω, IOUT = 10 mA; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit 3.234 – 2% 3.3 3.366 + 2% V Linear Regulator Output Voltage 10 mA < IOUT < IMAX. Note 2. Line Regulation IOUT = 10mA; VSOURCE = 4.75 V to 6.0 V. Note 3. – 1.0 5.0 mV Load Regulation VSOURCE = 5.0 V; IOUT = 10 mA to IMAX. Note 2. Note 3. – 5.0 15 mV 2. IMAX = 1.5 A for D2PAK only and with VIN > 4.75 V, otherwise IMAX = 500 mA. 3. Applies to either VIN or VSB. http://onsemi.com 2 CS5233–3 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 150°C; 4.75 V < VIN; VSB < 6.0 V; COUT ≥ 10 µF with ESR < 1.0 Ω, IOUT = 10 mA; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Linear Regulator Ground Current IOUT = 10 mA IOUT = 500 mA IOUT = 1.5 A. Note 4. – – – 2.0 3.0 9.0 3.0 6.0 20 mA mA mA Reverse Current VSOURCE = 0 V; VOUT = 3.3 V. Note 4. – 0.4 1.0 mA Current Limit VIN Input 8 Lead SOIC 5 Lead D2PAK 0 V < VOUT < 3.2 V VIN > 4.25 V 0.55 1.6 0.8 2.4 1.3 4.5 A A Current Limit VSB Input Either Package 0 V < VOUT < 3.2 V; VIN < 4.25 V; VSB > 4.25 V 0.55 0.8 1.3 A Thermal Shutdown Note 5. 150 180 210 °C Thermal Shutdown Hysteresis Note 5. – 25 – °C Auxiliary Drive VIN Turn–On Threshold VSB = 0 V; Ramp VIN up until AuxDrv goes high and regulator turns on 4.35 4.5 4.65 V VIN Turn–Off Threshold VSB = 0 V; Ramp VIN down until AuxDrv goes low and regulator turns off 4.25 4.4 4.55 V VSB Turn–On Threshold VSB = 0 V; Ramp VSB up until AuxDrv goes high and regulator turns on 4.35 4.5 4.65 V VSB Turn–Off Threshold VSB = 0 V; Ramp VSV down until AuxDrv goes low and regulator turns off 4.25 4.4 4.55 V – 75 100 125 mV – – 0.4 0.1 1.8 0.4 V V – 0.1 0.4 V Threshold Hysteresis AuxDrv Peak Voltage VOUT = 0 V; 0 V < VSOURCE < 2.0 V. Note 4. VOUT = 0 V; IAuxDrv = 100 µA; 2.0 V < VIN < 4.25 V; 2.0 V < VSB < 4.25 V VOUT = 3.0 V; IAuxDrv = 100 µA; 0 V < VIN < 4.25 V; 0 V < VSB < 4.25 V AuxDrv High Voltage VIN or VSB > 4.65 V 3.75 4.0 – V AuxDrv Pin Current Limit VAuxDrv = 1.0 V; VSOURCE = 4.0. Note 4. 0.5 6.0 25 mA VAuxDrv Turn–Off Response Time Step VSOURCE from 4.0 V to 5.0 V. Note 4. Note 5. – 20 40 µs VAuxDrv Turn–On Response Time Step VSOURCE from 5.0 V to 4.0 V. Note 4. Note 5. – 1.0 10 µs Pull–Up Resistance VIN = 0 V and VIN > 4.7 V. Note 4. Note 5. 5.0 10 25 kΩ 4. Applies to either VIN or VSB. 5. Guaranteed by design, not 100% production tested. http://onsemi.com 3 CS5233–3 PACKAGE PIN DESCRIPTION Package Lead # 5 Lead D2PAK 8 Lead SO Narrow Lead Symbol 1 1 VSB Standby 5.0 V input voltage. 2 2 VIN 5.0 V Main input voltage. 3, Tab 5, 6, 7, 8 GND Ground and IC substrate connection. 4 3 VOUT Regulated output voltage. 5 4 AuxDrv Function Control voltage for the external PFET switched auxiliary supply. This pin drives low if VIN and VSB are less than 4.4 V (typical), otherwise it is pulled up to the greater of VIN or VSB through an internal diode and 10 kΩ resistor. VIN VOUT VIN UV Comparator ENABLE + – VSB ENABLE VSB UV Comparator + – AuxDrv Current Limit Internal BIAS Error Amplifier Bandgap Reference – + GND Thermal Shutdown Figure 2. Block Diagram http://onsemi.com 4 CS5233–3 TYPICAL PERFORMANCE CHARACTERISTICS 3.310 3.5 3.305 VIN = 5.0 V VSB = 5.0 V 2.5 VOUT (V) Output Voltage (V) 3.0 3.300 2.0 1.5 1.0 3.295 0.5 3.290 0 20 40 60 80 100 Junction Temperature (°C) 0 120 Figure 3. Output Voltage vs. Junction Temperature, Output Voltage when Powered by VIN or VSB 1.0 0.5 0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 4.0 Figure 4. Output Voltage vs. Load Current, VSB Values Taken with VIN = 0 V Reverse Current (µA) Ground Current (mA) 3.5 3.0 VSB = 5.0 V 2.5 VIN = 5.0 V 2.0 460 440 420 1.5 0 0.25 0.50 0.75 1.00 Load Current (A) 1.25 0 1.50 40 60 80 Junction Temperature (°C) 100 Figure 6. Reverse Current vs. Junction Temperature VOUT Figure 5. Ground Pin Current vs. Output Current, VSB Data with VIN = 0 V 20 AuxDrv Output Current VIN 5.0 4.0 Figure 7. Transient Load Response, Transient Response for 1.5 A Step Load, VIN = 5.0 V, COUT = 33 F @ 0.4 ESR Figure 8. AuxDrv Response Time http://onsemi.com 5 120 CS5233–3 4.52 4.5 4.48 4.46 4.44 4.42 VIN Turn–Off Threshold 4.40 4.38 0 20 40 60 80 100 Junction Temperature (°C) 4.4 4.3 VIN = 4.65 V 120 0 Figure 9. VIN Threshold vs. Junction Temperature, Typical Minimum and Maximum Threshold Voltages to Switch AuxDrv Control 20 2.0 0°C 27°C 125°C 0 0 40 60 80 100 Junction Temperature (°C) 120 Figure 10. AuxDrv High Voltage vs. Junction Temperature 4.0 AuxDrv Voltage (V) VIN Threshold Voltage (V) AuxDrv High Voltage (V) VIN Turn–On Threshold 4.50 2.0 Input Voltage (V) 4.0 4.5 Figure 11. AuxDrv Voltage vs. Input Voltage (VSB or VIN) at Three Temperatures http://onsemi.com 6 CS5233–3 APPLICATIONS INFORMATION INPUT AND OUTPUT VOLTAGE MATRIX VIN 0V 0V 0V 0V 5.0 V 5.0 V 5.0 V 5.0 V ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Input VSB 3.3 VAUX 0V 0V 0V 3.3 V 5.0 V 0V 5.0 V 3.3 V 0V 0V 0V 3.3 V 5.0 V 0V 5.0 V 3.3 V ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ AuxDrv/5.0 V Detect VOUT, 5 Lead On (low) 0V On (low) 3.3 VAUX Off (high) 3.3 VREG @ 500 mA Off (high) 3.3 VREG @ 500 mA Off (high) 3.3 VREG @ 1.5 A Off (high) 3.3 VREG @ 1.5 A Off (high) 3.3 VREG @ 1.5 A Off (high) 3.3 VREG @ 1.5 A THEORY OF OPERATION ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Outputs D2PAK VOUT, 8 Lead SOIC 0V 3.3 VAUX 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA load. The AuxDrv is low only when neither VIN nor VSB are available. There is 100 mV of hysteresis (typical) in the circuitry that determines if VIN or VSB are present. Linear Regulator The CS5233–3 is a dual input fixed 3.3 V linear regulator that contains an auxiliary drive control feature. When VIN alone is present, or VIN and VSB are simultaneously present, the CS5233–3 uses the VIN supply to generate the 3.3 V output at currents of up to 1.5 A. When VSB alone is present, the CS5233–3 uses the VSB supply to generate the 3.3 V output at currents of up to 500 mA. The linear regulator is composed of a composite PNP–NPN pass transistor to provide low–voltage dropout capability. An output capacitor greater than 10 µF with equivalent series resistance (ESR) less than 1.0 Ω is required for compensation. More information is provided in the Stability Considerations section. STABILITY CONSIDERATIONS The output capacitor helps determine three main characteristics of a linear regulator: loop stability, load transient response, and start–up delay. The CS5233–3 is designed to be stable with an output capacitor that has a minimum value of 10 µF and an equivalent series resistance less than 1.0 Ω. To guarantee loop stability, the output capacitor should be located close to the regulator output and ground pins. The load transient response, during the time it takes the regulator to respond, is also determined by the output capacitor. For large changes in load current, the ESR of the output capacitor causes an immediate drop in output voltage given by: Auxiliary Drive Feature The CS5233–3 provides an auxiliary drive feature that allows a load to remain powered even if both supplies to the IC are absent. An external p–channel FET is the only additional component required to implement this function when the auxiliary power supply is available. The PFET gate is connected to the IC’s AuxDrv output, the PFET drain is connected to the auxiliary power supply, and the PFET source is connected to the load. The polarity of this connection is very important, since the PFET body diode will be connected between the load and the auxiliary supply. If the PFET is connected with its drain to the load and its source to the supply, the body diode could be forward–biased if the auxiliary supply is not present. This would result in the linear regulator providing current to everything on the auxiliary supply rail. The AuxDrv (5.0 V detect) output is pulled up to the input voltage through an internal resistor when VIN or VSB are available. If VIN and VSB are not available or both drop below 4.4 V, the AuxDrv output goes low, turning on an external PFET that connects the 3.3 V auxiliary supply to the V I ESR There is then an additional drop in output voltage given by: V I TC where T is the time for the regulation loop to begin to respond, (typically 4.0 µs for the CS5233–3). If tight output regulation is required with fast changing loads, a capacitor network of tantalum and low ESR ceramic capacitors can be added as close to the load as possible, with enough capacitance and a reduced ESR to minimize the voltage change, as determined by the formulas above. Input Capacitors and the Vin Thresholds A capacitor placed on the VIN pin will help to improve transient response. During a load transient, the input capacitor serves as a charge “reservoir,” providing the http://onsemi.com 7 CS5233–3 board traces. Such voltage drops can occur in both the supply traces and the return traces. The following board layout practices will help to minimize output voltage errors: • Always place the linear regulator as close to both load and output capacitors as possible. • Always use the widest possible traces to connect the linear regulator to the capacitor network and to the load. • Connect the load to ground through the widest possible traces. • Connect the IC ground to the load ground trace at the point where it connects to the load. needed extra current until the external power supply can respond. One of the consequences of providing this current is an instantaneous voltage drop at VIN due to capacitor ESR. The magnitude of the voltage change is again the product of the current change and the capacitor ESR. It is very important to consider the maximum current step that can exist in the system. If the change in current is large enough, it is possible that the instantaneous voltage drop on VIN will exceed the VIN threshold hysteresis, and the IC will enter a mode of operation resembling an oscillation. As the part turns on, the output current IOUT will increase, reaching current limit during initial charging. Increasing IOUT results in a drop at VIN such that the shutdown threshold is reached. The part will turn off, and the load current will decrease. As IOUT decreases, VIN will rise and the part will turn on, starting the cycle all over again. This oscillatory operation is most likely at initial start–up when the output capacitance is not charged, and in cases where the ramp–up of the VIN supply is slow. It may also occur during the power transition when the linear regulator turns on and the PFET turns off. A 20 µs delay exists between turn–on of the regulator and the AuxDrv pin pulling the gate of the PFET high. This delay prevents “chatter” during the power transitions. If required, using a few capacitors in parallel to increase the bulk charge storage and reduce the ESR should give better performance than using a single input capacitor. Short, straight connections between the power supply and VIN lead along with careful layout of the PC board ground plane will reduce parasitic inductance effects. Wide VIN and VOUT traces will reduce resistive voltage drops. Current Limit The CS5233–3 has internal current limit protection. Output current is limited to a typical value of 3.0 A for the D2PAK using VIN and 800 mA using VSB, even under output short circuit conditions. If the load current drain exceeds the current limit value, the output voltage will be pulled down and will result in an out of regulation condition. Thermal Shutdown The CS5233–3 has internal temperature monitoring circuitry. The output is disabled if junction temperature of the IC reaches 180°C. Thermal hysteresis is typically 25°C and allows the IC to recover from a thermal fault without the need for an external reset signal. The monitoring circuitry is located near the composite PNP–NPN output transistor, since this transistor is responsible for most of the on–chip power dissipation. The combination of current limit and thermal shutdown will protect the IC from nearly any fault condition. Choosing the PFET Switch The choice of the external PFET switch is based on two main considerations. First, the PFET should have a very low turn–on threshold. Choosing a switch transistor with VGS(ON) ≈ 1.0 V will ensure the PFET will be fully enhanced with only 3.3 V of gate drive voltage. Second, the switch transistor should be chosen to have a low RDS(ON) to minimize the voltage drop due to current flow in the switch. The formula for calculating the maximum allowable on–resistance is Reverse Current Protection During normal system operation, the auxiliary drive circuitry will maintain voltage on the VOUT pin. IC reliability and system efficiency are improved by limiting the amount of reverse current that flows from VOUT to ground and from VOUT to VIN. Current flows from VOUT to ground through the feedback resistor divider that sets up the output voltage, typically 400 µA. Current flow from VOUT to VIN will be limited to leakage current after the IC shuts down. On–chip RC time constants are such that the output transistor should be turned off well before VIN drops below the VOUT voltage. V VOUT(MIN) RDS(ON)MAX AUX(MIN) 1.5 IOUT(MAX) VAUX(MIN) is the minimum value of the auxiliary supply voltage, VOUT(MIN) is the minimum allowable output voltage, IOUT(MAX) is the maximum output current and 1.5 is a “fudge factor” to account for increases in RDS(ON) due to temperature. Calculating Power Dissipation and Heatsink Requirements Most linear regulators operate under conditions that result in high on–chip power dissipation. This results in high junction temperatures. Since the IC has a thermal shutdown feature, ensuring the regulator will operate correctly under normal conditions is an important design consideration. Some heatsinking will usually be required. Output Voltage Sensing It is not possible to remotely sense the output voltage of the C5233–3 since the feedback path to the error amplifier is not externally available. It is important to minimize voltage drops due to metal resistance of high current PC http://onsemi.com 8 CS5233–3 Thermal characteristics of an IC depend on four parameters: ambient temperature (TA in °C), power dissipation (PD in watts), thermal resistance from the die to the ambient air (θJA in °C per watt) and junction temperature (TJ in °C). The maximum junction temperature is calculated from the formula below: considered zero, since heat is conducted out of the package by the IC leads and the tab of the D2PAK package, and since the IC leads and tab are soldered directly to the PC board. Modification of θSA is the primary means of thermal management. For surface mount components, this means modifying the amount of trace metal that connects to the IC. The thermal capacity of PC board traces is dependent on how much copper area is used, if the IC is in direct contact with the metal, whether the metal surface is coated with some type of sealant, and whether there is airflow across the PC board. The chart provided below shows heatsinking capability of a square, single sided copper PC board trace. The area is given in square millimeters, and it is assumed there is no airflow across the PC board. TJ(MAX) TA(MAX) JA PD(MAX) Maximum ambient temperature and power dissipation are determined by the design, while θJA is dependent on the package manufacturer. The maximum junction temperature for operation of the CS5233–3 within specification is 150°C. The maximum power dissipation of a linear regulator is given as PD(MAX) (VIN(MAX) VOUT(MIN)) ILOAD(MAX) VIN(MAX) IGND(MAX) 70 60 Thermal Resistance, °CW where IGND(MAX) is the IC bias current. It is possible to change the effective value of θJA by adding a heatsink to the design. A heatsink serves in some manner to raise the effective area of the package, thus improving the flow of heat from the package into the surrounding air. Each material in the path of heat flow has its own characteristic thermal resistance, all measured in °C per watt. The thermal resistances are summed to determine the total thermal resistance between the die junction and air. There are three components of interest: junction–to–case thermal resistance (θJC), case–to–heatsink thermal resistance (θCS) and heatsink–to–air thermal resistance (θSA). The resulting equation for junction–to–air thermal resistance is 50 40 30 20 10 0 JA JC CS SA, or JA JC SA for CS 0 0 2000 4000 PC Board Trace Area (mm2) Figure 12. Thermal Resistance Capability of Copper PC Board Metal Traces The value of θJC for the CS5233–3 is provided in the Packaging Information section of this data sheet. θCS can be http://onsemi.com 9 6000 CS5233–3 PACKAGE DIMENSIONS D2PAK 5–PIN DP SUFFIX CASE 936F–01 ISSUE O –T– SEATING PLANE B C M E DIM A B C D E F G H J K M N A 1 2 3 4 5 K F G D H 5 PL 0.13 (0.005) M T B J M NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS B AND M. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAX. INCHES MIN MAX 0.326 0.336 0.396 0.406 0.170 0.180 0.026 0.035 0.045 0.055 0.090 0.110 0.067 BSC 0.098 0.108 0.018 0.025 0.204 0.214 0.055 0.066 0.000 0.004 MILLIMETERS MIN MAX 8.28 8.53 10.05 10.31 4.31 4.57 0.66 0.91 1.14 1.40 2.29 2.79 1.70 BSC 2.49 2.74 0.46 0.64 5.18 5.44 1.40 1.68 0.00 0.10 N SO–8 DF SUFFIX CASE 751–06 ISSUE T D A 8 E 5 0.25 H 1 M B M 4 h B e X 45 A C SEATING PLANE L 0.10 A1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C B 0.25 M C B S A S http://onsemi.com 10 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 CS5233–3 PACKAGE THERMAL DATA Parameter 5 Lead D2PAK 8 Lead SOIC Unit RΘJC Typical 1.0–4.0 25 °C/W RΘJA Typical 10–50* 110 °C/W *Depending on thermal properties of substrate. RθJA = RθJC + RθCA. http://onsemi.com 11 CS5233–3 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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