NSC 93L34

93L34
8-Bit Addressable Latch
General Description
Features
The 93L34 is an 8-bit addressable latch designed for general purpose storage applications in digital systems. It is a
multifunctional device capable of storing single line data in
eight addressable latches, and being a one-of-eight decoder
and demultiplexer with active level HIGH outputs. The device also incorporates an active LOW common clear for resetting all latches, as well as, an active LOW enable.
Y
Connection Diagram
Logic Symbol
Y
Y
Y
Y
Y
Serial to parallel capability
Eight bits of storage with output of each bit available
Random (addressable) data entry
Active high demultiplexing or decoding capability
Easily expandable
Common conditional clear
Dual-In-Line Package
TL/F/10201 – 2
VCC e Pin 16
GND e Pin 8
TL/F/10201 – 1
Order Number 93L34DMQB or 93L34FMQB
See NS Package Number J16A or W16A
Pin Names
A0–A3
D
E
CL
Q0–Q7
C1995 National Semiconductor Corporation
TL/F/10201
Description
Address Inputs
Data Input
Enable Input (Active LOW)
Clear Input (Active LOW)
Parallel Latch Outputs
RRD-B30M105/Printed in U. S. A.
93L34 8-Bit Addressable Latch
June 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
Military
b 65§ C to a 150§ C
Storage Temperature Range
Recommended Operating Conditions
Symbol
93L34 (Mil)
Parameter
Units
Min
Nom
Max
4.5
5
5.5
VCC
Supply Voltage
VIH
High Level Input Voltage
V
VIL
Low Level Input Voltage
IOH
High Level Output Voltage
IOL
Low Level Output Current
TA
Free Air Operating Temperature
ts (H)
Setup Time HIGH, D to E
45
th (H)
Hold Time HIGH, D to E
b5
ns
ts (L)
Setup Time LOW, D to E
45
ns
th (L)
Hold Time LOW, D to E
b7
ns
ts (H)
ts (L)
Setup Time HIGH or LOW
An to E
10
10
ns
tw (L)
E Pulse Width LOW
26
ns
tw (L)
CL Pulse Width LOW
35
ns
2
V
b 55
0.7
V
b 400
mA
4.8
mA
125
§C
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC e Min, II e b10 mA
VOH
High Level Output Voltage
VCC e Min, IOH e Max,
VIL e Max, VIH e Min
VOL
Low Level Output Voltage
VCC e Min, IOL e Max,
VIH e Min, VIL e Max
II
Input Current @ Max
Input Voltage
VCC e Max, VI e 5.5V
IIH
High Level Input Current
VCC e Max, VI e 2.4V
IIL
Low Level Input Current
VCC e Max, VI e 0.3V
IOS
Short Circuit
Output Current
VCC e Max (Note 2)
ICC
Supply Current
VCC e Max (Note 3)
Min
2
Max
Units
b 1.5
V
2.4
V
0.3
V
1
mA
Inputs
20
E
30
Inputs
b 0.4
E
b 0.6
b 2.5
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open and all inputs grounded.
Typ
(Note 1)
mA
mA
b 25
mA
21
mA
Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for Test Waveforms and Output Load)
Symbol
CL e 15 pF
Parameter
Min
Units
Max
tPLH
tPHL
Propagation Delay
E to Qn
45
42
ns
tPLH
tPHL
Propagation Delay
D to Qn
65
45
ns
tPLH
tPHL
Propagation Delay
An to Qn
66
66
ns
tPHL
Propagation Delay
CL to Qn
55
ns
Functional Description
The 93L34 has four modes of operation which are shown in
the Mode Select Table. In the addressable latch mode, data
on the data line (D) is written into the addressed latch. The
addressed latch will follow the Data input with all non-addressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous state and
are unaffected by the data or address inputs. To eliminate
the possibility of entering erroneous data into the latches,
the Enable should be held HIGH while the Address lines are
changing. In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the state of the D input with
all other outputs in the LOW state. In the clear mode all
outputs are LOW and unaffected by the address and data
inputs. When operating the 93L34 as an addressable latch,
changing more than one bit of the address could impose a
transient wrong address. Therefore, this should only be
done while in the memory mode.
Mode Select Table
3
E
CL
Mode
L
H
L
H
H
H
L
L
Addressable Latch
Memory
Active HIGH 8-Channel Demultiplexer
Clear
Truth Table
Inputs
Outputs
Mode
CL
E
A0
A1
A2
L
L
L
L
H
L
L
L
X
L
H
L
X
L
L
H
#
#
#
#
#
#
#
#
L
L
H
H
H
L
L
L
L
L
L
L
L
H
H
X
X
X
Qt–1
Qt–1
Qt–1
Qt – 1
Qt – 1
Qt – 1
Qt – 1
Qt – 1
Memory
H
H
H
L
L
L
L
H
L
L
L
H
L
L
L
D
Qt–1
Qt – 1
Qt–1
D
Qt – 1
Qt– 1
Qt–1
D
Qt – 1
Qt – 1
Qt –1
Qt – 1
Qt – 1
Qt –1
Qt – 1
Qt – 1
Qt –1
Qt – 1
Qt – 1
Qt –1
Qt – 1
Qt – 1
Qt –1
Addressable
Latch
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
H
L
H
H
H
Qt – 1
Qt – 1
Qt – 1
Qt –1
Qt –1
Qt –1
Qt –1
D
H e HIGH Voltage Level
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
X
L
L
L
L
D
L
L
L
L
D
L
L
L
L
D
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
L e LOW Voltage Level
X e Immaterial
4
Qt–1 e Previous Output State
Clear
Demultiplex
Logic Diagram
TL/F/10201 – 3
5
6
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L34DMQB
NS Package Number J16A
7
93L34 8-Bit Addressable Latch
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 93L34FMQB
NS Package Number W16A
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This datasheet has been download from:
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Datasheets for electronics components.