AD AD7691BRMZ

18-Bit, 1.5 LSB INL, 250 kSPS PulSAR®
Differential ADC in MSOP/QFN
AD7691
FEATURES
APPLICATION DIAGRAM
+2.3V TO VDD
+2.3V TO +5V
IN+
REF VDD VIO
SDI
IN–
SDO
+1.8V TO VDD
3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)
SCK
±10V, ±5V, ...
GND
ADA4941
CNV
06146-001
18-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.75 LSB typ, ±1.5 LSB max (±6 ppm of FSR)
Dynamic range: 102 dB typ @ 250 kSPS
Oversampled dynamic range: 125 dB @1 kSPS
Noise-free code resolution: 20 bits @ 1 kSPS
Effective resolution: 22.7 bits @ 1 kSPS
SINAD: 101.5 dB typ @ 1 kHz
THD: −125 dB typ @ 1 kHz
True differential analog input range: ±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 2.3 V to 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation
5 mW @ 5 V/250 kSPS
50 μW @ 5 V/1 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN 1 (LFCSP) (SOT-23 size)
Pin-for-pin compatible with the18-bit AD7690 and 16-bit
AD7693, AD7688, and AD7687
AD7691
Figure 2.
1
Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
Type
18-Bit
16-Bit True
Differential
16-Bit Pseudo
Differential/
Unipolar
14-Bit
1
100
kSPS
250
kSPS
AD7691
AD7684
AD7687
AD7683
AD7680
AD7685
AD7694
AD7940
AD7942
400 kSPS
to
500 kSPS
AD7690
AD7688
AD7693
AD7686
ADC
Driver
ADA4941-1
ADA4841-x
ADA4941-1
ADA4841-x
ADA4841-x
AD7946
ADA4841-x
QFN package in development. Contact sales for samples and availability.
GENERAL DESCRIPTION
APPLICATIONS
The AD7691 is an 18-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V and 5 V. It
contains a low power, high speed, 18-bit sampling ADC with no
missing codes, an internal conversion clock, and a versatile
serial interface port. On the CNV rising edge, it samples the
voltage difference between the IN+ and IN− pins. The voltages
on these pins usually swing in opposite phase between 0 V and
REF. The reference voltage, REF, is applied externally and can
be set up to the supply voltage.
Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments
1.5
POSITIVE INL = 0.43LSB
NEGATIVE INL = –0.62LSB
1.0
INL (LSB)
0.5
Its power scales linearly with throughput.
0
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
–0.5
–1.5
0
65536
131072
196608
CODE
262144
06146-025
–1.0
The AD7691 is housed in a 10-lead MSOP or a 10-lead QFN1
(LFCSP) with operation specified from −40°C to +85°C.
Figure 1. Integral Nonlinearity vs. Code, 5 V
1
QFN package in development. Contact sales for samples and availability.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD7691
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Operation.................................................................. 13
Applications....................................................................................... 1
Typical Connection Diagram ................................................... 14
Application Diagram........................................................................ 1
Analog Inputs ............................................................................. 15
General Description ......................................................................... 1
Driver Amplifier Choice ........................................................... 15
Revision History ............................................................................... 2
Single-to-Differential Driver .................................................... 16
Specifications..................................................................................... 3
Voltage Reference Input ............................................................ 16
Timing Specifications....................................................................... 5
Power Supply............................................................................... 16
Absolute Maximum Ratings............................................................ 7
Supplying the ADC from the Reference.................................. 17
ESD Caution.................................................................................. 7
Digital Interface.......................................................................... 17
Pin Configurations and Function Descriptions ........................... 8
Application Hints ........................................................................... 24
Terminology ...................................................................................... 9
Layout .......................................................................................... 24
Typical Performance Characteristics ........................................... 10
Evaluating the AD7691’s Performance.................................... 24
Theory of Operation ...................................................................... 13
Outline Dimensions ....................................................................... 25
Circuit Information.................................................................... 13
Ordering Guide .......................................................................... 25
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7691
SPECIFICATIONS
VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range, VIN
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance 1
THROUGHPUT
Conversion Rate
Transient Response
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error 3
Gain Error Temperature Drift
Zero Error3
Zero Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range 5
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Conditions/Comments
Min
18
IN+ − (IN−)
IN+, IN−
IN+, IN−
fIN = 250 kHz
Acquisition phase
−VREF
−0.1
0
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
Full-scale step
0
0
18
−1.5
−1
REF = VDD = 5 V
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
−45
−80
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
−0.8
−3.5
VDD = 5 V ± 5%
VREF = 5 V
fIN = 1 kSPS
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
101
100
95
100
95
Intermodulation Distortion 6
1
Typ
VREF/2
65
1
±0.75
±0.5
0.75
±2
±2
±0.5
±0.1
±0.7
±1
±0.25
102
125
101.5
96.5
−125
−118
101.5
96.5
115
Max
Unit
Bits
+VREF
VREF + 0.1
VREF/2 + 0.1
V
V
V
dB
nA
250
180
1.8
kSPS
kSPS
μs
+1.5
+1.25
+45
+80
+0.8
+3.5
Bits
LSB
LSB 2
LSB
LSB
LSB
ppm/°C
mV
mV
ppm/°C
LSB
dB 4
dB
dB
dB
dB
dB
dB
dB
dB
See the Analog Inputs section.
LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 μV.
3
See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5
Dynamic range obtained by oversampling the ADC running at a throughput fS of 250 kSPS, followed by postdigital filtering with an output word rate fO.
6
fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale.
2
Rev. 0 | Page 3 of 28
AD7691
VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay 1
VOL
VOH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current 2, 3
Power Dissipation
Energy per Conversion
TEMPERATURE RANGE 4
Specified Performance
Conditions/Comments
Min
Typ
0.5
Max
Unit
VDD + 0.3
250 kSPS, REF = 5 V
60
V
μA
VDD = 5 V
2
2.5
MHz
ns
−0.3
0.7 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+1
+1
V
V
μA
μA
0.4
V
V
5.25
VDD + 0.3
VDD + 0.3
50
V
V
V
nA
μW
mW
mW
nJ/sample
+85
°C
Serial 18-bit, twos
complement.
ISINK = +500 μA
ISOURCE = −500 μA
VIO − 0.3
Specified performance
Specified performance
2.3
2.3
1.8
VDD and VIO = 5 V, 25°C
100 SPS throughput
100 kSPS throughput
250 kSPS throughput
TMIN to TMAX
1
5
4
5
50
−40
1
Conversion results are available immediately after completed conversion.
With all digital inputs forced to VIO or GND as required.
3
During acquisition phase.
4
Contact an Analog Devices, Inc., sales representative for extended temperature range.
2
Rev. 0 | Page 4 of 28
AD7691
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
1
See Figure 3 and Figure 4 for load conditions.
Rev. 0 | Page 5 of 28
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
1.8
4
10
15
Typ
Max
2.2
17
18
19
20
7
7
4
Unit
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
16
17
ns
ns
ns
ns
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
26
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
10
3
4
AD7691
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 5. 1
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1
See Figure 3 and Figure 4 for load conditions.
Rev. 0 | Page 6 of 28
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
1.8
5.5
10
25
Typ
Max
3.7
29
35
40
12
12
5
Unit
μs
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
24
30
35
ns
ns
ns
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
30
0
5
8
8
10
36
AD7691
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Analog Inputs
IN+, 1 IN−1
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
(10-Lead MSOP)
θJC Thermal Impedance
(10-Lead MSOP)
Lead Temperature Range
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
GND − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
200°C/W
44°C/W
JEDEC J-STD-20
See the Analog Inputs section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µA
IOL
1.4V
TO SDO
500µA
05792-002
CL
50pF
IOH
Figure 3. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
2V OR VIO – 0.5V1
2V OR VIO – 0.5V1
0.8V OR 0.5V2
0.8V OR 0.5V2
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO
VIO BELOW 2.5V.
BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Rev. 0 | Page 7 of 28
05792-003
tDELAY
AD7691
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
VDD 2
IN+ 3
IN– 4
10
VIO
AD7691
9
SDI
TOP VIEW
(Not to Scale)
8
SCK
7
SDO
6
CNV
GND 5
IN– 4
GND 5
06146-004
REF 1
IN+ 3
10 VIO
AD7691
TOP VIEW
(Not to Scale)
9
SDI
8
SCK
7
SDO
6
CNV
NOTES
1. QFN PACKAGE IN DEVELOPMENT. CONTACT
SALES FOR SAMPLES AND AVAILABILITY.
06146-005
VDD 2
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Figure 5. 10-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
AI
AI
P
DI
7
8
SDO
SCK
DO
DI
9
SDI
DI
10
VIO
P
Description
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This
pin should be decoupled closely to the pin with a 10 μF capacitor.
Power Supply.
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions
and selects the interface mode of the part, either chain or CS mode. In CS mode, it enables the
SDO pin when low. In chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this
clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC
as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.
The digital data level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV
can enable the serial output signals when low, and if SDI or CNV is low when the conversion is
complete, the busy indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
1
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. 0 | Page 8 of 28
AD7691
TERMINOLOGY
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is
LSB(V) =
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
V INpp
2
Noise-Free Code Resolution
It is the number of bits beyond which it is impossible to resolve
individual codes distinctly. It is calculated as
N
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 26).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999943 V for the ±5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
Effective Resolution
It is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to acquire its
input accurately after a full-scale step function is applied.
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Rev. 0 | Page 9 of 28
AD7691
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.5
POSITIVE DNL = 0.37LSB
NEGATIVE DNL = –0.33LSB
POSITIVE INL = 0.39LSB
NEGATIVE INL = –0.73LSB
1.0
0.5
DNL (LSB)
INL (LSB)
0.5
0
0
–0.5
–0.5
0
65536
131072
262144
196608
–1.0
06146-026
CODE
70k
45k
40k
COUNTS
28527
27770
28179
24411
25k
20k
17460
14362
15k
20k
10k
10k
0
26
25
26
27
5k
2904
28
2062
29
2A
2B
2C
14
0
0
2D
2E
2F
CODE IN HEX
0
06146-027
0
–60
9
0
23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31
0
32768 POINT FFT
VDD = REF = 2.5V
fS = 180kSPS
fIN = 2kHz
SNR = 96.4dB
THD = –120.3dB
2ND HARMONIC = –132.5dB
3RD HARMONIC = –121.2dB
–20
AMPLITUDE (dB of Full Scale)
–40
910 78
29 501
Figure 11. Histogram of a DC Input at the Code Center, 2.5 V
32768 POINT FFT
VDD = REF = 5V
fS = 250kSPS
fIN = 2kHz
SNR = 101.4dB
THD = –120.1dB
2ND HARMONIC = –140.7dB
3RD HARMONIC = –120.3dB
–20
12
CODE IN HEX
Figure 8. Histogram of a DC Input at the Code Center, 5 V
0
4055
2997
0
06146-030
COUNTS
40k
30k
–80
–100
–120
–140
–160
–40
–60
–80
–100
–120
–140
–160
0
20
40
60
80
FREQUENCY (kHz)
100
120
06146-028
AMPLITUDE (dB of Full Scale)
VDD = REF = 2.5V
σ = 1.42LSB
38068
30k
50k
–180
262144
35k
60k
0
196608
Figure 10. Differential Nonlinearity vs. Code, 5 V
VDD = REF = 5V
σ = 0.76LSB
69769
131072
CODE
Figure 7. Integral Nonlinearity vs. Code 2.5 V
80k
65536
0
Figure 9. 2 kHz FFT Plot, 5 V
–180
0
10
20
30
40
50
60
FREQUENCY (kHz)
Figure 12. 2 kHz FFT Plot, 2.5 V
Rev. 0 | Page 10 of 28
70
80
90
06146-031
–1.5
06146-029
–1.0
AD7691
104
18
SNR
–105
102
–110
17
SINAD
16
94
ENOB (Bits)
ENOB
96
THD, SFDR (dB)
98
92
–115
THD
–120
–125
15
90
–130
88
2.9
3.2
3.5
3.8
4.1
4.4
4.7
5.0
14
5.3
–135
2.3
06146-032
2.6
REFERENCE VOLTAGE (V)
2.6
2.9
3.2
3.5
3.8
4.1
4.4
4.7
5.0
5.3
105
125
REFERENCE VOLTAGE (V)
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
06146-038
SFDR
86
2.3
Figure 16. THD, SFDR vs. Reference Voltage
105
–90
VREF = 5V
100
–100
95
THD (dB)
SNR (dB)
VREF = 2.5V
90
–110
VREF = 5V
–120
85
5
25
45
65
85
105
125
TEMPERATURE (°C)
–130
–55
–15
5
25
45
65
Figure 17. THD vs. Temperature
–60
VREF = 5V, –10dB
VREF = 5V, –1dB
100
–70
95
–80
90
–90
VREF = 5V, –1dB
THD (dB)
VREF = 2.5V, –1dB
VREF = 2.5V, –1dB
VREF = 2.5V, –10dB
85
–100
–110
75
–120
0
25
50
75
FREQUENCY (kHz)
100
125
06146-037
80
70
85
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
105
–35
Figure 15. SINAD vs. Frequency
–130
VREF = 2.5V, –10dB
VREF = 5V, –10dB
0
25
50
75
FREQUENCY (kHz)
Figure 18. THD vs. Frequency
Rev. 0 | Page 11 of 28
100
125
06146-040
–15
06146-033
–35
06146-039
VREF = 2.5V
80
–55
SINAD (dB)
SNR, SINAD (dB)
100
AD7691
–90
GAIN ERROR
–95
SNR 2.5V
99
4
OFFSET, GAIN ERROR (LSB)
102
–100
–110
93
THD 5V
90
–115
87
–120
THD 2.5V
81
–10
–8
–6
–4
–2
0
2
0
–2
–4
–125
OFFSET ERROR
–130
–6
–55
06146-041
84
THD (dB)
–105
96
SNR (dB)
6
INPUT LEVEL (dB)
POWER-DOWN CURRENT (nA)
OPERATING CURRENT (µA)
VDD = 2.5V
500
250
85
105
125
250
VDD + VIO
5
25
45
65
TEMPERATURE (°C)
85
105
125
Figure 20. Operating Current vs. Temperature
1000
65
500
0
–55
06146-042
–15
45
750
VIO
–35
25
1000
750
0
–55
5
Figure 22. Offset and Gain Error vs. Temperature
fS =100kSPS
VDD = 5V
–15
TEMPERATURE (°C)
Figure 19. SNR, THD vs. Input Level
1000
–35
06146-044
SNR 5V
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
06146-047
105
Figure 23. Power-Down Current vs. Temperature
25
fS =100kSPS
tDSDO DELAY (ns)
500
250
15
VDD = 5V, 85°C
10
VDD = 5V, 25°C
5
2.6
2.9
3.2
3.5
3.8
4.1
SUPPLY (V)
4.4
4.7
5.0
5.3
0
0
20
40
60
80
SDO CAPACITIVE LOAD (pF)
100
Figure 24. tDSDO Delay vs. Capacitance Load and Supply
Figure 21. Operating Current vs. Supply
Rev. 0 | Page 12 of 28
120
06146-034
VIO
0
2.3
06146-043
OPERATING CURRENT (µA)
20
VDD
750
AD7691
THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB
REF
131,072C 65,536C
LSB
4C
2C
C
SW+
C
BUSY
COMP
GND
131,072C 65,536C
4C
2C
C
CONTROL
LOGIC
OUTPUT CODE
C
MSB
LSB
SW–
05792-006
CNV
IN–
Figure 25. ADC Simplified Schematic
CIRCUIT INFORMATION
CONVERTER OPERATION
The AD7691 is a fast, low power, single-supply, precise, 18-bit
ADC using a successive approximation architecture.
The AD7691 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary-weighted capacitors, which are
connected to the two comparator inputs.
The AD7691 is capable of converting 250,000 samples per
second (250 kSPS) and powers down between conversions.
When operating at 1 kSPS, for example, it consumes 50 μW
typically, which is ideal for battery-powered applications.
The AD7691 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.
The AD7691 is specified from 2.3 V to 5.25 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead QFN 1 (LFCSP) that combines
space savings and allows flexible configurations.
It is pin-for-pin compatible with the 18-bit AD7690 as well as
the 16-bit AD7687 and AD7688.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/262,144).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.
Because the AD7691 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
1
QFN package in development. Contact sales for samples and availability.
Rev. 0 | Page 13 of 28
AD7691
TYPICAL CONNECTION DIAGRAM
The ideal transfer characteristic for the AD7691 is shown in
Figure 26 and Table 8.
Figure 27 shows an example of the recommended connection
diagram for the AD7691 when multiple supplies are available.
ADC CODE (TWOS COMPLEMENT)
Transfer Functions
011...111
011...110
011...101
100...010
100...000
–FSR
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
ANALOG INPUT
05792-007
100...001
Figure 26. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
2
Digital Output
Code (Hex)
0x2FFFF1
0x00001
0x00000
0x3FFFF
0x20001
0x200002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
V+
REF1
5V
10µF 2
100nF
V+
1.8V TO VDD
100nF
15Ω
REF
0 TO VREF
ADA4841-2 3
V–
V+
2.7nF
VDD
IN+
AD7691
4
IN–
15Ω
GND
VIO
SDI
SCK
SDO
3- OR 4-WIRE INTERFACE5
CNV
VREF TO 0
ADA4841-2 3
V–
2.7nF
4
1 SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3 SEE TABLE 9 FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5 SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
Figure 27. Typical Application Diagram with Multiple Supplies
Rev. 0 | Page 14 of 28
06146-008
1
Analog Input
VREF = 5 V
+4.999962 V
+38.15 μV
0V
−38.15 μV
−4.999962 V
−5 V
AD7691
ANALOG INPUTS
Figure 28 shows an equivalent circuit of the input structure of
the AD7691.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur if the input buffer’s
(U1’s) supplies are different than VDD. In such a case—for
example, an input buffer with a short circuit—the current
limitation can be used to protect the part.
When the source impedance of the driving circuit is low, the
AD7691 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7691 is easy to drive, the driver amplifier must
meet the following requirements:
•
VDD
D1
IN+
OR IN–
CIN
D2
05792-009
CPIN
RIN
GND
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7691. The noise coming from
the driver is filtered by the AD7691 analog input circuit’s
1-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. The SNR degradation due to
the amplifier is as follows:
Figure 28. Equivalent Analog Input Circuit
SNRLOSS
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
90
VNADC is the noise of the ADC, in μV, given by the following:
V INpp
80
V NADC =
CMRR (dB)
75
2 2
10
70
SNR
20
f−3 dB is the input bandwidth, in MHz, of the AD7691
(2 MHz) or the cutoff frequency of the input filter, if one is
used.
65
60
55
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
50
45
1
10
100
1000
FREQUENCY (kHz)
10000
eN+ and eN− are the equivalent input noise voltage densities
of the op amps connected to IN+ and IN−, in nV/√Hz.
This approximation can be used when the resistances
around the amplifier are small. If larger resistances are
used, their noise contributions should also be root-sumsquared.
06146-036
40
⎞
⎟
⎟
⎟
⎟
⎠
where:
VREF = VDD = 5V
85
⎛
⎜
VNADC
= 20 log ⎜
⎜
π
π
2
2
⎜ VNADC 2 + f −3 dB (NeN + ) + f −3 dB (NeN − )
2
2
⎝
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination
of the capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 3 kΩ and is a lumped component made up of
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
•
For ac applications, the driver should have a THD
performance commensurate with the AD7691.
•
For multichannel multiplexed applications, the driver
amplifier and the AD7691 analog input circuit must settle
for a full-scale step onto the capacitor array at an 18-bit
level (0.0004%, 4 ppm). In the amplifier’s data sheet,
settling at 0.1% to 0.01% is more commonly specified. This
could differ significantly from the settling time at an 18-bit
level and should be verified prior to driver selection.
During the conversion phase, where the switches are opened, the
input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter that reduces undesirable aliasing effects and
limits the noise.
Rev. 0 | Page 15 of 28
AD7691
Table 9. Recommended Driver Amplifiers
Amplifier
ADA4941-1
ADA4841-x
AD8655
AD8021
AD8022
OP184
AD8605, AD8615
VOLTAGE REFERENCE INPUT
Typical Application
Very low noise, low power single-ended-todifferential driver
Very low noise, small, and low power
5 V single supply, low noise
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single supply, low power
The AD7691 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended-to-differential
driver allows for a differential input into the part. The schematic
is shown in Figure 30.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF). R1, R2, and CF are chosen depending on
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.
R3 and R4 set the common mode on the IN− input, and R5 and
R6 set the common mode on the IN+ input of the ADC. The
common mode should be set close to VREF/2; however, if single
supply is desired, it can be set slightly above VREF/2 to provide
some headroom for the ADA4941-1 output stage. For example,
for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 =
11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ.
R5
R6
R3
R4
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values—down
to 2.2 μF—can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
POWER SUPPLY
The AD7691 uses two power supply pins: a core supply, VDD,
and a digital input/output interface supply, VIO. VIO allows
direct interface with any logic between 1.8 V and VDD. To
reduce the supplies needed, the VIO and VDD pins can be tied
together. The AD7691 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown
in Figure 31.
+5V REF
95
10µF
+5.2V
+5.2V
90
100nF
2.7nF
2.7nF
100nF
15Ω
IN+
REF
VDD
85
AD7691
IN–
PSRR (dB)
15Ω
GND
ADA4941
80
75
R2
CF
70
Figure 30. Single-Ended-to-Differential Driver Circuit
65
1
10
100
1000
FREQUENCY (kHz)
Figure 31. PSRR vs. Frequency
Rev. 0 | Page 16 of 28
10000
06146-035
R1
06146-010
±10V, ±5V, ...
AD7691
The AD7691 powers down automatically at the end of each
conversion phase, and therefore the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (as low as a few hertz) and low battery-powered applications.
10
VIO
0.1
1k
10k
1M
100k
SAMPLING RATE (SPS)
06146-045
OPERATING CURRENT (µA)
VDD = 5V
100
Figure 32. Operating Current vs. Sample Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7691, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 33. The reference line can be driven by
•
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 33.
5V
1µF
In either mode, the AD7691 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
The busy indicator feature is enabled
•
10kΩ
AD8031
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
•
5V
10Ω
5V
When in chain mode, the AD7691 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
10µF
1µF
1
REF
VDD
VIO
AD7691
1OPTIONAL
REFERENCE BUFFER AND FILTER.
06146-046
•
•
Though the AD7691 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7691 is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. In this mode, the AD7691 can use either a 3-wire
or 4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections and is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
the conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.
1000
0.001
10
DIGITAL INTERFACE
Figure 33. Example of an Application Circuit
Rev. 0 | Page 17 of 28
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 37 and Figure 41).
In the chain mode if SCK is high during the CNV rising
edge (see Figure 45).
AD7691
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge can allow a faster
reading rate, provided it has an acceptable hold time. After the
18th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
3-Wire CS Mode Without Busy Indicator
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34, and the corresponding timing is given in
Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers, but CNV must be returned
high before the minimum conversion time elapses and then
held high for the maximum possible conversion time to avoid
the generation of the busy signal indicator. When the
conversion is complete, the AD7691 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7691
DATA IN
SDO
06146-011
SCK
CLK
Figure 34. 3-Wire CS Mode Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
16
tHSDO
18
tSCKH
tDSDO
tEN
SDO
17
D17
D16
D15
tDIS
D1
D0
Figure 35. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
Rev. 0 | Page 18 of 28
05792-012
SCK
AD7691
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge,
or when CNV goes high, whichever is earlier, SDO returns to
high impedance.
3-Wire CS Mode with Busy Indicator
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
If multiple AD7691s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7691 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
CONVERT
VIO
DIGITAL HOST
CNV
VIO
47kΩ
AD7691
DATA IN
SDO
SCK
IRQ
06146-013
SDI
CLK
Figure 36. 3-Wire CS Mode with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
17
tHSDO
18
19
tSCKH
tDSDO
SDO
D17
D16
tDIS
D1
D0
Figure 37. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
Rev. 0 | Page 19 of 28
05792-014
SCK
AD7691
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7691 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
18th SCK falling edge, or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7691
can be read.
4-Wire CS Mode Without Busy Indicator
This mode is usually used when multiple AD7691s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7691s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
CNV
SDI
AD7691
DIGITAL HOST
CNV
SDO
SDI
AD7691
SCK
SDO
SCK
06146-015
DATA IN
CLK
Figure 38. 4-Wire CS Mode Without Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI (CS1)
tHSDICNV
SDI (CS2)
tSCK
tSCKL
1
2
16
3
tHSDO
18
19
20
34
35
36
tDSDO
tEN
SDO
17
tSCKH
D17
D16
D15
tDIS
D1
D0
D17
D16
Figure 39. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing
Rev. 0 | Page 20 of 28
D1
D0
06146-016
SCK
AD7691
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7691
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge,
or SDI going high, whichever is earlier, SDO returns to high
impedance.
4-Wire CS Mode with Busy Indicator
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
CS1
CONVERT
VIO
DIGITAL HOST
CNV
AD7691
DATA IN
SDO
SCK
IRQ
06146-017
SDI
47kΩ
CLK
Figure 40. 4-Wire CS Mode with Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
1
2
3
tHSDO
17
18
19
tSCKH
tDSDO
tDIS
tEN
SDO
D17
D16
D1
Figure 41. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
Rev. 0 | Page 21 of 28
D0
05792-018
SCK
AD7691
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7691 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge can allow a faster reading
rate and consequently more AD7691s in the chain, provided the
digital host has an acceptable hold time. The maximum
conversion rate can be reduced due to the total readback time.
Chain Mode Without Busy Indicator
This mode can be used to daisy-chain multiple AD7691s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7691s is shown in
Figure 42, and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
CONVERT
CNV
AD7691
A
SDO
SDI
DIGITAL HOST
SDO
B
SCK
DATA IN
SCK
06146-019
SDI
CNV
AD7691
CLK
Figure 42. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
tHSCKCNV
2
3
16
17
tSSDISCK
18
19
20
DA17
DA16
34
35
36
DA1
DA0
tSCKH
tHSDISC
tEN
SDOA = SDIB
DA17
DA16
DA15
DA1
DA0
DB17
DB16
DB15
DB1
DB0
SDOB
Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. 0 | Page 22 of 28
05792-020
tHSDO
tDSDO
AD7691
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7691 ADC labeled C in Figure 44) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7691 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and consequently more AD7691s in the
chain, provided the digital host has an acceptable hold time.
Chain Mode with Busy Indicator
This mode can also be used to daisy-chain multiple AD7691s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using three AD7691s is shown
in Figure 44, and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
CONVERT
SDI
AD7691
A
CNV
SDO
SDI
SCK
DIGITAL HOST
CNV
AD7691
B
SDO
SDI
AD7691
SCK
C
DATA IN
SDO
SCK
IRQ
06146-021
CNV
CLK
Figure 44. Chain Mode with Busy Indicator Connection Diagram
tCYC
ACQUISITION
tCONV
tACQ
ACQUISITION
CONVERSION
tSSCKCNV
SCK
tHSCKCNV
tSCKH
1
tEN
SDOA = SDIB
SDOB = SDIC
2
tSSDISCK
3
4
17
18
19
20
21
35
36
37
38
39
tSCKL
tHSDISC
DA17 DA16 DA15
tDSDOSDI
tSCK
DA1
54
55
tDSDOSDI
DA0
tHSDO
tDSDO
tDSDOSDI
DB17 DB16 DB15
DB1
DB0 DA17 DA16
DA1
DA0
DC17 DC16 DC15
DC1
DC0 DB17 DB16
DB1
DB0 DA17 DA16
tDSDOSDI
SDOC
53
tDSDOSDI
Figure 45. Chain Mode with Busy Indicator Serial Interface Timing
Rev. 0 | Page 23 of 28
DA1
DA0
05792-022
CNV = SDIA
AD7691
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7691 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7691, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7691.
06146-023
Avoid running digital lines under the device because this couples
noise onto the die unless a ground plane under the AD7691 is
used as a shield. Fast switching signals, such as CNV or clocks,
should not run near analog signal paths. Crossover of digital
and analog signals should be avoided.
Figure 46. Example Layout of the AD7691 (Top Layer)
The AD7691 voltage reference input, REF, has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies, VDD and VIO, of the AD7691
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7691 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
05792-024
An example of a layout following these rules is shown in
Figure 46 and Figure 47.
EVALUATING THE AD7691’S PERFORMANCE
Figure 47. Example Layout of the AD7691 (Bottom Layer)
Other recommended layouts for the AD7691 are outlined
in the documentation of the evaluation board for the AD7691
(EVAL-AD7691-CB). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
Rev. 0 | Page 24 of 28
AD7691
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
6
5
5.15
4.90
4.65
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.05
0.33
0.17
SEATING
PLANE
0.80
0.60
0.40
8°
0°
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
INDEX
ARE A
PIN 1
INDICATOR
3.00
BSC SQ
10
1.50
BCS SQ
0.50
BSC
1
(BOT TOM VIEW)
6
0.80
0.75
0.70
0.80 MAX
0.55 TYP
SIDE VIEW
SEATING
PLANE
0.30
0.23
0.18
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
0.50
0.40
0.30
5
1.74
1.64
1.49
0.05 MAX
0.02 NOM
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES
0.20 REF
Figure 49. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
QFN package in development. Contact sales for samples and availability.
ORDERING GUIDE
Model
AD7691BRMZ 1
AD7691BRMZ-RL71
EVAL-AD7691CB 2
EVAL-CONTROL BRD2 3
EVAL-CONTROL BRD33
Temperature Range
–40°C to +85°C
–40°C to +85°C
Ordering Quantity
Tube, 50
Reel, 1,000
Package Description
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Controller Board
Controller Board
1
Package Option
RM-10
RM-10
Z = Pb-free part.
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
3
These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
2
Rev. 0 | Page 25 of 28
Branding
C4E
C4E
AD7691
NOTES
Rev. 0 | Page 26 of 28
AD7691
NOTES
Rev. 0 | Page 27 of 28
AD7691
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06146-0-7/06(0)
Rev. 0 | Page 28 of 28